1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #ifndef __LINUX_KVM_RISCV_H 10 #define __LINUX_KVM_RISCV_H 11 12 #ifndef __ASSEMBLER__ 13 14 #include <linux/types.h> 15 #include <asm/bitsperlong.h> 16 #include <asm/ptrace.h> 17 18 #define __KVM_HAVE_IRQ_LINE 19 20 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 21 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 22 23 #define KVM_INTERRUPT_SET -1U 24 #define KVM_INTERRUPT_UNSET -2U 25 26 #define KVM_EXIT_FAIL_ENTRY_NO_VSFILE (1ULL << 0) 27 28 /* for KVM_GET_REGS and KVM_SET_REGS */ 29 struct kvm_regs { 30 }; 31 32 /* for KVM_GET_FPU and KVM_SET_FPU */ 33 struct kvm_fpu { 34 }; 35 36 /* KVM Debug exit structure */ 37 struct kvm_debug_exit_arch { 38 }; 39 40 /* for KVM_SET_GUEST_DEBUG */ 41 struct kvm_guest_debug_arch { 42 }; 43 44 /* definition of registers in kvm_run */ 45 struct kvm_sync_regs { 46 }; 47 48 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 49 struct kvm_sregs { 50 }; 51 52 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 53 struct kvm_riscv_config { 54 unsigned long isa; 55 unsigned long zicbom_block_size; 56 unsigned long mvendorid; 57 unsigned long marchid; 58 unsigned long mimpid; 59 unsigned long zicboz_block_size; 60 unsigned long satp_mode; 61 unsigned long zicbop_block_size; 62 }; 63 64 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 65 struct kvm_riscv_core { 66 struct user_regs_struct regs; 67 unsigned long mode; 68 }; 69 70 /* Possible privilege modes for kvm_riscv_core */ 71 #define KVM_RISCV_MODE_S 1 72 #define KVM_RISCV_MODE_U 0 73 74 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 75 struct kvm_riscv_csr { 76 unsigned long sstatus; 77 unsigned long sie; 78 unsigned long stvec; 79 unsigned long sscratch; 80 unsigned long sepc; 81 unsigned long scause; 82 unsigned long stval; 83 unsigned long sip; 84 unsigned long satp; 85 unsigned long scounteren; 86 unsigned long senvcfg; 87 }; 88 89 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 90 struct kvm_riscv_aia_csr { 91 unsigned long siselect; 92 unsigned long iprio1; 93 unsigned long iprio2; 94 unsigned long sieh; 95 unsigned long siph; 96 unsigned long iprio1h; 97 unsigned long iprio2h; 98 }; 99 100 /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 101 struct kvm_riscv_smstateen_csr { 102 unsigned long sstateen0; 103 }; 104 105 /* Zicfiss CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 106 struct kvm_riscv_zicfiss_csr { 107 unsigned long ssp; 108 }; 109 110 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 111 struct kvm_riscv_timer { 112 __u64 frequency; 113 __u64 time; 114 __u64 compare; 115 __u64 state; 116 }; 117 118 /* Possible states for kvm_riscv_timer */ 119 #define KVM_RISCV_TIMER_STATE_OFF 0 120 #define KVM_RISCV_TIMER_STATE_ON 1 121 122 /* 123 * ISA extension IDs specific to KVM. This is not the same as the host ISA 124 * extension IDs as that is internal to the host and should not be exposed 125 * to the guest. This should always be contiguous to keep the mapping simple 126 * in KVM implementation. 127 */ 128 enum KVM_RISCV_ISA_EXT_ID { 129 KVM_RISCV_ISA_EXT_A = 0, 130 KVM_RISCV_ISA_EXT_C, 131 KVM_RISCV_ISA_EXT_D, 132 KVM_RISCV_ISA_EXT_F, 133 KVM_RISCV_ISA_EXT_H, 134 KVM_RISCV_ISA_EXT_I, 135 KVM_RISCV_ISA_EXT_M, 136 KVM_RISCV_ISA_EXT_SVPBMT, 137 KVM_RISCV_ISA_EXT_SSTC, 138 KVM_RISCV_ISA_EXT_SVINVAL, 139 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 140 KVM_RISCV_ISA_EXT_ZICBOM, 141 KVM_RISCV_ISA_EXT_ZICBOZ, 142 KVM_RISCV_ISA_EXT_ZBB, 143 KVM_RISCV_ISA_EXT_SSAIA, 144 KVM_RISCV_ISA_EXT_V, 145 KVM_RISCV_ISA_EXT_SVNAPOT, 146 KVM_RISCV_ISA_EXT_ZBA, 147 KVM_RISCV_ISA_EXT_ZBS, 148 KVM_RISCV_ISA_EXT_ZICNTR, 149 KVM_RISCV_ISA_EXT_ZICSR, 150 KVM_RISCV_ISA_EXT_ZIFENCEI, 151 KVM_RISCV_ISA_EXT_ZIHPM, 152 KVM_RISCV_ISA_EXT_SMSTATEEN, 153 KVM_RISCV_ISA_EXT_ZICOND, 154 KVM_RISCV_ISA_EXT_ZBC, 155 KVM_RISCV_ISA_EXT_ZBKB, 156 KVM_RISCV_ISA_EXT_ZBKC, 157 KVM_RISCV_ISA_EXT_ZBKX, 158 KVM_RISCV_ISA_EXT_ZKND, 159 KVM_RISCV_ISA_EXT_ZKNE, 160 KVM_RISCV_ISA_EXT_ZKNH, 161 KVM_RISCV_ISA_EXT_ZKR, 162 KVM_RISCV_ISA_EXT_ZKSED, 163 KVM_RISCV_ISA_EXT_ZKSH, 164 KVM_RISCV_ISA_EXT_ZKT, 165 KVM_RISCV_ISA_EXT_ZVBB, 166 KVM_RISCV_ISA_EXT_ZVBC, 167 KVM_RISCV_ISA_EXT_ZVKB, 168 KVM_RISCV_ISA_EXT_ZVKG, 169 KVM_RISCV_ISA_EXT_ZVKNED, 170 KVM_RISCV_ISA_EXT_ZVKNHA, 171 KVM_RISCV_ISA_EXT_ZVKNHB, 172 KVM_RISCV_ISA_EXT_ZVKSED, 173 KVM_RISCV_ISA_EXT_ZVKSH, 174 KVM_RISCV_ISA_EXT_ZVKT, 175 KVM_RISCV_ISA_EXT_ZFH, 176 KVM_RISCV_ISA_EXT_ZFHMIN, 177 KVM_RISCV_ISA_EXT_ZIHINTNTL, 178 KVM_RISCV_ISA_EXT_ZVFH, 179 KVM_RISCV_ISA_EXT_ZVFHMIN, 180 KVM_RISCV_ISA_EXT_ZFA, 181 KVM_RISCV_ISA_EXT_ZTSO, 182 KVM_RISCV_ISA_EXT_ZACAS, 183 KVM_RISCV_ISA_EXT_SSCOFPMF, 184 KVM_RISCV_ISA_EXT_ZIMOP, 185 KVM_RISCV_ISA_EXT_ZCA, 186 KVM_RISCV_ISA_EXT_ZCB, 187 KVM_RISCV_ISA_EXT_ZCD, 188 KVM_RISCV_ISA_EXT_ZCF, 189 KVM_RISCV_ISA_EXT_ZCMOP, 190 KVM_RISCV_ISA_EXT_ZAWRS, 191 KVM_RISCV_ISA_EXT_SMNPM, 192 KVM_RISCV_ISA_EXT_SSNPM, 193 KVM_RISCV_ISA_EXT_SVADE, 194 KVM_RISCV_ISA_EXT_SVADU, 195 KVM_RISCV_ISA_EXT_SVVPTC, 196 KVM_RISCV_ISA_EXT_ZABHA, 197 KVM_RISCV_ISA_EXT_ZICCRSE, 198 KVM_RISCV_ISA_EXT_ZAAMO, 199 KVM_RISCV_ISA_EXT_ZALRSC, 200 KVM_RISCV_ISA_EXT_ZICBOP, 201 KVM_RISCV_ISA_EXT_ZFBFMIN, 202 KVM_RISCV_ISA_EXT_ZVFBFMIN, 203 KVM_RISCV_ISA_EXT_ZVFBFWMA, 204 KVM_RISCV_ISA_EXT_ZCLSD, 205 KVM_RISCV_ISA_EXT_ZILSD, 206 KVM_RISCV_ISA_EXT_ZALASR, 207 KVM_RISCV_ISA_EXT_ZICFILP, 208 KVM_RISCV_ISA_EXT_ZICFISS, 209 KVM_RISCV_ISA_EXT_MAX, 210 }; 211 212 /* 213 * SBI extension IDs specific to KVM. This is not the same as the SBI 214 * extension IDs defined by the RISC-V SBI specification. 215 */ 216 enum KVM_RISCV_SBI_EXT_ID { 217 KVM_RISCV_SBI_EXT_V01 = 0, 218 KVM_RISCV_SBI_EXT_TIME, 219 KVM_RISCV_SBI_EXT_IPI, 220 KVM_RISCV_SBI_EXT_RFENCE, 221 KVM_RISCV_SBI_EXT_SRST, 222 KVM_RISCV_SBI_EXT_HSM, 223 KVM_RISCV_SBI_EXT_PMU, 224 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 225 KVM_RISCV_SBI_EXT_VENDOR, 226 KVM_RISCV_SBI_EXT_DBCN, 227 KVM_RISCV_SBI_EXT_STA, 228 KVM_RISCV_SBI_EXT_SUSP, 229 KVM_RISCV_SBI_EXT_FWFT, 230 KVM_RISCV_SBI_EXT_MPXY, 231 KVM_RISCV_SBI_EXT_MAX, 232 }; 233 234 /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 235 struct kvm_riscv_sbi_sta { 236 unsigned long shmem_lo; 237 unsigned long shmem_hi; 238 }; 239 240 struct kvm_riscv_sbi_fwft_feature { 241 unsigned long enable; 242 unsigned long flags; 243 unsigned long value; 244 }; 245 246 /* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 247 struct kvm_riscv_sbi_fwft { 248 struct kvm_riscv_sbi_fwft_feature misaligned_deleg; 249 struct kvm_riscv_sbi_fwft_feature pointer_masking; 250 struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating; 251 struct kvm_riscv_sbi_fwft_feature landing_pad; 252 struct kvm_riscv_sbi_fwft_feature shadow_stack; 253 }; 254 255 /* If you need to interpret the index values, here is the key: */ 256 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 257 #define KVM_REG_RISCV_TYPE_SHIFT 24 258 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 259 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 260 261 /* Config registers are mapped as type 1 */ 262 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 263 #define KVM_REG_RISCV_CONFIG_REG(name) \ 264 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 265 266 /* Core registers are mapped as type 2 */ 267 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 268 #define KVM_REG_RISCV_CORE_REG(name) \ 269 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 270 271 /* Control and status registers are mapped as type 3 */ 272 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 273 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 274 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 275 #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 276 #define KVM_REG_RISCV_CSR_ZICFISS (0x3 << KVM_REG_RISCV_SUBTYPE_SHIFT) 277 #define KVM_REG_RISCV_CSR_REG(name) \ 278 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 279 #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 280 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 281 #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ 282 (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) 283 #define KVM_REG_RISCV_CSR_ZICFISS_REG(name) \ 284 (offsetof(struct kvm_riscv_zicfiss_csr, name) / sizeof(unsigned long)) 285 286 /* Timer registers are mapped as type 4 */ 287 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 288 #define KVM_REG_RISCV_TIMER_REG(name) \ 289 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 290 291 /* F extension registers are mapped as type 5 */ 292 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 293 #define KVM_REG_RISCV_FP_F_REG(name) \ 294 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 295 296 /* D extension registers are mapped as type 6 */ 297 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 298 #define KVM_REG_RISCV_FP_D_REG(name) \ 299 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 300 301 /* ISA Extension registers are mapped as type 7 */ 302 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 303 #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 304 #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 305 #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 306 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \ 307 ((__ext_id) / __BITS_PER_LONG) 308 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \ 309 (1UL << ((__ext_id) % __BITS_PER_LONG)) 310 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST \ 311 KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) 312 313 /* SBI extension registers are mapped as type 8 */ 314 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 315 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 316 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 317 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 318 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 319 ((__ext_id) / __BITS_PER_LONG) 320 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 321 (1UL << ((__ext_id) % __BITS_PER_LONG)) 322 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 323 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 324 325 /* V extension registers are mapped as type 9 */ 326 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 327 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 328 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 329 #define KVM_REG_RISCV_VECTOR_REG(n) \ 330 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 331 332 /* Registers for specific SBI extensions are mapped as type 10 */ 333 #define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) 334 #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 335 #define KVM_REG_RISCV_SBI_STA_REG(name) \ 336 (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) 337 #define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 338 #define KVM_REG_RISCV_SBI_FWFT_REG(name) \ 339 (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) 340 341 /* Device Control API: RISC-V AIA */ 342 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 343 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 344 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 345 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 346 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 347 348 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 349 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 350 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 351 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 352 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 353 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 354 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 355 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 356 357 /* 358 * Modes of RISC-V AIA device: 359 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 360 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 361 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 362 * available otherwise fallback to trap-n-emulation 363 */ 364 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 365 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 366 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 367 368 #define KVM_DEV_RISCV_AIA_IDS_MIN 63 369 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 370 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 371 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 372 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 373 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 374 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 375 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 376 377 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 378 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 379 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 380 #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 381 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 382 383 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 384 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 385 386 /* 387 * The device attribute type contains the memory mapped offset of the 388 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 389 */ 390 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 391 392 /* 393 * The lower 12-bits of the device attribute type contains the iselect 394 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 395 * bits contains the VCPU id. 396 */ 397 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 398 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 399 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 400 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 401 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 402 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 403 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 404 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 405 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 406 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 407 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 408 409 /* One single KVM irqchip, ie. the AIA */ 410 #define KVM_NR_IRQCHIPS 1 411 412 #endif 413 414 #endif /* __LINUX_KVM_RISCV_H */ 415