xref: /linux/arch/riscv/include/asm/xor.h (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2021 SiFive
4  */
5 
6 #include <linux/hardirq.h>
7 #include <asm-generic/xor.h>
8 #ifdef CONFIG_RISCV_ISA_V
9 #include <asm/vector.h>
10 #include <asm/switch_to.h>
11 #include <asm/asm-prototypes.h>
12 
13 static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1,
14 			 const unsigned long *__restrict p2)
15 {
16 	kernel_vector_begin();
17 	xor_regs_2_(bytes, p1, p2);
18 	kernel_vector_end();
19 }
20 
21 static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1,
22 			 const unsigned long *__restrict p2,
23 			 const unsigned long *__restrict p3)
24 {
25 	kernel_vector_begin();
26 	xor_regs_3_(bytes, p1, p2, p3);
27 	kernel_vector_end();
28 }
29 
30 static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1,
31 			 const unsigned long *__restrict p2,
32 			 const unsigned long *__restrict p3,
33 			 const unsigned long *__restrict p4)
34 {
35 	kernel_vector_begin();
36 	xor_regs_4_(bytes, p1, p2, p3, p4);
37 	kernel_vector_end();
38 }
39 
40 static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1,
41 			 const unsigned long *__restrict p2,
42 			 const unsigned long *__restrict p3,
43 			 const unsigned long *__restrict p4,
44 			 const unsigned long *__restrict p5)
45 {
46 	kernel_vector_begin();
47 	xor_regs_5_(bytes, p1, p2, p3, p4, p5);
48 	kernel_vector_end();
49 }
50 
51 static struct xor_block_template xor_block_rvv = {
52 	.name = "rvv",
53 	.do_2 = xor_vector_2,
54 	.do_3 = xor_vector_3,
55 	.do_4 = xor_vector_4,
56 	.do_5 = xor_vector_5
57 };
58 
59 #undef XOR_TRY_TEMPLATES
60 #define XOR_TRY_TEMPLATES           \
61 	do {        \
62 		xor_speed(&xor_block_8regs);    \
63 		xor_speed(&xor_block_32regs);    \
64 		if (has_vector()) { \
65 			xor_speed(&xor_block_rvv);\
66 		} \
67 	} while (0)
68 #endif
69