1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2020 SiFive 4 */ 5 6 #ifndef __ASM_RISCV_VECTOR_H 7 #define __ASM_RISCV_VECTOR_H 8 9 #include <linux/types.h> 10 #include <uapi/asm-generic/errno.h> 11 12 #ifdef CONFIG_RISCV_ISA_V 13 14 #include <asm/hwcap.h> 15 #include <asm/csr.h> 16 17 extern unsigned long riscv_v_vsize; 18 int riscv_v_setup_vsize(void); 19 20 static __always_inline bool has_vector(void) 21 { 22 return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); 23 } 24 25 static __always_inline void riscv_v_enable(void) 26 { 27 csr_set(CSR_SSTATUS, SR_VS); 28 } 29 30 static __always_inline void riscv_v_disable(void) 31 { 32 csr_clear(CSR_SSTATUS, SR_VS); 33 } 34 35 #else /* ! CONFIG_RISCV_ISA_V */ 36 37 struct pt_regs; 38 39 static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } 40 static __always_inline bool has_vector(void) { return false; } 41 #define riscv_v_vsize (0) 42 43 #endif /* CONFIG_RISCV_ISA_V */ 44 45 #endif /* ! __ASM_RISCV_VECTOR_H */ 46