1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2020 SiFive 4 */ 5 6 #ifndef __ASM_RISCV_VECTOR_H 7 #define __ASM_RISCV_VECTOR_H 8 9 #include <linux/types.h> 10 11 #ifdef CONFIG_RISCV_ISA_V 12 13 #include <asm/hwcap.h> 14 #include <asm/csr.h> 15 16 static __always_inline bool has_vector(void) 17 { 18 return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); 19 } 20 21 static __always_inline void riscv_v_enable(void) 22 { 23 csr_set(CSR_SSTATUS, SR_VS); 24 } 25 26 static __always_inline void riscv_v_disable(void) 27 { 28 csr_clear(CSR_SSTATUS, SR_VS); 29 } 30 31 #else /* ! CONFIG_RISCV_ISA_V */ 32 33 static __always_inline bool has_vector(void) { return false; } 34 35 #endif /* CONFIG_RISCV_ISA_V */ 36 37 #endif /* ! __ASM_RISCV_VECTOR_H */ 38