xref: /linux/arch/riscv/include/asm/suspend.h (revision b4db9f840283caca0d904436f187ef56a9126eaa)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2021 Western Digital Corporation or its affiliates.
4  * Copyright (c) 2022 Ventana Micro Systems Inc.
5  */
6 
7 #ifndef _ASM_RISCV_SUSPEND_H
8 #define _ASM_RISCV_SUSPEND_H
9 
10 #include <asm/ptrace.h>
11 
12 struct suspend_context {
13 	/* Saved and restored by low-level functions */
14 	struct pt_regs regs;
15 	/* Saved and restored by high-level functions */
16 	unsigned long scratch;
17 	unsigned long envcfg;
18 	unsigned long tvec;
19 	unsigned long ie;
20 #ifdef CONFIG_MMU
21 	unsigned long satp;
22 #endif
23 };
24 
25 /*
26  * Used by hibernation core and cleared during resume sequence
27  */
28 extern int in_suspend;
29 
30 /* Low-level CPU suspend entry function */
31 int __cpu_suspend_enter(struct suspend_context *context);
32 
33 /* High-level CPU suspend which will save context and call finish() */
34 int cpu_suspend(unsigned long arg,
35 		int (*finish)(unsigned long arg,
36 			      unsigned long entry,
37 			      unsigned long context));
38 
39 /* Low-level CPU resume entry function */
40 int __cpu_resume_enter(unsigned long hartid, unsigned long context);
41 
42 /* Used to save and restore the CSRs */
43 void suspend_save_csrs(struct suspend_context *context);
44 void suspend_restore_csrs(struct suspend_context *context);
45 
46 /* Low-level API to support hibernation */
47 int swsusp_arch_suspend(void);
48 int swsusp_arch_resume(void);
49 int arch_hibernation_header_save(void *addr, unsigned int max_size);
50 int arch_hibernation_header_restore(void *addr);
51 int __hibernate_cpu_resume(void);
52 
53 /* Used to resume on the CPU we hibernated on */
54 int hibernate_resume_nonboot_cpu_disable(void);
55 
56 asmlinkage void hibernate_restore_image(unsigned long resume_satp, unsigned long satp_temp,
57 					unsigned long cpu_resume);
58 asmlinkage int hibernate_core_restore_code(void);
59 bool riscv_sbi_hsm_is_supported(void);
60 bool riscv_sbi_suspend_state_is_valid(u32 state);
61 int riscv_sbi_hart_suspend(u32 state);
62 #endif
63