1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 */ 6 7 #ifndef _ASM_RISCV_SBI_H 8 #define _ASM_RISCV_SBI_H 9 10 #include <linux/types.h> 11 #include <linux/cpumask.h> 12 13 #ifdef CONFIG_RISCV_SBI 14 enum sbi_ext_id { 15 #ifdef CONFIG_RISCV_SBI_V01 16 SBI_EXT_0_1_SET_TIMER = 0x0, 17 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, 18 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, 19 SBI_EXT_0_1_CLEAR_IPI = 0x3, 20 SBI_EXT_0_1_SEND_IPI = 0x4, 21 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, 22 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, 23 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, 24 SBI_EXT_0_1_SHUTDOWN = 0x8, 25 #endif 26 SBI_EXT_BASE = 0x10, 27 SBI_EXT_TIME = 0x54494D45, 28 SBI_EXT_IPI = 0x735049, 29 SBI_EXT_RFENCE = 0x52464E43, 30 SBI_EXT_HSM = 0x48534D, 31 SBI_EXT_SRST = 0x53525354, 32 SBI_EXT_PMU = 0x504D55, 33 SBI_EXT_DBCN = 0x4442434E, 34 35 /* Experimentals extensions must lie within this range */ 36 SBI_EXT_EXPERIMENTAL_START = 0x08000000, 37 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF, 38 39 /* Vendor extensions must lie within this range */ 40 SBI_EXT_VENDOR_START = 0x09000000, 41 SBI_EXT_VENDOR_END = 0x09FFFFFF, 42 }; 43 44 enum sbi_ext_base_fid { 45 SBI_EXT_BASE_GET_SPEC_VERSION = 0, 46 SBI_EXT_BASE_GET_IMP_ID, 47 SBI_EXT_BASE_GET_IMP_VERSION, 48 SBI_EXT_BASE_PROBE_EXT, 49 SBI_EXT_BASE_GET_MVENDORID, 50 SBI_EXT_BASE_GET_MARCHID, 51 SBI_EXT_BASE_GET_MIMPID, 52 }; 53 54 enum sbi_ext_time_fid { 55 SBI_EXT_TIME_SET_TIMER = 0, 56 }; 57 58 enum sbi_ext_ipi_fid { 59 SBI_EXT_IPI_SEND_IPI = 0, 60 }; 61 62 enum sbi_ext_rfence_fid { 63 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, 64 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, 65 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, 66 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, 67 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, 68 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, 69 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, 70 }; 71 72 enum sbi_ext_hsm_fid { 73 SBI_EXT_HSM_HART_START = 0, 74 SBI_EXT_HSM_HART_STOP, 75 SBI_EXT_HSM_HART_STATUS, 76 SBI_EXT_HSM_HART_SUSPEND, 77 }; 78 79 enum sbi_hsm_hart_state { 80 SBI_HSM_STATE_STARTED = 0, 81 SBI_HSM_STATE_STOPPED, 82 SBI_HSM_STATE_START_PENDING, 83 SBI_HSM_STATE_STOP_PENDING, 84 SBI_HSM_STATE_SUSPENDED, 85 SBI_HSM_STATE_SUSPEND_PENDING, 86 SBI_HSM_STATE_RESUME_PENDING, 87 }; 88 89 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff 90 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 91 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000 92 93 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 94 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE 95 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK 96 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT 97 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ 98 SBI_HSM_SUSP_PLAT_BASE) 99 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ 100 SBI_HSM_SUSP_BASE_MASK) 101 102 enum sbi_ext_srst_fid { 103 SBI_EXT_SRST_RESET = 0, 104 }; 105 106 enum sbi_srst_reset_type { 107 SBI_SRST_RESET_TYPE_SHUTDOWN = 0, 108 SBI_SRST_RESET_TYPE_COLD_REBOOT, 109 SBI_SRST_RESET_TYPE_WARM_REBOOT, 110 }; 111 112 enum sbi_srst_reset_reason { 113 SBI_SRST_RESET_REASON_NONE = 0, 114 SBI_SRST_RESET_REASON_SYS_FAILURE, 115 }; 116 117 enum sbi_ext_pmu_fid { 118 SBI_EXT_PMU_NUM_COUNTERS = 0, 119 SBI_EXT_PMU_COUNTER_GET_INFO, 120 SBI_EXT_PMU_COUNTER_CFG_MATCH, 121 SBI_EXT_PMU_COUNTER_START, 122 SBI_EXT_PMU_COUNTER_STOP, 123 SBI_EXT_PMU_COUNTER_FW_READ, 124 }; 125 126 union sbi_pmu_ctr_info { 127 unsigned long value; 128 struct { 129 unsigned long csr:12; 130 unsigned long width:6; 131 #if __riscv_xlen == 32 132 unsigned long reserved:13; 133 #else 134 unsigned long reserved:45; 135 #endif 136 unsigned long type:1; 137 }; 138 }; 139 140 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) 141 #define RISCV_PMU_RAW_EVENT_IDX 0x20000 142 143 /** General pmu event codes specified in SBI PMU extension */ 144 enum sbi_pmu_hw_generic_events_t { 145 SBI_PMU_HW_NO_EVENT = 0, 146 SBI_PMU_HW_CPU_CYCLES = 1, 147 SBI_PMU_HW_INSTRUCTIONS = 2, 148 SBI_PMU_HW_CACHE_REFERENCES = 3, 149 SBI_PMU_HW_CACHE_MISSES = 4, 150 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, 151 SBI_PMU_HW_BRANCH_MISSES = 6, 152 SBI_PMU_HW_BUS_CYCLES = 7, 153 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, 154 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, 155 SBI_PMU_HW_REF_CPU_CYCLES = 10, 156 157 SBI_PMU_HW_GENERAL_MAX, 158 }; 159 160 /** 161 * Special "firmware" events provided by the firmware, even if the hardware 162 * does not support performance events. These events are encoded as a raw 163 * event type in Linux kernel perf framework. 164 */ 165 enum sbi_pmu_fw_generic_events_t { 166 SBI_PMU_FW_MISALIGNED_LOAD = 0, 167 SBI_PMU_FW_MISALIGNED_STORE = 1, 168 SBI_PMU_FW_ACCESS_LOAD = 2, 169 SBI_PMU_FW_ACCESS_STORE = 3, 170 SBI_PMU_FW_ILLEGAL_INSN = 4, 171 SBI_PMU_FW_SET_TIMER = 5, 172 SBI_PMU_FW_IPI_SENT = 6, 173 SBI_PMU_FW_IPI_RCVD = 7, 174 SBI_PMU_FW_FENCE_I_SENT = 8, 175 SBI_PMU_FW_FENCE_I_RCVD = 9, 176 SBI_PMU_FW_SFENCE_VMA_SENT = 10, 177 SBI_PMU_FW_SFENCE_VMA_RCVD = 11, 178 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, 179 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, 180 181 SBI_PMU_FW_HFENCE_GVMA_SENT = 14, 182 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, 183 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, 184 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, 185 186 SBI_PMU_FW_HFENCE_VVMA_SENT = 18, 187 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, 188 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, 189 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, 190 SBI_PMU_FW_MAX, 191 }; 192 193 /* SBI PMU event types */ 194 enum sbi_pmu_event_type { 195 SBI_PMU_EVENT_TYPE_HW = 0x0, 196 SBI_PMU_EVENT_TYPE_CACHE = 0x1, 197 SBI_PMU_EVENT_TYPE_RAW = 0x2, 198 SBI_PMU_EVENT_TYPE_FW = 0xf, 199 }; 200 201 /* SBI PMU event types */ 202 enum sbi_pmu_ctr_type { 203 SBI_PMU_CTR_TYPE_HW = 0x0, 204 SBI_PMU_CTR_TYPE_FW, 205 }; 206 207 /* Helper macros to decode event idx */ 208 #define SBI_PMU_EVENT_IDX_OFFSET 20 209 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF 210 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF 211 #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 212 #define SBI_PMU_EVENT_RAW_IDX 0x20000 213 #define SBI_PMU_FIXED_CTR_MASK 0x07 214 215 #define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 216 #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 217 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 218 219 #define SBI_PMU_EVENT_CACHE_ID_SHIFT 3 220 #define SBI_PMU_EVENT_CACHE_OP_SHIFT 1 221 222 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF 223 224 /* Flags defined for config matching function */ 225 #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) 226 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) 227 #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) 228 #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) 229 #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) 230 #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) 231 #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) 232 #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) 233 234 /* Flags defined for counter start function */ 235 #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) 236 237 /* Flags defined for counter stop function */ 238 #define SBI_PMU_STOP_FLAG_RESET (1 << 0) 239 240 enum sbi_ext_dbcn_fid { 241 SBI_EXT_DBCN_CONSOLE_WRITE = 0, 242 SBI_EXT_DBCN_CONSOLE_READ = 1, 243 SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, 244 }; 245 246 #define SBI_SPEC_VERSION_DEFAULT 0x1 247 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 248 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 249 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 250 251 /* SBI return error codes */ 252 #define SBI_SUCCESS 0 253 #define SBI_ERR_FAILURE -1 254 #define SBI_ERR_NOT_SUPPORTED -2 255 #define SBI_ERR_INVALID_PARAM -3 256 #define SBI_ERR_DENIED -4 257 #define SBI_ERR_INVALID_ADDRESS -5 258 #define SBI_ERR_ALREADY_AVAILABLE -6 259 #define SBI_ERR_ALREADY_STARTED -7 260 #define SBI_ERR_ALREADY_STOPPED -8 261 262 extern unsigned long sbi_spec_version; 263 struct sbiret { 264 long error; 265 long value; 266 }; 267 268 void sbi_init(void); 269 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 270 unsigned long arg1, unsigned long arg2, 271 unsigned long arg3, unsigned long arg4, 272 unsigned long arg5); 273 274 void sbi_console_putchar(int ch); 275 int sbi_console_getchar(void); 276 long sbi_get_mvendorid(void); 277 long sbi_get_marchid(void); 278 long sbi_get_mimpid(void); 279 void sbi_set_timer(uint64_t stime_value); 280 void sbi_shutdown(void); 281 void sbi_send_ipi(unsigned int cpu); 282 int sbi_remote_fence_i(const struct cpumask *cpu_mask); 283 284 int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask, 285 unsigned long start, 286 unsigned long size, 287 unsigned long asid); 288 int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask, 289 unsigned long start, 290 unsigned long size); 291 int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask, 292 unsigned long start, 293 unsigned long size, 294 unsigned long vmid); 295 int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask, 296 unsigned long start, 297 unsigned long size); 298 int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, 299 unsigned long start, 300 unsigned long size, 301 unsigned long asid); 302 long sbi_probe_extension(int ext); 303 304 /* Check if current SBI specification version is 0.1 or not */ 305 static inline int sbi_spec_is_0_1(void) 306 { 307 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0; 308 } 309 310 /* Get the major version of SBI */ 311 static inline unsigned long sbi_major_version(void) 312 { 313 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) & 314 SBI_SPEC_VERSION_MAJOR_MASK; 315 } 316 317 /* Get the minor version of SBI */ 318 static inline unsigned long sbi_minor_version(void) 319 { 320 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; 321 } 322 323 /* Make SBI version */ 324 static inline unsigned long sbi_mk_version(unsigned long major, 325 unsigned long minor) 326 { 327 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << 328 SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; 329 } 330 331 int sbi_err_map_linux_errno(int err); 332 #else /* CONFIG_RISCV_SBI */ 333 static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } 334 static inline void sbi_init(void) {} 335 #endif /* CONFIG_RISCV_SBI */ 336 337 unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 338 unsigned long riscv_cached_marchid(unsigned int cpu_id); 339 unsigned long riscv_cached_mimpid(unsigned int cpu_id); 340 341 #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) 342 void sbi_ipi_init(void); 343 #else 344 static inline void sbi_ipi_init(void) { } 345 #endif 346 347 #endif /* _ASM_RISCV_SBI_H */ 348