1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 */ 6 7 #ifndef _ASM_RISCV_SBI_H 8 #define _ASM_RISCV_SBI_H 9 10 #include <linux/types.h> 11 #include <linux/cpumask.h> 12 13 #ifdef CONFIG_RISCV_SBI 14 enum sbi_ext_id { 15 #ifdef CONFIG_RISCV_SBI_V01 16 SBI_EXT_0_1_SET_TIMER = 0x0, 17 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, 18 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, 19 SBI_EXT_0_1_CLEAR_IPI = 0x3, 20 SBI_EXT_0_1_SEND_IPI = 0x4, 21 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, 22 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, 23 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, 24 SBI_EXT_0_1_SHUTDOWN = 0x8, 25 #endif 26 SBI_EXT_BASE = 0x10, 27 SBI_EXT_TIME = 0x54494D45, 28 SBI_EXT_IPI = 0x735049, 29 SBI_EXT_RFENCE = 0x52464E43, 30 SBI_EXT_HSM = 0x48534D, 31 SBI_EXT_SRST = 0x53525354, 32 SBI_EXT_SUSP = 0x53555350, 33 SBI_EXT_PMU = 0x504D55, 34 SBI_EXT_DBCN = 0x4442434E, 35 36 /* Experimentals extensions must lie within this range */ 37 SBI_EXT_EXPERIMENTAL_START = 0x08000000, 38 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF, 39 40 /* Vendor extensions must lie within this range */ 41 SBI_EXT_VENDOR_START = 0x09000000, 42 SBI_EXT_VENDOR_END = 0x09FFFFFF, 43 }; 44 45 enum sbi_ext_base_fid { 46 SBI_EXT_BASE_GET_SPEC_VERSION = 0, 47 SBI_EXT_BASE_GET_IMP_ID, 48 SBI_EXT_BASE_GET_IMP_VERSION, 49 SBI_EXT_BASE_PROBE_EXT, 50 SBI_EXT_BASE_GET_MVENDORID, 51 SBI_EXT_BASE_GET_MARCHID, 52 SBI_EXT_BASE_GET_MIMPID, 53 }; 54 55 enum sbi_ext_time_fid { 56 SBI_EXT_TIME_SET_TIMER = 0, 57 }; 58 59 enum sbi_ext_ipi_fid { 60 SBI_EXT_IPI_SEND_IPI = 0, 61 }; 62 63 enum sbi_ext_rfence_fid { 64 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, 65 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, 66 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, 67 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, 68 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, 69 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, 70 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, 71 }; 72 73 enum sbi_ext_hsm_fid { 74 SBI_EXT_HSM_HART_START = 0, 75 SBI_EXT_HSM_HART_STOP, 76 SBI_EXT_HSM_HART_STATUS, 77 SBI_EXT_HSM_HART_SUSPEND, 78 }; 79 80 enum sbi_hsm_hart_state { 81 SBI_HSM_STATE_STARTED = 0, 82 SBI_HSM_STATE_STOPPED, 83 SBI_HSM_STATE_START_PENDING, 84 SBI_HSM_STATE_STOP_PENDING, 85 SBI_HSM_STATE_SUSPENDED, 86 SBI_HSM_STATE_SUSPEND_PENDING, 87 SBI_HSM_STATE_RESUME_PENDING, 88 }; 89 90 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff 91 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 92 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000 93 94 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 95 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE 96 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK 97 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT 98 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ 99 SBI_HSM_SUSP_PLAT_BASE) 100 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ 101 SBI_HSM_SUSP_BASE_MASK) 102 103 enum sbi_ext_srst_fid { 104 SBI_EXT_SRST_RESET = 0, 105 }; 106 107 enum sbi_srst_reset_type { 108 SBI_SRST_RESET_TYPE_SHUTDOWN = 0, 109 SBI_SRST_RESET_TYPE_COLD_REBOOT, 110 SBI_SRST_RESET_TYPE_WARM_REBOOT, 111 }; 112 113 enum sbi_srst_reset_reason { 114 SBI_SRST_RESET_REASON_NONE = 0, 115 SBI_SRST_RESET_REASON_SYS_FAILURE, 116 }; 117 118 enum sbi_ext_susp_fid { 119 SBI_EXT_SUSP_SYSTEM_SUSPEND = 0, 120 }; 121 122 enum sbi_ext_susp_sleep_type { 123 SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0, 124 }; 125 126 enum sbi_ext_pmu_fid { 127 SBI_EXT_PMU_NUM_COUNTERS = 0, 128 SBI_EXT_PMU_COUNTER_GET_INFO, 129 SBI_EXT_PMU_COUNTER_CFG_MATCH, 130 SBI_EXT_PMU_COUNTER_START, 131 SBI_EXT_PMU_COUNTER_STOP, 132 SBI_EXT_PMU_COUNTER_FW_READ, 133 }; 134 135 union sbi_pmu_ctr_info { 136 unsigned long value; 137 struct { 138 unsigned long csr:12; 139 unsigned long width:6; 140 #if __riscv_xlen == 32 141 unsigned long reserved:13; 142 #else 143 unsigned long reserved:45; 144 #endif 145 unsigned long type:1; 146 }; 147 }; 148 149 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) 150 #define RISCV_PMU_RAW_EVENT_IDX 0x20000 151 152 /** General pmu event codes specified in SBI PMU extension */ 153 enum sbi_pmu_hw_generic_events_t { 154 SBI_PMU_HW_NO_EVENT = 0, 155 SBI_PMU_HW_CPU_CYCLES = 1, 156 SBI_PMU_HW_INSTRUCTIONS = 2, 157 SBI_PMU_HW_CACHE_REFERENCES = 3, 158 SBI_PMU_HW_CACHE_MISSES = 4, 159 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, 160 SBI_PMU_HW_BRANCH_MISSES = 6, 161 SBI_PMU_HW_BUS_CYCLES = 7, 162 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, 163 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, 164 SBI_PMU_HW_REF_CPU_CYCLES = 10, 165 166 SBI_PMU_HW_GENERAL_MAX, 167 }; 168 169 /** 170 * Special "firmware" events provided by the firmware, even if the hardware 171 * does not support performance events. These events are encoded as a raw 172 * event type in Linux kernel perf framework. 173 */ 174 enum sbi_pmu_fw_generic_events_t { 175 SBI_PMU_FW_MISALIGNED_LOAD = 0, 176 SBI_PMU_FW_MISALIGNED_STORE = 1, 177 SBI_PMU_FW_ACCESS_LOAD = 2, 178 SBI_PMU_FW_ACCESS_STORE = 3, 179 SBI_PMU_FW_ILLEGAL_INSN = 4, 180 SBI_PMU_FW_SET_TIMER = 5, 181 SBI_PMU_FW_IPI_SENT = 6, 182 SBI_PMU_FW_IPI_RCVD = 7, 183 SBI_PMU_FW_FENCE_I_SENT = 8, 184 SBI_PMU_FW_FENCE_I_RCVD = 9, 185 SBI_PMU_FW_SFENCE_VMA_SENT = 10, 186 SBI_PMU_FW_SFENCE_VMA_RCVD = 11, 187 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, 188 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, 189 190 SBI_PMU_FW_HFENCE_GVMA_SENT = 14, 191 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, 192 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, 193 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, 194 195 SBI_PMU_FW_HFENCE_VVMA_SENT = 18, 196 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, 197 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, 198 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, 199 SBI_PMU_FW_MAX, 200 }; 201 202 /* SBI PMU event types */ 203 enum sbi_pmu_event_type { 204 SBI_PMU_EVENT_TYPE_HW = 0x0, 205 SBI_PMU_EVENT_TYPE_CACHE = 0x1, 206 SBI_PMU_EVENT_TYPE_RAW = 0x2, 207 SBI_PMU_EVENT_TYPE_FW = 0xf, 208 }; 209 210 /* SBI PMU event types */ 211 enum sbi_pmu_ctr_type { 212 SBI_PMU_CTR_TYPE_HW = 0x0, 213 SBI_PMU_CTR_TYPE_FW, 214 }; 215 216 /* Helper macros to decode event idx */ 217 #define SBI_PMU_EVENT_IDX_OFFSET 20 218 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF 219 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF 220 #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 221 #define SBI_PMU_EVENT_RAW_IDX 0x20000 222 #define SBI_PMU_FIXED_CTR_MASK 0x07 223 224 #define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 225 #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 226 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 227 228 #define SBI_PMU_EVENT_CACHE_ID_SHIFT 3 229 #define SBI_PMU_EVENT_CACHE_OP_SHIFT 1 230 231 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF 232 233 /* Flags defined for config matching function */ 234 #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) 235 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) 236 #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) 237 #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) 238 #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) 239 #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) 240 #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) 241 #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) 242 243 /* Flags defined for counter start function */ 244 #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) 245 246 /* Flags defined for counter stop function */ 247 #define SBI_PMU_STOP_FLAG_RESET (1 << 0) 248 249 enum sbi_ext_dbcn_fid { 250 SBI_EXT_DBCN_CONSOLE_WRITE = 0, 251 SBI_EXT_DBCN_CONSOLE_READ = 1, 252 SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, 253 }; 254 255 #define SBI_SPEC_VERSION_DEFAULT 0x1 256 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 257 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 258 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 259 260 /* SBI return error codes */ 261 #define SBI_SUCCESS 0 262 #define SBI_ERR_FAILURE -1 263 #define SBI_ERR_NOT_SUPPORTED -2 264 #define SBI_ERR_INVALID_PARAM -3 265 #define SBI_ERR_DENIED -4 266 #define SBI_ERR_INVALID_ADDRESS -5 267 #define SBI_ERR_ALREADY_AVAILABLE -6 268 #define SBI_ERR_ALREADY_STARTED -7 269 #define SBI_ERR_ALREADY_STOPPED -8 270 271 extern unsigned long sbi_spec_version; 272 struct sbiret { 273 long error; 274 long value; 275 }; 276 277 void sbi_init(void); 278 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 279 unsigned long arg1, unsigned long arg2, 280 unsigned long arg3, unsigned long arg4, 281 unsigned long arg5); 282 283 #ifdef CONFIG_RISCV_SBI_V01 284 void sbi_console_putchar(int ch); 285 int sbi_console_getchar(void); 286 #else 287 static inline void sbi_console_putchar(int ch) { } 288 static inline int sbi_console_getchar(void) { return -ENOENT; } 289 #endif 290 long sbi_get_mvendorid(void); 291 long sbi_get_marchid(void); 292 long sbi_get_mimpid(void); 293 void sbi_set_timer(uint64_t stime_value); 294 void sbi_shutdown(void); 295 void sbi_send_ipi(unsigned int cpu); 296 int sbi_remote_fence_i(const struct cpumask *cpu_mask); 297 298 int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask, 299 unsigned long start, 300 unsigned long size, 301 unsigned long asid); 302 int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask, 303 unsigned long start, 304 unsigned long size); 305 int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask, 306 unsigned long start, 307 unsigned long size, 308 unsigned long vmid); 309 int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask, 310 unsigned long start, 311 unsigned long size); 312 int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, 313 unsigned long start, 314 unsigned long size, 315 unsigned long asid); 316 long sbi_probe_extension(int ext); 317 318 /* Check if current SBI specification version is 0.1 or not */ 319 static inline int sbi_spec_is_0_1(void) 320 { 321 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0; 322 } 323 324 /* Get the major version of SBI */ 325 static inline unsigned long sbi_major_version(void) 326 { 327 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) & 328 SBI_SPEC_VERSION_MAJOR_MASK; 329 } 330 331 /* Get the minor version of SBI */ 332 static inline unsigned long sbi_minor_version(void) 333 { 334 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; 335 } 336 337 /* Make SBI version */ 338 static inline unsigned long sbi_mk_version(unsigned long major, 339 unsigned long minor) 340 { 341 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << 342 SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; 343 } 344 345 int sbi_err_map_linux_errno(int err); 346 347 extern bool sbi_debug_console_available; 348 int sbi_debug_console_write(const char *bytes, unsigned int num_bytes); 349 int sbi_debug_console_read(char *bytes, unsigned int num_bytes); 350 351 #else /* CONFIG_RISCV_SBI */ 352 static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } 353 static inline void sbi_init(void) {} 354 #endif /* CONFIG_RISCV_SBI */ 355 356 unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 357 unsigned long riscv_cached_marchid(unsigned int cpu_id); 358 unsigned long riscv_cached_mimpid(unsigned int cpu_id); 359 360 #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI) 361 void sbi_ipi_init(void); 362 #else 363 static inline void sbi_ipi_init(void) { } 364 #endif 365 366 #endif /* _ASM_RISCV_SBI_H */ 367