1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #ifdef CONFIG_RELOCATABLE 16 #define KERNEL_LINK_ADDR UL(0) 17 #else 18 #define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL) 19 #endif 20 #define KERN_VIRT_SIZE (UL(-1)) 21 #else 22 23 #define ADDRESS_SPACE_END (UL(-1)) 24 25 #ifdef CONFIG_64BIT 26 /* Leave 2GB for kernel and BPF at the end of the address space */ 27 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 28 #else 29 #define KERNEL_LINK_ADDR PAGE_OFFSET 30 #endif 31 32 /* Number of entries in the page global directory */ 33 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 34 /* Number of entries in the page table */ 35 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 36 37 /* 38 * Half of the kernel address space (1/4 of the entries of the page global 39 * directory) is for the direct mapping. 40 */ 41 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 42 43 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 44 #define VMALLOC_END PAGE_OFFSET 45 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 46 47 #define BPF_JIT_REGION_SIZE (SZ_128M) 48 #ifdef CONFIG_64BIT 49 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 50 #define BPF_JIT_REGION_END (MODULES_END) 51 #else 52 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 53 #define BPF_JIT_REGION_END (VMALLOC_END) 54 #endif 55 56 /* Modules always live before the kernel */ 57 #ifdef CONFIG_64BIT 58 /* This is used to define the end of the KASAN shadow region */ 59 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 60 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 61 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 62 #else 63 #define MODULES_VADDR VMALLOC_START 64 #define MODULES_END VMALLOC_END 65 #endif 66 67 /* 68 * Roughly size the vmemmap space to be large enough to fit enough 69 * struct pages to map half the virtual address space. Then 70 * position vmemmap directly below the VMALLOC region. 71 */ 72 #define VA_BITS_SV32 32 73 #ifdef CONFIG_64BIT 74 #define VA_BITS_SV39 39 75 #define VA_BITS_SV48 48 76 #define VA_BITS_SV57 57 77 78 #define VA_BITS (pgtable_l5_enabled ? \ 79 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 80 #else 81 #define VA_BITS VA_BITS_SV32 82 #endif 83 84 #define VMEMMAP_SHIFT \ 85 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 86 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 87 #define VMEMMAP_END VMALLOC_START 88 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 89 90 /* 91 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 92 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 93 */ 94 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) 95 96 #define PCI_IO_SIZE SZ_16M 97 #define PCI_IO_END VMEMMAP_START 98 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 99 100 #define FIXADDR_TOP PCI_IO_START 101 #ifdef CONFIG_64BIT 102 #define MAX_FDT_SIZE PMD_SIZE 103 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 104 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 105 #else 106 #define MAX_FDT_SIZE PGDIR_SIZE 107 #define FIX_FDT_SIZE MAX_FDT_SIZE 108 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 109 #endif 110 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 111 112 #endif 113 114 #ifndef __ASSEMBLY__ 115 116 #include <asm/page.h> 117 #include <asm/tlbflush.h> 118 #include <linux/mm_types.h> 119 #include <asm/compat.h> 120 #include <asm/cpufeature.h> 121 122 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 123 124 #ifdef CONFIG_64BIT 125 #include <asm/pgtable-64.h> 126 127 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) 128 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) 129 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) 130 131 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 132 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 133 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 134 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 135 #else 136 #include <asm/pgtable-32.h> 137 #endif /* CONFIG_64BIT */ 138 139 #include <linux/page_table_check.h> 140 141 #ifdef CONFIG_XIP_KERNEL 142 #define XIP_FIXUP(addr) ({ \ 143 extern char _sdata[], _start[], _end[]; \ 144 uintptr_t __rom_start_data = CONFIG_XIP_PHYS_ADDR \ 145 + (uintptr_t)&_sdata - (uintptr_t)&_start; \ 146 uintptr_t __rom_end_data = CONFIG_XIP_PHYS_ADDR \ 147 + (uintptr_t)&_end - (uintptr_t)&_start; \ 148 uintptr_t __a = (uintptr_t)(addr); \ 149 (__a >= __rom_start_data && __a < __rom_end_data) ? \ 150 __a - __rom_start_data + CONFIG_PHYS_RAM_BASE : __a; \ 151 }) 152 #else 153 #define XIP_FIXUP(addr) (addr) 154 #endif /* CONFIG_XIP_KERNEL */ 155 156 struct pt_alloc_ops { 157 pte_t *(*get_pte_virt)(phys_addr_t pa); 158 phys_addr_t (*alloc_pte)(uintptr_t va); 159 #ifndef __PAGETABLE_PMD_FOLDED 160 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 161 phys_addr_t (*alloc_pmd)(uintptr_t va); 162 pud_t *(*get_pud_virt)(phys_addr_t pa); 163 phys_addr_t (*alloc_pud)(uintptr_t va); 164 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 165 phys_addr_t (*alloc_p4d)(uintptr_t va); 166 #endif 167 }; 168 169 extern struct pt_alloc_ops pt_ops __meminitdata; 170 171 #ifdef CONFIG_MMU 172 /* Number of PGD entries that a user-mode program can use */ 173 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 174 175 /* Page protection bits */ 176 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 177 178 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 179 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 180 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 181 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 182 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 183 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 184 _PAGE_EXEC | _PAGE_WRITE) 185 186 #define PAGE_COPY PAGE_READ 187 #define PAGE_COPY_EXEC PAGE_READ_EXEC 188 #define PAGE_SHARED PAGE_WRITE 189 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 190 191 #define _PAGE_KERNEL (_PAGE_READ \ 192 | _PAGE_WRITE \ 193 | _PAGE_PRESENT \ 194 | _PAGE_ACCESSED \ 195 | _PAGE_DIRTY \ 196 | _PAGE_GLOBAL) 197 198 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 199 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 200 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 201 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 202 | _PAGE_EXEC) 203 204 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 205 206 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 207 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 208 209 extern pgd_t swapper_pg_dir[]; 210 extern pgd_t trampoline_pg_dir[]; 211 extern pgd_t early_pg_dir[]; 212 213 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 214 static inline int pmd_present(pmd_t pmd) 215 { 216 /* 217 * Checking for _PAGE_LEAF is needed too because: 218 * When splitting a THP, split_huge_page() will temporarily clear 219 * the present bit, in this situation, pmd_present() and 220 * pmd_trans_huge() still needs to return true. 221 */ 222 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 223 } 224 #else 225 static inline int pmd_present(pmd_t pmd) 226 { 227 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 228 } 229 #endif 230 231 static inline int pmd_none(pmd_t pmd) 232 { 233 return (pmd_val(pmd) == 0); 234 } 235 236 static inline int pmd_bad(pmd_t pmd) 237 { 238 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 239 } 240 241 #define pmd_leaf pmd_leaf 242 static inline bool pmd_leaf(pmd_t pmd) 243 { 244 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 245 } 246 247 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 248 { 249 WRITE_ONCE(*pmdp, pmd); 250 } 251 252 static inline void pmd_clear(pmd_t *pmdp) 253 { 254 set_pmd(pmdp, __pmd(0)); 255 } 256 257 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 258 { 259 unsigned long prot_val = pgprot_val(prot); 260 261 ALT_THEAD_PMA(prot_val); 262 263 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 264 } 265 266 static inline unsigned long _pgd_pfn(pgd_t pgd) 267 { 268 return __page_val_to_pfn(pgd_val(pgd)); 269 } 270 271 static inline struct page *pmd_page(pmd_t pmd) 272 { 273 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 274 } 275 276 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 277 { 278 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 279 } 280 281 static inline pte_t pmd_pte(pmd_t pmd) 282 { 283 return __pte(pmd_val(pmd)); 284 } 285 286 static inline pte_t pud_pte(pud_t pud) 287 { 288 return __pte(pud_val(pud)); 289 } 290 291 #ifdef CONFIG_RISCV_ISA_SVNAPOT 292 293 static __always_inline bool has_svnapot(void) 294 { 295 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 296 } 297 298 static inline unsigned long pte_napot(pte_t pte) 299 { 300 return pte_val(pte) & _PAGE_NAPOT; 301 } 302 303 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 304 { 305 int pos = order - 1 + _PAGE_PFN_SHIFT; 306 unsigned long napot_bit = BIT(pos); 307 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 308 309 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 310 } 311 312 #else 313 314 static __always_inline bool has_svnapot(void) { return false; } 315 316 static inline unsigned long pte_napot(pte_t pte) 317 { 318 return 0; 319 } 320 321 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 322 323 /* Yields the page frame number (PFN) of a page table entry */ 324 static inline unsigned long pte_pfn(pte_t pte) 325 { 326 unsigned long res = __page_val_to_pfn(pte_val(pte)); 327 328 if (has_svnapot() && pte_napot(pte)) 329 res = res & (res - 1UL); 330 331 return res; 332 } 333 334 #define pte_page(x) pfn_to_page(pte_pfn(x)) 335 336 /* Constructs a page table entry */ 337 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 338 { 339 unsigned long prot_val = pgprot_val(prot); 340 341 ALT_THEAD_PMA(prot_val); 342 343 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 344 } 345 346 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 347 348 #define pte_pgprot pte_pgprot 349 static inline pgprot_t pte_pgprot(pte_t pte) 350 { 351 unsigned long pfn = pte_pfn(pte); 352 353 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 354 } 355 356 static inline int pte_present(pte_t pte) 357 { 358 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 359 } 360 361 #define pte_accessible pte_accessible 362 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 363 { 364 if (pte_val(a) & _PAGE_PRESENT) 365 return true; 366 367 if ((pte_val(a) & _PAGE_PROT_NONE) && 368 atomic_read(&mm->tlb_flush_pending)) 369 return true; 370 371 return false; 372 } 373 374 static inline int pte_none(pte_t pte) 375 { 376 return (pte_val(pte) == 0); 377 } 378 379 static inline int pte_write(pte_t pte) 380 { 381 return pte_val(pte) & _PAGE_WRITE; 382 } 383 384 static inline int pte_exec(pte_t pte) 385 { 386 return pte_val(pte) & _PAGE_EXEC; 387 } 388 389 static inline int pte_user(pte_t pte) 390 { 391 return pte_val(pte) & _PAGE_USER; 392 } 393 394 static inline int pte_huge(pte_t pte) 395 { 396 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 397 } 398 399 static inline int pte_dirty(pte_t pte) 400 { 401 return pte_val(pte) & _PAGE_DIRTY; 402 } 403 404 static inline int pte_young(pte_t pte) 405 { 406 return pte_val(pte) & _PAGE_ACCESSED; 407 } 408 409 static inline int pte_special(pte_t pte) 410 { 411 return pte_val(pte) & _PAGE_SPECIAL; 412 } 413 414 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP 415 static inline int pte_devmap(pte_t pte) 416 { 417 return pte_val(pte) & _PAGE_DEVMAP; 418 } 419 #endif 420 421 /* static inline pte_t pte_rdprotect(pte_t pte) */ 422 423 static inline pte_t pte_wrprotect(pte_t pte) 424 { 425 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 426 } 427 428 /* static inline pte_t pte_mkread(pte_t pte) */ 429 430 static inline pte_t pte_mkwrite_novma(pte_t pte) 431 { 432 return __pte(pte_val(pte) | _PAGE_WRITE); 433 } 434 435 /* static inline pte_t pte_mkexec(pte_t pte) */ 436 437 static inline pte_t pte_mkdirty(pte_t pte) 438 { 439 return __pte(pte_val(pte) | _PAGE_DIRTY); 440 } 441 442 static inline pte_t pte_mkclean(pte_t pte) 443 { 444 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 445 } 446 447 static inline pte_t pte_mkyoung(pte_t pte) 448 { 449 return __pte(pte_val(pte) | _PAGE_ACCESSED); 450 } 451 452 static inline pte_t pte_mkold(pte_t pte) 453 { 454 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 455 } 456 457 static inline pte_t pte_mkspecial(pte_t pte) 458 { 459 return __pte(pte_val(pte) | _PAGE_SPECIAL); 460 } 461 462 static inline pte_t pte_mkdevmap(pte_t pte) 463 { 464 return __pte(pte_val(pte) | _PAGE_DEVMAP); 465 } 466 467 static inline pte_t pte_mkhuge(pte_t pte) 468 { 469 return pte; 470 } 471 472 #ifdef CONFIG_RISCV_ISA_SVNAPOT 473 #define pte_leaf_size(pte) (pte_napot(pte) ? \ 474 napot_cont_size(napot_cont_order(pte)) :\ 475 PAGE_SIZE) 476 #endif 477 478 #ifdef CONFIG_NUMA_BALANCING 479 /* 480 * See the comment in include/asm-generic/pgtable.h 481 */ 482 static inline int pte_protnone(pte_t pte) 483 { 484 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 485 } 486 487 static inline int pmd_protnone(pmd_t pmd) 488 { 489 return pte_protnone(pmd_pte(pmd)); 490 } 491 #endif 492 493 /* Modify page protection bits */ 494 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 495 { 496 unsigned long newprot_val = pgprot_val(newprot); 497 498 ALT_THEAD_PMA(newprot_val); 499 500 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 501 } 502 503 #define pgd_ERROR(e) \ 504 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 505 506 507 /* Commit new configuration to MMU hardware */ 508 static inline void update_mmu_cache_range(struct vm_fault *vmf, 509 struct vm_area_struct *vma, unsigned long address, 510 pte_t *ptep, unsigned int nr) 511 { 512 asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) 513 : : : : svvptc); 514 515 /* 516 * The kernel assumes that TLBs don't cache invalid entries, but 517 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 518 * cache flush; it is necessary even after writing invalid entries. 519 * Relying on flush_tlb_fix_spurious_fault would suffice, but 520 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 521 */ 522 while (nr--) 523 local_flush_tlb_page(address + nr * PAGE_SIZE); 524 525 svvptc:; 526 /* 527 * Svvptc guarantees that the new valid pte will be visible within 528 * a bounded timeframe, so when the uarch does not cache invalid 529 * entries, we don't have to do anything. 530 */ 531 } 532 #define update_mmu_cache(vma, addr, ptep) \ 533 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 534 535 #define update_mmu_tlb_range(vma, addr, ptep, nr) \ 536 update_mmu_cache_range(NULL, vma, addr, ptep, nr) 537 538 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 539 unsigned long address, pmd_t *pmdp) 540 { 541 pte_t *ptep = (pte_t *)pmdp; 542 543 update_mmu_cache(vma, address, ptep); 544 } 545 546 #define __HAVE_ARCH_PTE_SAME 547 static inline int pte_same(pte_t pte_a, pte_t pte_b) 548 { 549 return pte_val(pte_a) == pte_val(pte_b); 550 } 551 552 /* 553 * Certain architectures need to do special things when PTEs within 554 * a page table are directly modified. Thus, the following hook is 555 * made available. 556 */ 557 static inline void set_pte(pte_t *ptep, pte_t pteval) 558 { 559 WRITE_ONCE(*ptep, pteval); 560 } 561 562 void flush_icache_pte(struct mm_struct *mm, pte_t pte); 563 564 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval) 565 { 566 if (pte_present(pteval) && pte_exec(pteval)) 567 flush_icache_pte(mm, pteval); 568 569 set_pte(ptep, pteval); 570 } 571 572 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT 573 574 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 575 pte_t *ptep, pte_t pteval, unsigned int nr) 576 { 577 page_table_check_ptes_set(mm, ptep, pteval, nr); 578 579 for (;;) { 580 __set_pte_at(mm, ptep, pteval); 581 if (--nr == 0) 582 break; 583 ptep++; 584 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 585 } 586 } 587 #define set_ptes set_ptes 588 589 static inline void pte_clear(struct mm_struct *mm, 590 unsigned long addr, pte_t *ptep) 591 { 592 __set_pte_at(mm, ptep, __pte(0)); 593 } 594 595 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 596 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 597 pte_t *ptep, pte_t entry, int dirty); 598 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 599 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address, 600 pte_t *ptep); 601 602 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 603 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 604 unsigned long address, pte_t *ptep) 605 { 606 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 607 608 page_table_check_pte_clear(mm, pte); 609 610 return pte; 611 } 612 613 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 614 static inline void ptep_set_wrprotect(struct mm_struct *mm, 615 unsigned long address, pte_t *ptep) 616 { 617 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 618 } 619 620 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 621 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 622 unsigned long address, pte_t *ptep) 623 { 624 /* 625 * This comment is borrowed from x86, but applies equally to RISC-V: 626 * 627 * Clearing the accessed bit without a TLB flush 628 * doesn't cause data corruption. [ It could cause incorrect 629 * page aging and the (mistaken) reclaim of hot pages, but the 630 * chance of that should be relatively low. ] 631 * 632 * So as a performance optimization don't flush the TLB when 633 * clearing the accessed bit, it will eventually be flushed by 634 * a context switch or a VM operation anyway. [ In the rare 635 * event of it not getting flushed for a long time the delay 636 * shouldn't really matter because there's no real memory 637 * pressure for swapout to react to. ] 638 */ 639 return ptep_test_and_clear_young(vma, address, ptep); 640 } 641 642 #define pgprot_nx pgprot_nx 643 static inline pgprot_t pgprot_nx(pgprot_t _prot) 644 { 645 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC); 646 } 647 648 #define pgprot_noncached pgprot_noncached 649 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 650 { 651 unsigned long prot = pgprot_val(_prot); 652 653 prot &= ~_PAGE_MTMASK; 654 prot |= _PAGE_IO; 655 656 return __pgprot(prot); 657 } 658 659 #define pgprot_writecombine pgprot_writecombine 660 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 661 { 662 unsigned long prot = pgprot_val(_prot); 663 664 prot &= ~_PAGE_MTMASK; 665 prot |= _PAGE_NOCACHE; 666 667 return __pgprot(prot); 668 } 669 670 /* 671 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By 672 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in 673 * DT. 674 */ 675 #define arch_has_hw_pte_young arch_has_hw_pte_young 676 static inline bool arch_has_hw_pte_young(void) 677 { 678 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); 679 } 680 681 /* 682 * THP functions 683 */ 684 static inline pmd_t pte_pmd(pte_t pte) 685 { 686 return __pmd(pte_val(pte)); 687 } 688 689 static inline pud_t pte_pud(pte_t pte) 690 { 691 return __pud(pte_val(pte)); 692 } 693 694 static inline pmd_t pmd_mkhuge(pmd_t pmd) 695 { 696 return pmd; 697 } 698 699 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 700 { 701 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 702 } 703 704 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 705 706 static inline unsigned long pmd_pfn(pmd_t pmd) 707 { 708 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 709 } 710 711 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 712 713 #define pud_pfn pud_pfn 714 static inline unsigned long pud_pfn(pud_t pud) 715 { 716 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 717 } 718 719 #define pmd_pgprot pmd_pgprot 720 static inline pgprot_t pmd_pgprot(pmd_t pmd) 721 { 722 return pte_pgprot(pmd_pte(pmd)); 723 } 724 725 #define pud_pgprot pud_pgprot 726 static inline pgprot_t pud_pgprot(pud_t pud) 727 { 728 return pte_pgprot(pud_pte(pud)); 729 } 730 731 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 732 { 733 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 734 } 735 736 #define pmd_write pmd_write 737 static inline int pmd_write(pmd_t pmd) 738 { 739 return pte_write(pmd_pte(pmd)); 740 } 741 742 #define pud_write pud_write 743 static inline int pud_write(pud_t pud) 744 { 745 return pte_write(pud_pte(pud)); 746 } 747 748 #define pmd_dirty pmd_dirty 749 static inline int pmd_dirty(pmd_t pmd) 750 { 751 return pte_dirty(pmd_pte(pmd)); 752 } 753 754 #define pmd_young pmd_young 755 static inline int pmd_young(pmd_t pmd) 756 { 757 return pte_young(pmd_pte(pmd)); 758 } 759 760 static inline int pmd_user(pmd_t pmd) 761 { 762 return pte_user(pmd_pte(pmd)); 763 } 764 765 static inline pmd_t pmd_mkold(pmd_t pmd) 766 { 767 return pte_pmd(pte_mkold(pmd_pte(pmd))); 768 } 769 770 static inline pmd_t pmd_mkyoung(pmd_t pmd) 771 { 772 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 773 } 774 775 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 776 { 777 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 778 } 779 780 static inline pmd_t pmd_wrprotect(pmd_t pmd) 781 { 782 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 783 } 784 785 static inline pmd_t pmd_mkclean(pmd_t pmd) 786 { 787 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 788 } 789 790 static inline pmd_t pmd_mkdirty(pmd_t pmd) 791 { 792 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 793 } 794 795 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 796 { 797 return pte_pmd(pte_mkdevmap(pmd_pte(pmd))); 798 } 799 800 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 801 static inline bool pmd_special(pmd_t pmd) 802 { 803 return pte_special(pmd_pte(pmd)); 804 } 805 806 static inline pmd_t pmd_mkspecial(pmd_t pmd) 807 { 808 return pte_pmd(pte_mkspecial(pmd_pte(pmd))); 809 } 810 #endif 811 812 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 813 static inline bool pud_special(pud_t pud) 814 { 815 return pte_special(pud_pte(pud)); 816 } 817 818 static inline pud_t pud_mkspecial(pud_t pud) 819 { 820 return pte_pud(pte_mkspecial(pud_pte(pud))); 821 } 822 #endif 823 824 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 825 pmd_t *pmdp, pmd_t pmd) 826 { 827 page_table_check_pmd_set(mm, pmdp, pmd); 828 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd)); 829 } 830 831 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 832 pud_t *pudp, pud_t pud) 833 { 834 page_table_check_pud_set(mm, pudp, pud); 835 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud)); 836 } 837 838 #ifdef CONFIG_PAGE_TABLE_CHECK 839 static inline bool pte_user_accessible_page(pte_t pte) 840 { 841 return pte_present(pte) && pte_user(pte); 842 } 843 844 static inline bool pmd_user_accessible_page(pmd_t pmd) 845 { 846 return pmd_leaf(pmd) && pmd_user(pmd); 847 } 848 849 static inline bool pud_user_accessible_page(pud_t pud) 850 { 851 return pud_leaf(pud) && pud_user(pud); 852 } 853 #endif 854 855 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 856 static inline int pmd_trans_huge(pmd_t pmd) 857 { 858 return pmd_leaf(pmd); 859 } 860 861 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 862 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 863 unsigned long address, pmd_t *pmdp, 864 pmd_t entry, int dirty) 865 { 866 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 867 } 868 869 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 870 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 871 unsigned long address, pmd_t *pmdp) 872 { 873 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 874 } 875 876 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 877 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 878 unsigned long address, pmd_t *pmdp) 879 { 880 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 881 882 page_table_check_pmd_clear(mm, pmd); 883 884 return pmd; 885 } 886 887 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 888 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 889 unsigned long address, pmd_t *pmdp) 890 { 891 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 892 } 893 894 #define pmdp_establish pmdp_establish 895 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 896 unsigned long address, pmd_t *pmdp, pmd_t pmd) 897 { 898 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 899 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 900 } 901 902 #define pmdp_collapse_flush pmdp_collapse_flush 903 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 904 unsigned long address, pmd_t *pmdp); 905 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 906 907 /* 908 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 909 * are !pte_none() && !pte_present(). 910 * 911 * Format of swap PTE: 912 * bit 0: _PAGE_PRESENT (zero) 913 * bit 1 to 3: _PAGE_LEAF (zero) 914 * bit 5: _PAGE_PROT_NONE (zero) 915 * bit 6: exclusive marker 916 * bits 7 to 11: swap type 917 * bits 12 to XLEN-1: swap offset 918 */ 919 #define __SWP_TYPE_SHIFT 7 920 #define __SWP_TYPE_BITS 5 921 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 922 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 923 924 #define MAX_SWAPFILES_CHECK() \ 925 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 926 927 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 928 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 929 #define __swp_entry(type, offset) ((swp_entry_t) \ 930 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 931 ((offset) << __SWP_OFFSET_SHIFT) }) 932 933 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 934 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 935 936 static inline int pte_swp_exclusive(pte_t pte) 937 { 938 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 939 } 940 941 static inline pte_t pte_swp_mkexclusive(pte_t pte) 942 { 943 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 944 } 945 946 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 947 { 948 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 949 } 950 951 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 952 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 953 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 954 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 955 956 /* 957 * In the RV64 Linux scheme, we give the user half of the virtual-address space 958 * and give the kernel the other (upper) half. 959 */ 960 #ifdef CONFIG_64BIT 961 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 962 #else 963 #define KERN_VIRT_START FIXADDR_START 964 #endif 965 966 /* 967 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 968 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 969 * Task size is: 970 * - 0x9fc00000 (~2.5GB) for RV32. 971 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 972 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 973 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 974 * 975 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 976 * Instruction Set Manual Volume II: Privileged Architecture" states that 977 * "load and store effective addresses, which are 64bits, must have bits 978 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 979 * Similarly for SV57, bits 63–57 must be equal to bit 56. 980 */ 981 #ifdef CONFIG_64BIT 982 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 983 #define TASK_SIZE_MAX LONG_MAX 984 985 #ifdef CONFIG_COMPAT 986 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 987 #define TASK_SIZE (is_compat_task() ? \ 988 TASK_SIZE_32 : TASK_SIZE_64) 989 #else 990 #define TASK_SIZE TASK_SIZE_64 991 #endif 992 993 #else 994 #define TASK_SIZE FIXADDR_START 995 #endif 996 997 #else /* CONFIG_MMU */ 998 999 #define PAGE_SHARED __pgprot(0) 1000 #define PAGE_KERNEL __pgprot(0) 1001 #define swapper_pg_dir NULL 1002 #define TASK_SIZE _AC(-1, UL) 1003 #define VMALLOC_START _AC(0, UL) 1004 #define VMALLOC_END TASK_SIZE 1005 1006 #endif /* !CONFIG_MMU */ 1007 1008 extern char _start[]; 1009 extern void *_dtb_early_va; 1010 extern uintptr_t _dtb_early_pa; 1011 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 1012 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 1013 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 1014 #else 1015 #define dtb_early_va _dtb_early_va 1016 #define dtb_early_pa _dtb_early_pa 1017 #endif /* CONFIG_XIP_KERNEL */ 1018 extern u64 satp_mode; 1019 1020 void paging_init(void); 1021 void misc_mem_init(void); 1022 1023 /* 1024 * ZERO_PAGE is a global shared page that is always zero, 1025 * used for zero-mapped memory areas, etc. 1026 */ 1027 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 1028 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 1029 1030 /* 1031 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1032 * TLB flush will be required as a result of the "set". For example, use 1033 * in scenarios where it is known ahead of time that the routine is 1034 * setting non-present entries, or re-setting an existing entry to the 1035 * same value. Otherwise, use the typical "set" helpers and flush the 1036 * TLB. 1037 */ 1038 #define set_p4d_safe(p4dp, p4d) \ 1039 ({ \ 1040 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1041 set_p4d(p4dp, p4d); \ 1042 }) 1043 1044 #define set_pgd_safe(pgdp, pgd) \ 1045 ({ \ 1046 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1047 set_pgd(pgdp, pgd); \ 1048 }) 1049 #endif /* !__ASSEMBLY__ */ 1050 1051 #endif /* _ASM_RISCV_PGTABLE_H */ 1052