1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #ifdef CONFIG_RELOCATABLE 16 #define KERNEL_LINK_ADDR UL(0) 17 #else 18 #define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL) 19 #endif 20 #define KERN_VIRT_SIZE (UL(-1)) 21 #else 22 23 #define ADDRESS_SPACE_END (UL(-1)) 24 25 #ifdef CONFIG_64BIT 26 /* Leave 2GB for kernel and BPF at the end of the address space */ 27 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 28 #else 29 #define KERNEL_LINK_ADDR PAGE_OFFSET 30 #endif 31 32 /* Number of entries in the page global directory */ 33 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 34 /* Number of entries in the page table */ 35 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 36 37 /* 38 * Half of the kernel address space (1/4 of the entries of the page global 39 * directory) is for the direct mapping. 40 */ 41 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 42 43 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 44 #define VMALLOC_END PAGE_OFFSET 45 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 46 47 #define BPF_JIT_REGION_SIZE (SZ_128M) 48 #ifdef CONFIG_64BIT 49 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 50 #define BPF_JIT_REGION_END (MODULES_END) 51 #else 52 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 53 #define BPF_JIT_REGION_END (VMALLOC_END) 54 #endif 55 56 /* Modules always live before the kernel */ 57 #ifdef CONFIG_64BIT 58 /* This is used to define the end of the KASAN shadow region */ 59 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 60 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 61 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 62 #else 63 #define MODULES_VADDR VMALLOC_START 64 #define MODULES_END VMALLOC_END 65 #endif 66 67 /* 68 * Roughly size the vmemmap space to be large enough to fit enough 69 * struct pages to map half the virtual address space. Then 70 * position vmemmap directly below the VMALLOC region. 71 */ 72 #define VA_BITS_SV32 32 73 #ifdef CONFIG_64BIT 74 #define VA_BITS_SV39 39 75 #define VA_BITS_SV48 48 76 #define VA_BITS_SV57 57 77 78 #define VA_BITS (pgtable_l5_enabled ? \ 79 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 80 #else 81 #define VA_BITS VA_BITS_SV32 82 #endif 83 84 #define VMEMMAP_SHIFT \ 85 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 86 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 87 #define VMEMMAP_END VMALLOC_START 88 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 89 90 /* 91 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 92 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 93 */ 94 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) 95 96 #define PCI_IO_SIZE SZ_16M 97 #define PCI_IO_END VMEMMAP_START 98 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 99 100 #define FIXADDR_TOP PCI_IO_START 101 #ifdef CONFIG_64BIT 102 #define MAX_FDT_SIZE PMD_SIZE 103 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 104 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 105 #else 106 #define MAX_FDT_SIZE PGDIR_SIZE 107 #define FIX_FDT_SIZE MAX_FDT_SIZE 108 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 109 #endif 110 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 111 112 #endif 113 114 #ifndef __ASSEMBLER__ 115 116 #include <asm/page.h> 117 #include <asm/tlbflush.h> 118 #include <linux/mm_types.h> 119 #include <asm/compat.h> 120 #include <asm/cpufeature.h> 121 122 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 123 124 #ifdef CONFIG_64BIT 125 #include <asm/pgtable-64.h> 126 127 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1)) 128 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1)) 129 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1)) 130 131 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 132 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 133 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 134 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 135 #else 136 #include <asm/pgtable-32.h> 137 #endif /* CONFIG_64BIT */ 138 139 #include <linux/page_table_check.h> 140 141 #ifdef CONFIG_XIP_KERNEL 142 #define XIP_FIXUP(addr) ({ \ 143 extern char _sdata[], _start[], _end[]; \ 144 uintptr_t __rom_start_data = CONFIG_XIP_PHYS_ADDR \ 145 + (uintptr_t)&_sdata - (uintptr_t)&_start; \ 146 uintptr_t __rom_end_data = CONFIG_XIP_PHYS_ADDR \ 147 + (uintptr_t)&_end - (uintptr_t)&_start; \ 148 uintptr_t __a = (uintptr_t)(addr); \ 149 (__a >= __rom_start_data && __a < __rom_end_data) ? \ 150 __a - __rom_start_data + CONFIG_PHYS_RAM_BASE : __a; \ 151 }) 152 #else 153 #define XIP_FIXUP(addr) (addr) 154 #endif /* CONFIG_XIP_KERNEL */ 155 156 struct pt_alloc_ops { 157 pte_t *(*get_pte_virt)(phys_addr_t pa); 158 phys_addr_t (*alloc_pte)(uintptr_t va); 159 #ifndef __PAGETABLE_PMD_FOLDED 160 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 161 phys_addr_t (*alloc_pmd)(uintptr_t va); 162 pud_t *(*get_pud_virt)(phys_addr_t pa); 163 phys_addr_t (*alloc_pud)(uintptr_t va); 164 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 165 phys_addr_t (*alloc_p4d)(uintptr_t va); 166 #endif 167 }; 168 169 extern struct pt_alloc_ops pt_ops __meminitdata; 170 171 #ifdef CONFIG_MMU 172 /* Number of PGD entries that a user-mode program can use */ 173 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 174 175 /* Page protection bits */ 176 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 177 178 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 179 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 180 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 181 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 182 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 183 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 184 _PAGE_EXEC | _PAGE_WRITE) 185 186 #define PAGE_COPY PAGE_READ 187 #define PAGE_COPY_EXEC PAGE_READ_EXEC 188 #define PAGE_SHARED PAGE_WRITE 189 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 190 191 #define _PAGE_KERNEL (_PAGE_READ \ 192 | _PAGE_WRITE \ 193 | _PAGE_PRESENT \ 194 | _PAGE_ACCESSED \ 195 | _PAGE_DIRTY \ 196 | _PAGE_GLOBAL) 197 198 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 199 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 200 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 201 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 202 | _PAGE_EXEC) 203 204 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 205 206 #define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) 207 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 208 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 209 210 extern pgd_t swapper_pg_dir[]; 211 extern pgd_t trampoline_pg_dir[]; 212 extern pgd_t early_pg_dir[]; 213 214 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 215 static inline int pmd_present(pmd_t pmd) 216 { 217 /* 218 * Checking for _PAGE_LEAF is needed too because: 219 * When splitting a THP, split_huge_page() will temporarily clear 220 * the present bit, in this situation, pmd_present() and 221 * pmd_trans_huge() still needs to return true. 222 */ 223 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 224 } 225 #else 226 static inline int pmd_present(pmd_t pmd) 227 { 228 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 229 } 230 #endif 231 232 static inline int pmd_none(pmd_t pmd) 233 { 234 return (pmd_val(pmd) == 0); 235 } 236 237 static inline int pmd_bad(pmd_t pmd) 238 { 239 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 240 } 241 242 #define pmd_leaf pmd_leaf 243 static inline bool pmd_leaf(pmd_t pmd) 244 { 245 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 246 } 247 248 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 249 { 250 WRITE_ONCE(*pmdp, pmd); 251 } 252 253 static inline void pmd_clear(pmd_t *pmdp) 254 { 255 set_pmd(pmdp, __pmd(0)); 256 } 257 258 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 259 { 260 unsigned long prot_val = pgprot_val(prot); 261 262 ALT_THEAD_PMA(prot_val); 263 264 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 265 } 266 267 static inline unsigned long _pgd_pfn(pgd_t pgd) 268 { 269 return __page_val_to_pfn(pgd_val(pgd)); 270 } 271 272 static inline struct page *pmd_page(pmd_t pmd) 273 { 274 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 275 } 276 277 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 278 { 279 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 280 } 281 282 static inline pte_t pmd_pte(pmd_t pmd) 283 { 284 return __pte(pmd_val(pmd)); 285 } 286 287 static inline pte_t pud_pte(pud_t pud) 288 { 289 return __pte(pud_val(pud)); 290 } 291 292 #ifdef CONFIG_RISCV_ISA_SVNAPOT 293 294 static __always_inline bool has_svnapot(void) 295 { 296 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 297 } 298 299 static inline unsigned long pte_napot(pte_t pte) 300 { 301 return pte_val(pte) & _PAGE_NAPOT; 302 } 303 304 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 305 { 306 int pos = order - 1 + _PAGE_PFN_SHIFT; 307 unsigned long napot_bit = BIT(pos); 308 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 309 310 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 311 } 312 313 #else 314 315 static __always_inline bool has_svnapot(void) { return false; } 316 317 static inline unsigned long pte_napot(pte_t pte) 318 { 319 return 0; 320 } 321 322 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 323 324 /* Yields the page frame number (PFN) of a page table entry */ 325 static inline unsigned long pte_pfn(pte_t pte) 326 { 327 unsigned long res = __page_val_to_pfn(pte_val(pte)); 328 329 if (has_svnapot() && pte_napot(pte)) 330 res = res & (res - 1UL); 331 332 return res; 333 } 334 335 #define pte_page(x) pfn_to_page(pte_pfn(x)) 336 337 /* Constructs a page table entry */ 338 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 339 { 340 unsigned long prot_val = pgprot_val(prot); 341 342 ALT_THEAD_PMA(prot_val); 343 344 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 345 } 346 347 #define pte_pgprot pte_pgprot 348 static inline pgprot_t pte_pgprot(pte_t pte) 349 { 350 unsigned long pfn = pte_pfn(pte); 351 352 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 353 } 354 355 static inline int pte_present(pte_t pte) 356 { 357 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 358 } 359 360 #define pte_accessible pte_accessible 361 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 362 { 363 if (pte_val(a) & _PAGE_PRESENT) 364 return true; 365 366 if ((pte_val(a) & _PAGE_PROT_NONE) && 367 atomic_read(&mm->tlb_flush_pending)) 368 return true; 369 370 return false; 371 } 372 373 static inline int pte_none(pte_t pte) 374 { 375 return (pte_val(pte) == 0); 376 } 377 378 static inline int pte_write(pte_t pte) 379 { 380 return pte_val(pte) & _PAGE_WRITE; 381 } 382 383 static inline int pte_exec(pte_t pte) 384 { 385 return pte_val(pte) & _PAGE_EXEC; 386 } 387 388 static inline int pte_user(pte_t pte) 389 { 390 return pte_val(pte) & _PAGE_USER; 391 } 392 393 static inline int pte_huge(pte_t pte) 394 { 395 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 396 } 397 398 static inline int pte_dirty(pte_t pte) 399 { 400 return pte_val(pte) & _PAGE_DIRTY; 401 } 402 403 static inline int pte_young(pte_t pte) 404 { 405 return pte_val(pte) & _PAGE_ACCESSED; 406 } 407 408 static inline int pte_special(pte_t pte) 409 { 410 return pte_val(pte) & _PAGE_SPECIAL; 411 } 412 413 /* static inline pte_t pte_rdprotect(pte_t pte) */ 414 415 static inline pte_t pte_wrprotect(pte_t pte) 416 { 417 return __pte(pte_val(pte) & ~(_PAGE_WRITE)); 418 } 419 420 /* static inline pte_t pte_mkread(pte_t pte) */ 421 422 static inline pte_t pte_mkwrite_novma(pte_t pte) 423 { 424 return __pte(pte_val(pte) | _PAGE_WRITE); 425 } 426 427 /* static inline pte_t pte_mkexec(pte_t pte) */ 428 429 static inline pte_t pte_mkdirty(pte_t pte) 430 { 431 return __pte(pte_val(pte) | _PAGE_DIRTY); 432 } 433 434 static inline pte_t pte_mkclean(pte_t pte) 435 { 436 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 437 } 438 439 static inline pte_t pte_mkyoung(pte_t pte) 440 { 441 return __pte(pte_val(pte) | _PAGE_ACCESSED); 442 } 443 444 static inline pte_t pte_mkold(pte_t pte) 445 { 446 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 447 } 448 449 static inline pte_t pte_mkspecial(pte_t pte) 450 { 451 return __pte(pte_val(pte) | _PAGE_SPECIAL); 452 } 453 454 static inline pte_t pte_mkhuge(pte_t pte) 455 { 456 return pte; 457 } 458 459 #ifdef CONFIG_RISCV_ISA_SVNAPOT 460 #define pte_leaf_size(pte) (pte_napot(pte) ? \ 461 napot_cont_size(napot_cont_order(pte)) :\ 462 PAGE_SIZE) 463 #endif 464 465 #ifdef CONFIG_NUMA_BALANCING 466 /* 467 * See the comment in include/asm-generic/pgtable.h 468 */ 469 static inline int pte_protnone(pte_t pte) 470 { 471 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 472 } 473 474 static inline int pmd_protnone(pmd_t pmd) 475 { 476 return pte_protnone(pmd_pte(pmd)); 477 } 478 #endif 479 480 /* Modify page protection bits */ 481 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 482 { 483 unsigned long newprot_val = pgprot_val(newprot); 484 485 ALT_THEAD_PMA(newprot_val); 486 487 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 488 } 489 490 #define pgd_ERROR(e) \ 491 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 492 493 494 /* Commit new configuration to MMU hardware */ 495 static inline void update_mmu_cache_range(struct vm_fault *vmf, 496 struct vm_area_struct *vma, unsigned long address, 497 pte_t *ptep, unsigned int nr) 498 { 499 /* 500 * Svvptc guarantees that the new valid pte will be visible within 501 * a bounded timeframe, so when the uarch does not cache invalid 502 * entries, we don't have to do anything. 503 */ 504 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) 505 return; 506 507 /* 508 * The kernel assumes that TLBs don't cache invalid entries, but 509 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 510 * cache flush; it is necessary even after writing invalid entries. 511 * Relying on flush_tlb_fix_spurious_fault would suffice, but 512 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 513 */ 514 while (nr--) 515 local_flush_tlb_page(address + nr * PAGE_SIZE); 516 517 } 518 #define update_mmu_cache(vma, addr, ptep) \ 519 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 520 521 #define update_mmu_tlb_range(vma, addr, ptep, nr) \ 522 update_mmu_cache_range(NULL, vma, addr, ptep, nr) 523 524 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 525 unsigned long address, pmd_t *pmdp) 526 { 527 pte_t *ptep = (pte_t *)pmdp; 528 529 update_mmu_cache(vma, address, ptep); 530 } 531 532 #define __HAVE_ARCH_PTE_SAME 533 static inline int pte_same(pte_t pte_a, pte_t pte_b) 534 { 535 return pte_val(pte_a) == pte_val(pte_b); 536 } 537 538 /* 539 * Certain architectures need to do special things when PTEs within 540 * a page table are directly modified. Thus, the following hook is 541 * made available. 542 */ 543 static inline void set_pte(pte_t *ptep, pte_t pteval) 544 { 545 WRITE_ONCE(*ptep, pteval); 546 } 547 548 void flush_icache_pte(struct mm_struct *mm, pte_t pte); 549 550 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval) 551 { 552 if (pte_present(pteval) && pte_exec(pteval)) 553 flush_icache_pte(mm, pteval); 554 555 set_pte(ptep, pteval); 556 } 557 558 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT 559 560 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 561 pte_t *ptep, pte_t pteval, unsigned int nr) 562 { 563 page_table_check_ptes_set(mm, ptep, pteval, nr); 564 565 for (;;) { 566 __set_pte_at(mm, ptep, pteval); 567 if (--nr == 0) 568 break; 569 ptep++; 570 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 571 } 572 } 573 #define set_ptes set_ptes 574 575 static inline void pte_clear(struct mm_struct *mm, 576 unsigned long addr, pte_t *ptep) 577 { 578 __set_pte_at(mm, ptep, __pte(0)); 579 } 580 581 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 582 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 583 pte_t *ptep, pte_t entry, int dirty); 584 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 585 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address, 586 pte_t *ptep); 587 588 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 589 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 590 unsigned long address, pte_t *ptep) 591 { 592 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); 593 594 page_table_check_pte_clear(mm, pte); 595 596 return pte; 597 } 598 599 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 600 static inline void ptep_set_wrprotect(struct mm_struct *mm, 601 unsigned long address, pte_t *ptep) 602 { 603 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep); 604 } 605 606 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 607 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 608 unsigned long address, pte_t *ptep) 609 { 610 /* 611 * This comment is borrowed from x86, but applies equally to RISC-V: 612 * 613 * Clearing the accessed bit without a TLB flush 614 * doesn't cause data corruption. [ It could cause incorrect 615 * page aging and the (mistaken) reclaim of hot pages, but the 616 * chance of that should be relatively low. ] 617 * 618 * So as a performance optimization don't flush the TLB when 619 * clearing the accessed bit, it will eventually be flushed by 620 * a context switch or a VM operation anyway. [ In the rare 621 * event of it not getting flushed for a long time the delay 622 * shouldn't really matter because there's no real memory 623 * pressure for swapout to react to. ] 624 */ 625 return ptep_test_and_clear_young(vma, address, ptep); 626 } 627 628 #define pgprot_nx pgprot_nx 629 static inline pgprot_t pgprot_nx(pgprot_t _prot) 630 { 631 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC); 632 } 633 634 #define pgprot_noncached pgprot_noncached 635 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 636 { 637 unsigned long prot = pgprot_val(_prot); 638 639 prot &= ~_PAGE_MTMASK; 640 prot |= _PAGE_IO; 641 642 return __pgprot(prot); 643 } 644 645 #define pgprot_writecombine pgprot_writecombine 646 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 647 { 648 unsigned long prot = pgprot_val(_prot); 649 650 prot &= ~_PAGE_MTMASK; 651 prot |= _PAGE_NOCACHE; 652 653 return __pgprot(prot); 654 } 655 656 #define pgprot_dmacoherent pgprot_writecombine 657 658 /* 659 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By 660 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in 661 * DT. 662 */ 663 #define arch_has_hw_pte_young arch_has_hw_pte_young 664 static inline bool arch_has_hw_pte_young(void) 665 { 666 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); 667 } 668 669 /* 670 * THP functions 671 */ 672 static inline pmd_t pte_pmd(pte_t pte) 673 { 674 return __pmd(pte_val(pte)); 675 } 676 677 static inline pud_t pte_pud(pte_t pte) 678 { 679 return __pud(pte_val(pte)); 680 } 681 682 static inline pmd_t pmd_mkhuge(pmd_t pmd) 683 { 684 return pmd; 685 } 686 687 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 688 { 689 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 690 } 691 692 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 693 694 static inline unsigned long pmd_pfn(pmd_t pmd) 695 { 696 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 697 } 698 699 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 700 701 #define pud_pfn pud_pfn 702 static inline unsigned long pud_pfn(pud_t pud) 703 { 704 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 705 } 706 707 #define pmd_pgprot pmd_pgprot 708 static inline pgprot_t pmd_pgprot(pmd_t pmd) 709 { 710 return pte_pgprot(pmd_pte(pmd)); 711 } 712 713 #define pud_pgprot pud_pgprot 714 static inline pgprot_t pud_pgprot(pud_t pud) 715 { 716 return pte_pgprot(pud_pte(pud)); 717 } 718 719 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 720 { 721 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 722 } 723 724 #define pmd_write pmd_write 725 static inline int pmd_write(pmd_t pmd) 726 { 727 return pte_write(pmd_pte(pmd)); 728 } 729 730 #define pud_write pud_write 731 static inline int pud_write(pud_t pud) 732 { 733 return pte_write(pud_pte(pud)); 734 } 735 736 #define pmd_dirty pmd_dirty 737 static inline int pmd_dirty(pmd_t pmd) 738 { 739 return pte_dirty(pmd_pte(pmd)); 740 } 741 742 #define pmd_young pmd_young 743 static inline int pmd_young(pmd_t pmd) 744 { 745 return pte_young(pmd_pte(pmd)); 746 } 747 748 static inline int pmd_user(pmd_t pmd) 749 { 750 return pte_user(pmd_pte(pmd)); 751 } 752 753 static inline pmd_t pmd_mkold(pmd_t pmd) 754 { 755 return pte_pmd(pte_mkold(pmd_pte(pmd))); 756 } 757 758 static inline pmd_t pmd_mkyoung(pmd_t pmd) 759 { 760 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 761 } 762 763 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 764 { 765 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 766 } 767 768 static inline pmd_t pmd_wrprotect(pmd_t pmd) 769 { 770 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 771 } 772 773 static inline pmd_t pmd_mkclean(pmd_t pmd) 774 { 775 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 776 } 777 778 static inline pmd_t pmd_mkdirty(pmd_t pmd) 779 { 780 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 781 } 782 783 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 784 static inline bool pmd_special(pmd_t pmd) 785 { 786 return pte_special(pmd_pte(pmd)); 787 } 788 789 static inline pmd_t pmd_mkspecial(pmd_t pmd) 790 { 791 return pte_pmd(pte_mkspecial(pmd_pte(pmd))); 792 } 793 #endif 794 795 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 796 static inline bool pud_special(pud_t pud) 797 { 798 return pte_special(pud_pte(pud)); 799 } 800 801 static inline pud_t pud_mkspecial(pud_t pud) 802 { 803 return pte_pud(pte_mkspecial(pud_pte(pud))); 804 } 805 #endif 806 807 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 808 pmd_t *pmdp, pmd_t pmd) 809 { 810 page_table_check_pmd_set(mm, pmdp, pmd); 811 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd)); 812 } 813 814 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 815 pud_t *pudp, pud_t pud) 816 { 817 page_table_check_pud_set(mm, pudp, pud); 818 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud)); 819 } 820 821 #ifdef CONFIG_PAGE_TABLE_CHECK 822 static inline bool pte_user_accessible_page(pte_t pte) 823 { 824 return pte_present(pte) && pte_user(pte); 825 } 826 827 static inline bool pmd_user_accessible_page(pmd_t pmd) 828 { 829 return pmd_leaf(pmd) && pmd_user(pmd); 830 } 831 832 static inline bool pud_user_accessible_page(pud_t pud) 833 { 834 return pud_leaf(pud) && pud_user(pud); 835 } 836 #endif 837 838 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 839 static inline int pmd_trans_huge(pmd_t pmd) 840 { 841 return pmd_leaf(pmd); 842 } 843 844 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 845 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 846 unsigned long address, pmd_t *pmdp, 847 pmd_t entry, int dirty) 848 { 849 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 850 } 851 852 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 853 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 854 unsigned long address, pmd_t *pmdp) 855 { 856 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 857 } 858 859 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 860 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 861 unsigned long address, pmd_t *pmdp) 862 { 863 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0)); 864 865 page_table_check_pmd_clear(mm, pmd); 866 867 return pmd; 868 } 869 870 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 871 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 872 unsigned long address, pmd_t *pmdp) 873 { 874 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 875 } 876 877 #define pmdp_establish pmdp_establish 878 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 879 unsigned long address, pmd_t *pmdp, pmd_t pmd) 880 { 881 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 882 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 883 } 884 885 #define pmdp_collapse_flush pmdp_collapse_flush 886 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 887 unsigned long address, pmd_t *pmdp); 888 889 static inline pud_t pud_wrprotect(pud_t pud) 890 { 891 return pte_pud(pte_wrprotect(pud_pte(pud))); 892 } 893 894 static inline int pud_trans_huge(pud_t pud) 895 { 896 return pud_leaf(pud); 897 } 898 899 static inline int pud_dirty(pud_t pud) 900 { 901 return pte_dirty(pud_pte(pud)); 902 } 903 904 static inline pud_t pud_mkyoung(pud_t pud) 905 { 906 return pte_pud(pte_mkyoung(pud_pte(pud))); 907 } 908 909 static inline pud_t pud_mkold(pud_t pud) 910 { 911 return pte_pud(pte_mkold(pud_pte(pud))); 912 } 913 914 static inline pud_t pud_mkdirty(pud_t pud) 915 { 916 return pte_pud(pte_mkdirty(pud_pte(pud))); 917 } 918 919 static inline pud_t pud_mkclean(pud_t pud) 920 { 921 return pte_pud(pte_mkclean(pud_pte(pud))); 922 } 923 924 static inline pud_t pud_mkwrite(pud_t pud) 925 { 926 return pte_pud(pte_mkwrite_novma(pud_pte(pud))); 927 } 928 929 static inline pud_t pud_mkhuge(pud_t pud) 930 { 931 return pud; 932 } 933 934 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 935 unsigned long address, pud_t *pudp, 936 pud_t entry, int dirty) 937 { 938 return ptep_set_access_flags(vma, address, (pte_t *)pudp, pud_pte(entry), dirty); 939 } 940 941 static inline int pudp_test_and_clear_young(struct vm_area_struct *vma, 942 unsigned long address, pud_t *pudp) 943 { 944 return ptep_test_and_clear_young(vma, address, (pte_t *)pudp); 945 } 946 947 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 948 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 949 unsigned long address, pud_t *pudp) 950 { 951 #ifdef CONFIG_SMP 952 pud_t pud = __pud(xchg(&pudp->pud, 0)); 953 #else 954 pud_t pud = *pudp; 955 956 pud_clear(pudp); 957 #endif 958 959 page_table_check_pud_clear(mm, pud); 960 961 return pud; 962 } 963 964 static inline int pud_young(pud_t pud) 965 { 966 return pte_young(pud_pte(pud)); 967 } 968 969 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 970 unsigned long address, pud_t *pudp) 971 { 972 pte_t *ptep = (pte_t *)pudp; 973 974 update_mmu_cache(vma, address, ptep); 975 } 976 977 static inline pud_t pudp_establish(struct vm_area_struct *vma, 978 unsigned long address, pud_t *pudp, pud_t pud) 979 { 980 page_table_check_pud_set(vma->vm_mm, pudp, pud); 981 return __pud(atomic_long_xchg((atomic_long_t *)pudp, pud_val(pud))); 982 } 983 984 static inline pud_t pud_mkinvalid(pud_t pud) 985 { 986 return __pud(pud_val(pud) & ~(_PAGE_PRESENT | _PAGE_PROT_NONE)); 987 } 988 989 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 990 pud_t *pudp); 991 992 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 993 { 994 return pte_pud(pte_modify(pud_pte(pud), newprot)); 995 } 996 997 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 998 999 /* 1000 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 1001 * are !pte_none() && !pte_present(). 1002 * 1003 * Format of swap PTE: 1004 * bit 0: _PAGE_PRESENT (zero) 1005 * bit 1 to 3: _PAGE_LEAF (zero) 1006 * bit 5: _PAGE_PROT_NONE (zero) 1007 * bit 6: exclusive marker 1008 * bits 7 to 11: swap type 1009 * bits 12 to XLEN-1: swap offset 1010 */ 1011 #define __SWP_TYPE_SHIFT 7 1012 #define __SWP_TYPE_BITS 5 1013 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 1014 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1015 1016 #define MAX_SWAPFILES_CHECK() \ 1017 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1018 1019 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1020 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 1021 #define __swp_entry(type, offset) ((swp_entry_t) \ 1022 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 1023 ((offset) << __SWP_OFFSET_SHIFT) }) 1024 1025 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1026 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1027 1028 static inline bool pte_swp_exclusive(pte_t pte) 1029 { 1030 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 1031 } 1032 1033 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1034 { 1035 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 1036 } 1037 1038 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1039 { 1040 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 1041 } 1042 1043 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1044 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1045 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1046 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1047 1048 /* 1049 * In the RV64 Linux scheme, we give the user half of the virtual-address space 1050 * and give the kernel the other (upper) half. 1051 */ 1052 #ifdef CONFIG_64BIT 1053 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 1054 #else 1055 #define KERN_VIRT_START FIXADDR_START 1056 #endif 1057 1058 /* 1059 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 1060 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 1061 * Task size is: 1062 * - 0x9fc00000 (~2.5GB) for RV32. 1063 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 1064 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 1065 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 1066 * 1067 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 1068 * Instruction Set Manual Volume II: Privileged Architecture" states that 1069 * "load and store effective addresses, which are 64bits, must have bits 1070 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 1071 * Similarly for SV57, bits 63–57 must be equal to bit 56. 1072 */ 1073 #ifdef CONFIG_64BIT 1074 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 1075 1076 #ifdef CONFIG_COMPAT 1077 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 1078 #define TASK_SIZE (is_compat_task() ? \ 1079 TASK_SIZE_32 : TASK_SIZE_64) 1080 #else 1081 #define TASK_SIZE TASK_SIZE_64 1082 #endif 1083 1084 #else 1085 #define TASK_SIZE FIXADDR_START 1086 #endif 1087 1088 #else /* CONFIG_MMU */ 1089 1090 #define PAGE_SHARED __pgprot(0) 1091 #define PAGE_KERNEL __pgprot(0) 1092 #define swapper_pg_dir NULL 1093 #define TASK_SIZE _AC(-1, UL) 1094 #define VMALLOC_START _AC(0, UL) 1095 #define VMALLOC_END TASK_SIZE 1096 1097 #endif /* !CONFIG_MMU */ 1098 1099 extern char _start[]; 1100 extern void *_dtb_early_va; 1101 extern uintptr_t _dtb_early_pa; 1102 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) 1103 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) 1104 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) 1105 #else 1106 #define dtb_early_va _dtb_early_va 1107 #define dtb_early_pa _dtb_early_pa 1108 #endif /* CONFIG_XIP_KERNEL */ 1109 extern u64 satp_mode; 1110 1111 void paging_init(void); 1112 void misc_mem_init(void); 1113 1114 /* 1115 * ZERO_PAGE is a global shared page that is always zero, 1116 * used for zero-mapped memory areas, etc. 1117 */ 1118 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 1119 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 1120 1121 /* 1122 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1123 * TLB flush will be required as a result of the "set". For example, use 1124 * in scenarios where it is known ahead of time that the routine is 1125 * setting non-present entries, or re-setting an existing entry to the 1126 * same value. Otherwise, use the typical "set" helpers and flush the 1127 * TLB. 1128 */ 1129 #define set_p4d_safe(p4dp, p4d) \ 1130 ({ \ 1131 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1132 set_p4d(p4dp, p4d); \ 1133 }) 1134 1135 #define set_pgd_safe(pgdp, pgd) \ 1136 ({ \ 1137 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1138 set_pgd(pgdp, pgd); \ 1139 }) 1140 #endif /* !__ASSEMBLER__ */ 1141 1142 #endif /* _ASM_RISCV_PGTABLE_H */ 1143