1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_PGTABLE_H 7 #define _ASM_RISCV_PGTABLE_H 8 9 #include <linux/mmzone.h> 10 #include <linux/sizes.h> 11 12 #include <asm/pgtable-bits.h> 13 14 #ifndef CONFIG_MMU 15 #ifdef CONFIG_RELOCATABLE 16 #define KERNEL_LINK_ADDR UL(0) 17 #else 18 #define KERNEL_LINK_ADDR _AC(CONFIG_PHYS_RAM_BASE, UL) 19 #endif 20 #define KERN_VIRT_SIZE (UL(-1)) 21 #else 22 23 #define ADDRESS_SPACE_END (UL(-1)) 24 25 #ifdef CONFIG_64BIT 26 /* Leave 2GB for kernel and BPF at the end of the address space */ 27 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) 28 #else 29 #define KERNEL_LINK_ADDR PAGE_OFFSET 30 #endif 31 32 /* Number of entries in the page global directory */ 33 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 34 /* Number of entries in the page table */ 35 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 36 37 /* 38 * Half of the kernel address space (1/4 of the entries of the page global 39 * directory) is for the direct mapping. 40 */ 41 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) 42 43 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 44 #define VMALLOC_END PAGE_OFFSET 45 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) 46 47 #define BPF_JIT_REGION_SIZE (SZ_128M) 48 #ifdef CONFIG_64BIT 49 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) 50 #define BPF_JIT_REGION_END (MODULES_END) 51 #else 52 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) 53 #define BPF_JIT_REGION_END (VMALLOC_END) 54 #endif 55 56 /* Modules always live before the kernel */ 57 #ifdef CONFIG_64BIT 58 /* This is used to define the end of the KASAN shadow region */ 59 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G) 60 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) 61 #define MODULES_END (PFN_ALIGN((unsigned long)&_start)) 62 #else 63 #define MODULES_VADDR VMALLOC_START 64 #define MODULES_END VMALLOC_END 65 #endif 66 67 /* 68 * Roughly size the vmemmap space to be large enough to fit enough 69 * struct pages to map half the virtual address space. Then 70 * position vmemmap directly below the VMALLOC region. 71 */ 72 #define VA_BITS_SV32 32 73 #ifdef CONFIG_64BIT 74 #define VA_BITS_SV39 39 75 #define VA_BITS_SV48 48 76 #define VA_BITS_SV57 57 77 78 #define VA_BITS (pgtable_l5_enabled ? \ 79 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39)) 80 #else 81 #define VA_BITS VA_BITS_SV32 82 #endif 83 84 #define VMEMMAP_SHIFT \ 85 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) 86 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) 87 #define VMEMMAP_END VMALLOC_START 88 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) 89 90 /* 91 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 92 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 93 */ 94 #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) 95 96 /* Needed to limit get_free_mem_region() */ 97 #if defined(CONFIG_FLATMEM) 98 #define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) 99 #elif defined(CONFIG_SPARSEMEM_VMEMMAP) 100 #define DIRECT_MAP_PHYSMEM_END \ 101 ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) 102 #elif defined(CONFIG_SPARSEMEM) 103 /* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ 104 #endif 105 106 #define PCI_IO_SIZE SZ_16M 107 #define PCI_IO_END VMEMMAP_START 108 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) 109 110 #define FIXADDR_TOP PCI_IO_START 111 #ifdef CONFIG_64BIT 112 #define MAX_FDT_SIZE PMD_SIZE 113 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) 114 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) 115 #else 116 #define MAX_FDT_SIZE PGDIR_SIZE 117 #define FIX_FDT_SIZE MAX_FDT_SIZE 118 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE) 119 #endif 120 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 121 122 #endif 123 124 #ifndef __ASSEMBLER__ 125 126 #include <asm/page.h> 127 #include <asm/tlbflush.h> 128 #include <linux/mm_types.h> 129 #include <asm/compat.h> 130 #include <asm/cpufeature.h> 131 132 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) 133 134 #ifdef CONFIG_64BIT 135 #include <asm/pgtable-64.h> 136 137 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS) 138 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39) 139 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64) 140 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64) 141 #else 142 #include <asm/pgtable-32.h> 143 #endif /* CONFIG_64BIT */ 144 145 #include <linux/page_table_check.h> 146 147 struct pt_alloc_ops { 148 pte_t *(*get_pte_virt)(phys_addr_t pa); 149 phys_addr_t (*alloc_pte)(uintptr_t va); 150 #ifndef __PAGETABLE_PMD_FOLDED 151 pmd_t *(*get_pmd_virt)(phys_addr_t pa); 152 phys_addr_t (*alloc_pmd)(uintptr_t va); 153 pud_t *(*get_pud_virt)(phys_addr_t pa); 154 phys_addr_t (*alloc_pud)(uintptr_t va); 155 p4d_t *(*get_p4d_virt)(phys_addr_t pa); 156 phys_addr_t (*alloc_p4d)(uintptr_t va); 157 #endif 158 }; 159 160 extern struct pt_alloc_ops pt_ops __meminitdata; 161 162 #ifdef CONFIG_MMU 163 /* Number of PGD entries that a user-mode program can use */ 164 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 165 166 /* Page protection bits */ 167 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) 168 169 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ) 170 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) 171 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) 172 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) 173 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 174 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ 175 _PAGE_EXEC | _PAGE_WRITE) 176 #define PAGE_SHADOWSTACK __pgprot(_PAGE_BASE | _PAGE_WRITE) 177 178 #define PAGE_COPY PAGE_READ 179 #define PAGE_COPY_EXEC PAGE_READ_EXEC 180 #define PAGE_SHARED PAGE_WRITE 181 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC 182 183 #define _PAGE_KERNEL (_PAGE_READ \ 184 | _PAGE_WRITE \ 185 | _PAGE_PRESENT \ 186 | _PAGE_ACCESSED \ 187 | _PAGE_DIRTY \ 188 | _PAGE_GLOBAL) 189 190 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 191 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 192 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) 193 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ 194 | _PAGE_EXEC) 195 196 #define PAGE_TABLE __pgprot(_PAGE_TABLE) 197 198 #define _PAGE_KERNEL_NC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) 199 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) 200 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) 201 202 extern pgd_t swapper_pg_dir[]; 203 extern pgd_t trampoline_pg_dir[]; 204 extern pgd_t early_pg_dir[]; 205 206 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 207 static inline int pmd_present(pmd_t pmd) 208 { 209 /* 210 * Checking for _PAGE_LEAF is needed too because: 211 * When splitting a THP, split_huge_page() will temporarily clear 212 * the present bit, in this situation, pmd_present() and 213 * pmd_trans_huge() still needs to return true. 214 */ 215 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); 216 } 217 #else 218 static inline int pmd_present(pmd_t pmd) 219 { 220 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 221 } 222 #endif 223 224 static inline int pmd_none(pmd_t pmd) 225 { 226 return (pmd_val(pmd) == 0); 227 } 228 229 static inline int pmd_bad(pmd_t pmd) 230 { 231 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); 232 } 233 234 #define pmd_leaf pmd_leaf 235 static inline bool pmd_leaf(pmd_t pmd) 236 { 237 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); 238 } 239 240 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 241 { 242 WRITE_ONCE(*pmdp, pmd); 243 } 244 245 static inline void pmd_clear(pmd_t *pmdp) 246 { 247 set_pmd(pmdp, __pmd(0)); 248 } 249 250 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) 251 { 252 unsigned long prot_val = pgprot_val(prot); 253 254 ALT_THEAD_PMA(prot_val); 255 256 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val); 257 } 258 259 static inline unsigned long _pgd_pfn(pgd_t pgd) 260 { 261 return __page_val_to_pfn(pgd_val(pgd)); 262 } 263 264 static inline struct page *pmd_page(pmd_t pmd) 265 { 266 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd))); 267 } 268 269 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 270 { 271 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd))); 272 } 273 274 static inline pte_t pmd_pte(pmd_t pmd) 275 { 276 return __pte(pmd_val(pmd)); 277 } 278 279 static inline pte_t pud_pte(pud_t pud) 280 { 281 return __pte(pud_val(pud)); 282 } 283 284 #ifdef CONFIG_RISCV_ISA_SVNAPOT 285 286 static __always_inline bool has_svnapot(void) 287 { 288 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); 289 } 290 291 static inline unsigned long pte_napot(pte_t pte) 292 { 293 return pte_val(pte) & _PAGE_NAPOT; 294 } 295 296 static inline pte_t pte_mknapot(pte_t pte, unsigned int order) 297 { 298 int pos = order - 1 + _PAGE_PFN_SHIFT; 299 unsigned long napot_bit = BIT(pos); 300 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT); 301 302 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT); 303 } 304 305 #else 306 307 static __always_inline bool has_svnapot(void) { return false; } 308 309 static inline unsigned long pte_napot(pte_t pte) 310 { 311 return 0; 312 } 313 314 #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 315 316 /* Yields the page frame number (PFN) of a page table entry */ 317 static inline unsigned long pte_pfn(pte_t pte) 318 { 319 unsigned long res = __page_val_to_pfn(pte_val(pte)); 320 321 if (has_svnapot() && pte_napot(pte)) 322 res = res & (res - 1UL); 323 324 return res; 325 } 326 327 #define pte_page(x) pfn_to_page(pte_pfn(x)) 328 329 /* Constructs a page table entry */ 330 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 331 { 332 unsigned long prot_val = pgprot_val(prot); 333 334 ALT_THEAD_PMA(prot_val); 335 336 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val); 337 } 338 339 #define pte_pgprot pte_pgprot 340 static inline pgprot_t pte_pgprot(pte_t pte) 341 { 342 unsigned long pfn = pte_pfn(pte); 343 344 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 345 } 346 347 static inline int pte_present(pte_t pte) 348 { 349 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); 350 } 351 352 #define pte_accessible pte_accessible 353 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 354 { 355 if (pte_val(a) & _PAGE_PRESENT) 356 return true; 357 358 if ((pte_val(a) & _PAGE_PROT_NONE) && 359 atomic_read(&mm->tlb_flush_pending)) 360 return true; 361 362 return false; 363 } 364 365 static inline int pte_none(pte_t pte) 366 { 367 return (pte_val(pte) == 0); 368 } 369 370 static inline int pte_write(pte_t pte) 371 { 372 return pte_val(pte) & _PAGE_WRITE; 373 } 374 375 static inline int pte_exec(pte_t pte) 376 { 377 return pte_val(pte) & _PAGE_EXEC; 378 } 379 380 static inline int pte_user(pte_t pte) 381 { 382 return pte_val(pte) & _PAGE_USER; 383 } 384 385 static inline int pte_huge(pte_t pte) 386 { 387 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); 388 } 389 390 static inline int pte_dirty(pte_t pte) 391 { 392 return pte_val(pte) & _PAGE_DIRTY; 393 } 394 395 static inline int pte_young(pte_t pte) 396 { 397 return pte_val(pte) & _PAGE_ACCESSED; 398 } 399 400 static inline int pte_special(pte_t pte) 401 { 402 return pte_val(pte) & _PAGE_SPECIAL; 403 } 404 405 /* static inline pte_t pte_rdprotect(pte_t pte) */ 406 407 static inline pte_t pte_wrprotect(pte_t pte) 408 { 409 return __pte((pte_val(pte) & ~(_PAGE_WRITE)) | (_PAGE_READ)); 410 } 411 412 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 413 #define pgtable_supports_uffd() \ 414 riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B) 415 416 static inline bool pte_uffd(pte_t pte) 417 { 418 return !!(pte_val(pte) & _PAGE_UFFD); 419 } 420 421 static inline pte_t pte_mkuffd(pte_t pte) 422 { 423 return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD)); 424 } 425 426 static inline pte_t pte_clear_uffd(pte_t pte) 427 { 428 return __pte(pte_val(pte) & ~(_PAGE_UFFD)); 429 } 430 431 static inline bool pte_swp_uffd(pte_t pte) 432 { 433 return !!(pte_val(pte) & _PAGE_SWP_UFFD); 434 } 435 436 static inline pte_t pte_swp_mkuffd(pte_t pte) 437 { 438 return __pte(pte_val(pte) | _PAGE_SWP_UFFD); 439 } 440 441 static inline pte_t pte_swp_clear_uffd(pte_t pte) 442 { 443 return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD)); 444 } 445 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 446 447 /* static inline pte_t pte_mkread(pte_t pte) */ 448 449 struct vm_area_struct; 450 pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma); 451 #define pte_mkwrite pte_mkwrite 452 453 static inline pte_t pte_mkwrite_novma(pte_t pte) 454 { 455 return __pte(pte_val(pte) | _PAGE_WRITE); 456 } 457 458 static inline pte_t pte_mkwrite_shstk(pte_t pte) 459 { 460 return __pte((pte_val(pte) & ~(_PAGE_LEAF)) | _PAGE_WRITE); 461 } 462 463 /* static inline pte_t pte_mkexec(pte_t pte) */ 464 465 static inline pte_t pte_mkdirty(pte_t pte) 466 { 467 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 468 } 469 470 static inline pte_t pte_mkclean(pte_t pte) 471 { 472 return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); 473 } 474 475 static inline pte_t pte_mkyoung(pte_t pte) 476 { 477 return __pte(pte_val(pte) | _PAGE_ACCESSED); 478 } 479 480 static inline pte_t pte_mkold(pte_t pte) 481 { 482 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); 483 } 484 485 static inline pte_t pte_mkspecial(pte_t pte) 486 { 487 return __pte(pte_val(pte) | _PAGE_SPECIAL); 488 } 489 490 static inline pte_t pte_mkhuge(pte_t pte) 491 { 492 return pte; 493 } 494 495 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 496 #define pgtable_supports_soft_dirty() \ 497 (IS_ENABLED(CONFIG_MEM_SOFT_DIRTY) && \ 498 riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) 499 500 static inline bool pte_soft_dirty(pte_t pte) 501 { 502 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY); 503 } 504 505 static inline pte_t pte_mksoft_dirty(pte_t pte) 506 { 507 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 508 } 509 510 static inline pte_t pte_clear_soft_dirty(pte_t pte) 511 { 512 return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY)); 513 } 514 515 static inline bool pte_swp_soft_dirty(pte_t pte) 516 { 517 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY); 518 } 519 520 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 521 { 522 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 523 } 524 525 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 526 { 527 return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY)); 528 } 529 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 530 531 #ifdef CONFIG_RISCV_ISA_SVNAPOT 532 #define pte_leaf_size(pte) (pte_napot(pte) ? \ 533 napot_cont_size(napot_cont_order(pte)) :\ 534 PAGE_SIZE) 535 #endif 536 537 #ifdef CONFIG_ARCH_HAS_PTE_PROTNONE 538 static inline int pte_protnone(pte_t pte) 539 { 540 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; 541 } 542 543 static inline int pmd_protnone(pmd_t pmd) 544 { 545 return pte_protnone(pmd_pte(pmd)); 546 } 547 #endif /* CONFIG_ARCH_HAS_PTE_PROTNONE */ 548 549 /* Modify page protection bits */ 550 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 551 { 552 unsigned long newprot_val = pgprot_val(newprot); 553 554 ALT_THEAD_PMA(newprot_val); 555 556 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val); 557 } 558 559 #define pgd_ERROR(e) \ 560 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) 561 562 563 /* Commit new configuration to MMU hardware */ 564 static inline void update_mmu_cache_range(struct vm_fault *vmf, 565 struct vm_area_struct *vma, unsigned long address, 566 pte_t *ptep, unsigned int nr) 567 { 568 /* 569 * Svvptc guarantees that the new valid pte will be visible within 570 * a bounded timeframe, so when the uarch does not cache invalid 571 * entries, we don't have to do anything. 572 */ 573 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) 574 return; 575 576 /* 577 * The kernel assumes that TLBs don't cache invalid entries, but 578 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a 579 * cache flush; it is necessary even after writing invalid entries. 580 * Relying on flush_tlb_fix_spurious_fault would suffice, but 581 * the extra traps reduce performance. So, eagerly SFENCE.VMA. 582 */ 583 while (nr--) 584 local_flush_tlb_page(address + nr * PAGE_SIZE); 585 586 } 587 #define update_mmu_cache(vma, addr, ptep) \ 588 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 589 590 #define update_mmu_tlb_range(vma, addr, ptep, nr) \ 591 update_mmu_cache_range(NULL, vma, addr, ptep, nr) 592 593 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 594 unsigned long address, pmd_t *pmdp) 595 { 596 pte_t *ptep = (pte_t *)pmdp; 597 598 update_mmu_cache(vma, address, ptep); 599 } 600 601 #define __HAVE_ARCH_PTE_SAME 602 static inline int pte_same(pte_t pte_a, pte_t pte_b) 603 { 604 return pte_val(pte_a) == pte_val(pte_b); 605 } 606 607 /* 608 * Certain architectures need to do special things when PTEs within 609 * a page table are directly modified. Thus, the following hook is 610 * made available. 611 */ 612 static inline void set_pte(pte_t *ptep, pte_t pteval) 613 { 614 WRITE_ONCE(*ptep, pteval); 615 } 616 617 void flush_icache_pte(struct mm_struct *mm, pte_t pte); 618 619 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval) 620 { 621 if (pte_present(pteval) && pte_exec(pteval)) 622 flush_icache_pte(mm, pteval); 623 624 set_pte(ptep, pteval); 625 } 626 627 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT 628 629 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 630 pte_t *ptep, pte_t pteval, unsigned int nr) 631 { 632 page_table_check_ptes_set(mm, addr, ptep, pteval, nr); 633 634 for (;;) { 635 __set_pte_at(mm, ptep, pteval); 636 if (--nr == 0) 637 break; 638 ptep++; 639 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; 640 } 641 } 642 #define set_ptes set_ptes 643 644 static inline void pte_clear(struct mm_struct *mm, 645 unsigned long addr, pte_t *ptep) 646 { 647 __set_pte_at(mm, ptep, __pte(0)); 648 } 649 650 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */ 651 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 652 pte_t *ptep, pte_t entry, int dirty); 653 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */ 654 bool ptep_test_and_clear_young(struct vm_area_struct *vma, 655 unsigned long address, pte_t *ptep); 656 657 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 658 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 659 unsigned long address, pte_t *ptep) 660 { 661 #ifdef CONFIG_SMP 662 pte_t pte = __pte(xchg(&ptep->pte, 0)); 663 #else 664 pte_t pte = *ptep; 665 666 set_pte(ptep, __pte(0)); 667 #endif 668 669 page_table_check_pte_clear(mm, address, pte); 670 671 return pte; 672 } 673 674 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 675 static inline void ptep_set_wrprotect(struct mm_struct *mm, 676 unsigned long address, pte_t *ptep) 677 { 678 pte_t read_pte = READ_ONCE(*ptep); 679 /* 680 * ptep_set_wrprotect can be called for shadow stack ranges too. 681 * shadow stack memory is XWR = 010 and thus clearing _PAGE_WRITE will lead to 682 * encoding 000b which is wrong encoding with V = 1. This should lead to page fault 683 * but we dont want this wrong configuration to be set in page tables. 684 */ 685 atomic_long_set((atomic_long_t *)ptep, 686 ((pte_val(read_pte) & ~(unsigned long)_PAGE_WRITE) | _PAGE_READ)); 687 } 688 689 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 690 static inline bool ptep_clear_flush_young(struct vm_area_struct *vma, 691 unsigned long address, pte_t *ptep) 692 { 693 /* 694 * This comment is borrowed from x86, but applies equally to RISC-V: 695 * 696 * Clearing the accessed bit without a TLB flush 697 * doesn't cause data corruption. [ It could cause incorrect 698 * page aging and the (mistaken) reclaim of hot pages, but the 699 * chance of that should be relatively low. ] 700 * 701 * So as a performance optimization don't flush the TLB when 702 * clearing the accessed bit, it will eventually be flushed by 703 * a context switch or a VM operation anyway. [ In the rare 704 * event of it not getting flushed for a long time the delay 705 * shouldn't really matter because there's no real memory 706 * pressure for swapout to react to. ] 707 */ 708 return ptep_test_and_clear_young(vma, address, ptep); 709 } 710 711 #define pgprot_nx pgprot_nx 712 static inline pgprot_t pgprot_nx(pgprot_t _prot) 713 { 714 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC); 715 } 716 717 #define pgprot_noncached pgprot_noncached 718 static inline pgprot_t pgprot_noncached(pgprot_t _prot) 719 { 720 unsigned long prot = pgprot_val(_prot); 721 722 prot &= ~_PAGE_MTMASK; 723 prot |= _PAGE_IO; 724 725 return __pgprot(prot); 726 } 727 728 #define pgprot_writecombine pgprot_writecombine 729 static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 730 { 731 unsigned long prot = pgprot_val(_prot); 732 733 prot &= ~_PAGE_MTMASK; 734 prot |= _PAGE_NOCACHE; 735 736 return __pgprot(prot); 737 } 738 739 #define pgprot_dmacoherent pgprot_writecombine 740 741 /* 742 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By 743 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in 744 * DT. 745 */ 746 #define arch_has_hw_pte_young arch_has_hw_pte_young 747 static inline bool arch_has_hw_pte_young(void) 748 { 749 return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); 750 } 751 752 /* 753 * THP functions 754 */ 755 static inline pmd_t pte_pmd(pte_t pte) 756 { 757 return __pmd(pte_val(pte)); 758 } 759 760 static inline pud_t pte_pud(pte_t pte) 761 { 762 return __pud(pte_val(pte)); 763 } 764 765 static inline pmd_t pmd_mkhuge(pmd_t pmd) 766 { 767 return pmd; 768 } 769 770 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 771 { 772 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); 773 } 774 775 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT) 776 777 static inline unsigned long pmd_pfn(pmd_t pmd) 778 { 779 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); 780 } 781 782 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT) 783 784 #define pud_pfn pud_pfn 785 static inline unsigned long pud_pfn(pud_t pud) 786 { 787 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT); 788 } 789 790 #define pmd_pgprot pmd_pgprot 791 static inline pgprot_t pmd_pgprot(pmd_t pmd) 792 { 793 return pte_pgprot(pmd_pte(pmd)); 794 } 795 796 #define pud_pgprot pud_pgprot 797 static inline pgprot_t pud_pgprot(pud_t pud) 798 { 799 return pte_pgprot(pud_pte(pud)); 800 } 801 802 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 803 { 804 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 805 } 806 807 #define pmd_write pmd_write 808 static inline int pmd_write(pmd_t pmd) 809 { 810 return pte_write(pmd_pte(pmd)); 811 } 812 813 #define pud_write pud_write 814 static inline int pud_write(pud_t pud) 815 { 816 return pte_write(pud_pte(pud)); 817 } 818 819 #define pmd_dirty pmd_dirty 820 static inline int pmd_dirty(pmd_t pmd) 821 { 822 return pte_dirty(pmd_pte(pmd)); 823 } 824 825 #define pmd_young pmd_young 826 static inline int pmd_young(pmd_t pmd) 827 { 828 return pte_young(pmd_pte(pmd)); 829 } 830 831 static inline int pmd_user(pmd_t pmd) 832 { 833 return pte_user(pmd_pte(pmd)); 834 } 835 836 static inline pmd_t pmd_mkold(pmd_t pmd) 837 { 838 return pte_pmd(pte_mkold(pmd_pte(pmd))); 839 } 840 841 static inline pmd_t pmd_mkyoung(pmd_t pmd) 842 { 843 return pte_pmd(pte_mkyoung(pmd_pte(pmd))); 844 } 845 846 pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma); 847 #define pmd_mkwrite pmd_mkwrite 848 849 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 850 { 851 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))); 852 } 853 854 static inline pmd_t pmd_mkwrite_shstk(pmd_t pte) 855 { 856 return __pmd((pmd_val(pte) & ~(_PAGE_LEAF)) | _PAGE_WRITE); 857 } 858 859 static inline pmd_t pmd_wrprotect(pmd_t pmd) 860 { 861 return pte_pmd(pte_wrprotect(pmd_pte(pmd))); 862 } 863 864 static inline pmd_t pmd_mkclean(pmd_t pmd) 865 { 866 return pte_pmd(pte_mkclean(pmd_pte(pmd))); 867 } 868 869 static inline pmd_t pmd_mkdirty(pmd_t pmd) 870 { 871 return pte_pmd(pte_mkdirty(pmd_pte(pmd))); 872 } 873 874 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 875 static inline bool pmd_special(pmd_t pmd) 876 { 877 return pte_special(pmd_pte(pmd)); 878 } 879 880 static inline pmd_t pmd_mkspecial(pmd_t pmd) 881 { 882 return pte_pmd(pte_mkspecial(pmd_pte(pmd))); 883 } 884 #endif 885 886 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 887 static inline bool pud_special(pud_t pud) 888 { 889 return pte_special(pud_pte(pud)); 890 } 891 892 static inline pud_t pud_mkspecial(pud_t pud) 893 { 894 return pte_pud(pte_mkspecial(pud_pte(pud))); 895 } 896 #endif 897 898 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 899 static inline bool pmd_uffd(pmd_t pmd) 900 { 901 return pte_uffd(pmd_pte(pmd)); 902 } 903 904 static inline pmd_t pmd_mkuffd(pmd_t pmd) 905 { 906 return pte_pmd(pte_mkuffd(pmd_pte(pmd))); 907 } 908 909 static inline pmd_t pmd_clear_uffd(pmd_t pmd) 910 { 911 return pte_pmd(pte_clear_uffd(pmd_pte(pmd))); 912 } 913 914 static inline bool pmd_swp_uffd(pmd_t pmd) 915 { 916 return pte_swp_uffd(pmd_pte(pmd)); 917 } 918 919 static inline pmd_t pmd_swp_mkuffd(pmd_t pmd) 920 { 921 return pte_pmd(pte_swp_mkuffd(pmd_pte(pmd))); 922 } 923 924 static inline pmd_t pmd_swp_clear_uffd(pmd_t pmd) 925 { 926 return pte_pmd(pte_swp_clear_uffd(pmd_pte(pmd))); 927 } 928 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 929 930 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 931 static inline bool pmd_soft_dirty(pmd_t pmd) 932 { 933 return pte_soft_dirty(pmd_pte(pmd)); 934 } 935 936 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 937 { 938 return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))); 939 } 940 941 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 942 { 943 return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))); 944 } 945 946 #ifdef CONFIG_ARCH_HAS_PMD_SOFTLEAVES 947 static inline bool pmd_swp_soft_dirty(pmd_t pmd) 948 { 949 return pte_swp_soft_dirty(pmd_pte(pmd)); 950 } 951 952 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 953 { 954 return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))); 955 } 956 957 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 958 { 959 return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))); 960 } 961 #endif /* CONFIG_ARCH_HAS_PMD_SOFTLEAVES */ 962 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 963 964 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 965 pmd_t *pmdp, pmd_t pmd) 966 { 967 page_table_check_pmd_set(mm, addr, pmdp, pmd); 968 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd)); 969 } 970 971 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 972 pud_t *pudp, pud_t pud) 973 { 974 page_table_check_pud_set(mm, addr, pudp, pud); 975 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud)); 976 } 977 978 #ifdef CONFIG_PAGE_TABLE_CHECK 979 static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte) 980 { 981 return pte_present(pte) && pte_user(pte); 982 } 983 984 static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd) 985 { 986 return pmd_leaf(pmd) && pmd_user(pmd); 987 } 988 989 static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud) 990 { 991 return pud_leaf(pud) && pud_user(pud); 992 } 993 #endif 994 995 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 996 static inline int pmd_trans_huge(pmd_t pmd) 997 { 998 return pmd_leaf(pmd); 999 } 1000 1001 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1002 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1003 unsigned long address, pmd_t *pmdp, 1004 pmd_t entry, int dirty) 1005 { 1006 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 1007 } 1008 1009 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1010 static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma, 1011 unsigned long address, pmd_t *pmdp) 1012 { 1013 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1014 } 1015 1016 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1017 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1018 unsigned long address, pmd_t *pmdp) 1019 { 1020 #ifdef CONFIG_SMP 1021 pmd_t pmd = __pmd(xchg(&pmdp->pmd, 0)); 1022 #else 1023 pmd_t pmd = *pmdp; 1024 1025 pmd_clear(pmdp); 1026 #endif 1027 1028 page_table_check_pmd_clear(mm, address, pmd); 1029 1030 return pmd; 1031 } 1032 1033 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1034 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1035 unsigned long address, pmd_t *pmdp) 1036 { 1037 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1038 } 1039 1040 #define pmdp_establish pmdp_establish 1041 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1042 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1043 { 1044 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 1045 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); 1046 } 1047 1048 #define pmdp_collapse_flush pmdp_collapse_flush 1049 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1050 unsigned long address, pmd_t *pmdp); 1051 1052 static inline pud_t pud_wrprotect(pud_t pud) 1053 { 1054 return pte_pud(pte_wrprotect(pud_pte(pud))); 1055 } 1056 1057 static inline int pud_trans_huge(pud_t pud) 1058 { 1059 return pud_leaf(pud); 1060 } 1061 1062 static inline int pud_dirty(pud_t pud) 1063 { 1064 return pte_dirty(pud_pte(pud)); 1065 } 1066 1067 static inline pud_t pud_mkyoung(pud_t pud) 1068 { 1069 return pte_pud(pte_mkyoung(pud_pte(pud))); 1070 } 1071 1072 static inline pud_t pud_mkold(pud_t pud) 1073 { 1074 return pte_pud(pte_mkold(pud_pte(pud))); 1075 } 1076 1077 static inline pud_t pud_mkdirty(pud_t pud) 1078 { 1079 return pte_pud(pte_mkdirty(pud_pte(pud))); 1080 } 1081 1082 static inline pud_t pud_mkclean(pud_t pud) 1083 { 1084 return pte_pud(pte_mkclean(pud_pte(pud))); 1085 } 1086 1087 static inline pud_t pud_mkwrite(pud_t pud) 1088 { 1089 return pte_pud(pte_mkwrite_novma(pud_pte(pud))); 1090 } 1091 1092 static inline pud_t pud_mkhuge(pud_t pud) 1093 { 1094 return pud; 1095 } 1096 1097 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 1098 unsigned long address, pud_t *pudp, 1099 pud_t entry, int dirty) 1100 { 1101 return ptep_set_access_flags(vma, address, (pte_t *)pudp, pud_pte(entry), dirty); 1102 } 1103 1104 static inline bool pudp_test_and_clear_young(struct vm_area_struct *vma, 1105 unsigned long address, pud_t *pudp) 1106 { 1107 return ptep_test_and_clear_young(vma, address, (pte_t *)pudp); 1108 } 1109 1110 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1111 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1112 unsigned long address, pud_t *pudp) 1113 { 1114 #ifdef CONFIG_SMP 1115 pud_t pud = __pud(xchg(&pudp->pud, 0)); 1116 #else 1117 pud_t pud = *pudp; 1118 1119 pud_clear(pudp); 1120 #endif 1121 1122 page_table_check_pud_clear(mm, address, pud); 1123 1124 return pud; 1125 } 1126 1127 static inline int pud_young(pud_t pud) 1128 { 1129 return pte_young(pud_pte(pud)); 1130 } 1131 1132 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1133 unsigned long address, pud_t *pudp) 1134 { 1135 pte_t *ptep = (pte_t *)pudp; 1136 1137 update_mmu_cache(vma, address, ptep); 1138 } 1139 1140 static inline pud_t pudp_establish(struct vm_area_struct *vma, 1141 unsigned long address, pud_t *pudp, pud_t pud) 1142 { 1143 page_table_check_pud_set(vma->vm_mm, address, pudp, pud); 1144 return __pud(atomic_long_xchg((atomic_long_t *)pudp, pud_val(pud))); 1145 } 1146 1147 static inline pud_t pud_mkinvalid(pud_t pud) 1148 { 1149 return __pud(pud_val(pud) & ~(_PAGE_PRESENT | _PAGE_PROT_NONE)); 1150 } 1151 1152 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1153 pud_t *pudp); 1154 1155 static inline pud_t pud_modify(pud_t pud, pgprot_t newprot) 1156 { 1157 return pte_pud(pte_modify(pud_pte(pud), newprot)); 1158 } 1159 1160 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1161 1162 /* 1163 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 1164 * are !pte_none() && !pte_present(). 1165 * 1166 * Format of swap PTE: 1167 * bit 0: _PAGE_PRESENT (zero) 1168 * bit 1 to 2: (zero) 1169 * bit 3: _PAGE_SWP_SOFT_DIRTY 1170 * bit 4: _PAGE_SWP_UFFD 1171 * bit 5: _PAGE_PROT_NONE (zero) 1172 * bit 6: exclusive marker 1173 * bits 7 to 11: swap type 1174 * bits 12 to XLEN-1: swap offset 1175 */ 1176 #define __SWP_TYPE_SHIFT 7 1177 #define __SWP_TYPE_BITS 5 1178 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 1179 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1180 1181 #define MAX_SWAPFILES_CHECK() \ 1182 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1183 1184 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1185 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 1186 #define __swp_entry(type, offset) ((swp_entry_t) \ 1187 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \ 1188 ((offset) << __SWP_OFFSET_SHIFT) }) 1189 1190 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1191 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1192 1193 static inline bool pte_swp_exclusive(pte_t pte) 1194 { 1195 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 1196 } 1197 1198 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1199 { 1200 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 1201 } 1202 1203 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1204 { 1205 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 1206 } 1207 1208 #ifdef CONFIG_ARCH_HAS_PMD_SOFTLEAVES 1209 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1210 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1211 #endif /* CONFIG_ARCH_HAS_PMD_SOFTLEAVES */ 1212 1213 /* 1214 * In the RV64 Linux scheme, we give the user half of the virtual-address space 1215 * and give the kernel the other (upper) half. 1216 */ 1217 #ifdef CONFIG_64BIT 1218 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE) 1219 #else 1220 #define KERN_VIRT_START FIXADDR_START 1221 #endif 1222 1223 /* 1224 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. 1225 * Note that PGDIR_SIZE must evenly divide TASK_SIZE. 1226 * Task size is: 1227 * - 0x9fc00000 (~2.5GB) for RV32. 1228 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu 1229 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu 1230 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu 1231 * 1232 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V 1233 * Instruction Set Manual Volume II: Privileged Architecture" states that 1234 * "load and store effective addresses, which are 64bits, must have bits 1235 * 63–48 all equal to bit 47, or else a page-fault exception will occur." 1236 * Similarly for SV57, bits 63–57 must be equal to bit 56. 1237 */ 1238 #ifdef CONFIG_64BIT 1239 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) 1240 1241 #ifdef CONFIG_COMPAT 1242 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) 1243 #define TASK_SIZE (is_compat_task() ? \ 1244 TASK_SIZE_32 : TASK_SIZE_64) 1245 #else 1246 #define TASK_SIZE TASK_SIZE_64 1247 #endif 1248 1249 #else 1250 #define TASK_SIZE FIXADDR_START 1251 #endif 1252 1253 #else /* CONFIG_MMU */ 1254 1255 #define PAGE_SHARED __pgprot(0) 1256 #define PAGE_KERNEL __pgprot(0) 1257 #define swapper_pg_dir NULL 1258 #define TASK_SIZE _AC(-1, UL) 1259 #define VMALLOC_START _AC(0, UL) 1260 #define VMALLOC_END TASK_SIZE 1261 1262 #endif /* !CONFIG_MMU */ 1263 1264 extern char _start[]; 1265 extern void *_dtb_early_va; 1266 extern uintptr_t _dtb_early_pa; 1267 #define dtb_early_va _dtb_early_va 1268 #define dtb_early_pa _dtb_early_pa 1269 extern u64 satp_mode; 1270 1271 void paging_init(void); 1272 void misc_mem_init(void); 1273 1274 /* 1275 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1276 * TLB flush will be required as a result of the "set". For example, use 1277 * in scenarios where it is known ahead of time that the routine is 1278 * setting non-present entries, or re-setting an existing entry to the 1279 * same value. Otherwise, use the typical "set" helpers and flush the 1280 * TLB. 1281 */ 1282 #define set_p4d_safe(p4dp, p4d) \ 1283 ({ \ 1284 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1285 set_p4d(p4dp, p4d); \ 1286 }) 1287 1288 #define set_pgd_safe(pgdp, pgd) \ 1289 ({ \ 1290 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1291 set_pgd(pgdp, pgd); \ 1292 }) 1293 #endif /* !__ASSEMBLER__ */ 1294 1295 #endif /* _ASM_RISCV_PGTABLE_H */ 1296