14ecbd3ebSAnup Patel /* SPDX-License-Identifier: GPL-2.0-only */ 24ecbd3ebSAnup Patel /* 34ecbd3ebSAnup Patel * Copyright (c) 2025 Ventana Micro Systems Inc. 44ecbd3ebSAnup Patel */ 54ecbd3ebSAnup Patel 64ecbd3ebSAnup Patel #ifndef __RISCV_KVM_MMU_H_ 74ecbd3ebSAnup Patel #define __RISCV_KVM_MMU_H_ 84ecbd3ebSAnup Patel 9*dd82e356SAnup Patel #include <asm/kvm_gstage.h> 104ecbd3ebSAnup Patel 11*dd82e356SAnup Patel int kvm_riscv_mmu_ioremap(struct kvm *kvm, gpa_t gpa, phys_addr_t hpa, 12*dd82e356SAnup Patel unsigned long size, bool writable, bool in_atomic); 13*dd82e356SAnup Patel void kvm_riscv_mmu_iounmap(struct kvm *kvm, gpa_t gpa, unsigned long size); 14*dd82e356SAnup Patel int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, 15f035b44bSAnup Patel gpa_t gpa, unsigned long hva, bool is_write, 16f035b44bSAnup Patel struct kvm_gstage_mapping *out_map); 17*dd82e356SAnup Patel int kvm_riscv_mmu_alloc_pgd(struct kvm *kvm); 18*dd82e356SAnup Patel void kvm_riscv_mmu_free_pgd(struct kvm *kvm); 19*dd82e356SAnup Patel void kvm_riscv_mmu_update_hgatp(struct kvm_vcpu *vcpu); 204ecbd3ebSAnup Patel 214ecbd3ebSAnup Patel #endif 22