1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 SiFive 4 */ 5 6 #ifndef _ASM_RISCV_INSN_H 7 #define _ASM_RISCV_INSN_H 8 9 #include <linux/bits.h> 10 11 #define RV_INSN_FUNCT3_MASK GENMASK(14, 12) 12 #define RV_INSN_FUNCT3_OPOFF 12 13 #define RV_INSN_OPCODE_MASK GENMASK(6, 0) 14 #define RV_INSN_OPCODE_OPOFF 0 15 #define RV_INSN_FUNCT12_OPOFF 20 16 17 #define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF) 18 #define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF) 19 20 /* The bit field of immediate value in I-type instruction */ 21 #define RV_I_IMM_SIGN_OPOFF 31 22 #define RV_I_IMM_11_0_OPOFF 20 23 #define RV_I_IMM_SIGN_OFF 12 24 #define RV_I_IMM_11_0_OFF 0 25 #define RV_I_IMM_11_0_MASK GENMASK(11, 0) 26 27 /* The bit field of immediate value in J-type instruction */ 28 #define RV_J_IMM_SIGN_OPOFF 31 29 #define RV_J_IMM_10_1_OPOFF 21 30 #define RV_J_IMM_11_OPOFF 20 31 #define RV_J_IMM_19_12_OPOFF 12 32 #define RV_J_IMM_SIGN_OFF 20 33 #define RV_J_IMM_10_1_OFF 1 34 #define RV_J_IMM_11_OFF 11 35 #define RV_J_IMM_19_12_OFF 12 36 #define RV_J_IMM_10_1_MASK GENMASK(9, 0) 37 #define RV_J_IMM_11_MASK GENMASK(0, 0) 38 #define RV_J_IMM_19_12_MASK GENMASK(7, 0) 39 40 /* 41 * U-type IMMs contain the upper 20bits [31:20] of an immediate with 42 * the rest filled in by zeros, so no shifting required. Similarly, 43 * bit31 contains the signed state, so no sign extension necessary. 44 */ 45 #define RV_U_IMM_SIGN_OPOFF 31 46 #define RV_U_IMM_31_12_OPOFF 0 47 #define RV_U_IMM_31_12_MASK GENMASK(31, 12) 48 49 /* The bit field of immediate value in B-type instruction */ 50 #define RV_B_IMM_SIGN_OPOFF 31 51 #define RV_B_IMM_10_5_OPOFF 25 52 #define RV_B_IMM_4_1_OPOFF 8 53 #define RV_B_IMM_11_OPOFF 7 54 #define RV_B_IMM_SIGN_OFF 12 55 #define RV_B_IMM_10_5_OFF 5 56 #define RV_B_IMM_4_1_OFF 1 57 #define RV_B_IMM_11_OFF 11 58 #define RV_B_IMM_10_5_MASK GENMASK(5, 0) 59 #define RV_B_IMM_4_1_MASK GENMASK(3, 0) 60 #define RV_B_IMM_11_MASK GENMASK(0, 0) 61 62 /* The register offset in RVG instruction */ 63 #define RVG_RS1_OPOFF 15 64 #define RVG_RS2_OPOFF 20 65 #define RVG_RD_OPOFF 7 66 #define RVG_RS1_MASK GENMASK(4, 0) 67 #define RVG_RS2_MASK GENMASK(4, 0) 68 #define RVG_RD_MASK GENMASK(4, 0) 69 70 /* The bit field of immediate value in RVC J instruction */ 71 #define RVC_J_IMM_SIGN_OPOFF 12 72 #define RVC_J_IMM_4_OPOFF 11 73 #define RVC_J_IMM_9_8_OPOFF 9 74 #define RVC_J_IMM_10_OPOFF 8 75 #define RVC_J_IMM_6_OPOFF 7 76 #define RVC_J_IMM_7_OPOFF 6 77 #define RVC_J_IMM_3_1_OPOFF 3 78 #define RVC_J_IMM_5_OPOFF 2 79 #define RVC_J_IMM_SIGN_OFF 11 80 #define RVC_J_IMM_4_OFF 4 81 #define RVC_J_IMM_9_8_OFF 8 82 #define RVC_J_IMM_10_OFF 10 83 #define RVC_J_IMM_6_OFF 6 84 #define RVC_J_IMM_7_OFF 7 85 #define RVC_J_IMM_3_1_OFF 1 86 #define RVC_J_IMM_5_OFF 5 87 #define RVC_J_IMM_4_MASK GENMASK(0, 0) 88 #define RVC_J_IMM_9_8_MASK GENMASK(1, 0) 89 #define RVC_J_IMM_10_MASK GENMASK(0, 0) 90 #define RVC_J_IMM_6_MASK GENMASK(0, 0) 91 #define RVC_J_IMM_7_MASK GENMASK(0, 0) 92 #define RVC_J_IMM_3_1_MASK GENMASK(2, 0) 93 #define RVC_J_IMM_5_MASK GENMASK(0, 0) 94 95 /* The bit field of immediate value in RVC B instruction */ 96 #define RVC_B_IMM_SIGN_OPOFF 12 97 #define RVC_B_IMM_4_3_OPOFF 10 98 #define RVC_B_IMM_7_6_OPOFF 5 99 #define RVC_B_IMM_2_1_OPOFF 3 100 #define RVC_B_IMM_5_OPOFF 2 101 #define RVC_B_IMM_SIGN_OFF 8 102 #define RVC_B_IMM_4_3_OFF 3 103 #define RVC_B_IMM_7_6_OFF 6 104 #define RVC_B_IMM_2_1_OFF 1 105 #define RVC_B_IMM_5_OFF 5 106 #define RVC_B_IMM_4_3_MASK GENMASK(1, 0) 107 #define RVC_B_IMM_7_6_MASK GENMASK(1, 0) 108 #define RVC_B_IMM_2_1_MASK GENMASK(1, 0) 109 #define RVC_B_IMM_5_MASK GENMASK(0, 0) 110 111 #define RVC_INSN_FUNCT4_MASK GENMASK(15, 12) 112 #define RVC_INSN_FUNCT4_OPOFF 12 113 #define RVC_INSN_FUNCT3_MASK GENMASK(15, 13) 114 #define RVC_INSN_FUNCT3_OPOFF 13 115 #define RVC_INSN_J_RS1_MASK GENMASK(11, 7) 116 #define RVC_INSN_J_RS2_MASK GENMASK(6, 2) 117 #define RVC_INSN_OPCODE_MASK GENMASK(1, 0) 118 #define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF) 119 #define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF) 120 121 /* The register offset in RVC op=C0 instruction */ 122 #define RVC_C0_RS1_OPOFF 7 123 #define RVC_C0_RS2_OPOFF 2 124 #define RVC_C0_RD_OPOFF 2 125 126 /* The register offset in RVC op=C1 instruction */ 127 #define RVC_C1_RS1_OPOFF 7 128 #define RVC_C1_RS2_OPOFF 2 129 #define RVC_C1_RD_OPOFF 7 130 131 /* The register offset in RVC op=C2 instruction */ 132 #define RVC_C2_RS1_OPOFF 7 133 #define RVC_C2_RS2_OPOFF 2 134 #define RVC_C2_RD_OPOFF 7 135 #define RVC_C2_RS1_MASK GENMASK(4, 0) 136 137 /* parts of opcode for RVG*/ 138 #define RVG_OPCODE_FENCE 0x0f 139 #define RVG_OPCODE_AUIPC 0x17 140 #define RVG_OPCODE_BRANCH 0x63 141 #define RVG_OPCODE_JALR 0x67 142 #define RVG_OPCODE_JAL 0x6f 143 #define RVG_OPCODE_SYSTEM 0x73 144 #define RVG_SYSTEM_CSR_OFF 20 145 #define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) 146 147 /* parts of opcode for RVF, RVD and RVQ */ 148 #define RVFDQ_FL_FS_WIDTH_OFF 12 149 #define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0) 150 #define RVFDQ_FL_FS_WIDTH_W 2 151 #define RVFDQ_FL_FS_WIDTH_D 3 152 #define RVFDQ_LS_FS_WIDTH_Q 4 153 #define RVFDQ_OPCODE_FL 0x07 154 #define RVFDQ_OPCODE_FS 0x27 155 156 /* parts of opcode for RVV */ 157 #define RVV_OPCODE_VECTOR 0x57 158 #define RVV_VL_VS_WIDTH_8 0 159 #define RVV_VL_VS_WIDTH_16 5 160 #define RVV_VL_VS_WIDTH_32 6 161 #define RVV_VL_VS_WIDTH_64 7 162 #define RVV_OPCODE_VL RVFDQ_OPCODE_FL 163 #define RVV_OPCODE_VS RVFDQ_OPCODE_FS 164 165 /* parts of opcode for RVC*/ 166 #define RVC_OPCODE_C0 0x0 167 #define RVC_OPCODE_C1 0x1 168 #define RVC_OPCODE_C2 0x2 169 170 /* parts of funct3 code for I, M, A extension*/ 171 #define RVG_FUNCT3_JALR 0x0 172 #define RVG_FUNCT3_BEQ 0x0 173 #define RVG_FUNCT3_BNE 0x1 174 #define RVG_FUNCT3_BLT 0x4 175 #define RVG_FUNCT3_BGE 0x5 176 #define RVG_FUNCT3_BLTU 0x6 177 #define RVG_FUNCT3_BGEU 0x7 178 179 /* parts of funct3 code for C extension*/ 180 #define RVC_FUNCT3_C_BEQZ 0x6 181 #define RVC_FUNCT3_C_BNEZ 0x7 182 #define RVC_FUNCT3_C_J 0x5 183 #define RVC_FUNCT3_C_JAL 0x1 184 #define RVC_FUNCT4_C_JR 0x8 185 #define RVC_FUNCT4_C_JALR 0x9 186 #define RVC_FUNCT4_C_EBREAK 0x9 187 188 #define RVG_FUNCT12_EBREAK 0x1 189 #define RVG_FUNCT12_SRET 0x102 190 191 #define RVG_MATCH_AUIPC (RVG_OPCODE_AUIPC) 192 #define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR) 193 #define RVG_MATCH_JAL (RVG_OPCODE_JAL) 194 #define RVG_MATCH_FENCE (RVG_OPCODE_FENCE) 195 #define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH) 196 #define RVG_MATCH_BNE (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH) 197 #define RVG_MATCH_BLT (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH) 198 #define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH) 199 #define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH) 200 #define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH) 201 #define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM) 202 #define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM) 203 #define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1) 204 #define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1) 205 #define RVC_MATCH_C_J (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1) 206 #define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1) 207 #define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2) 208 #define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2) 209 #define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2) 210 211 #define RVG_MASK_AUIPC (RV_INSN_OPCODE_MASK) 212 #define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 213 #define RVG_MASK_JAL (RV_INSN_OPCODE_MASK) 214 #define RVG_MASK_FENCE (RV_INSN_OPCODE_MASK) 215 #define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK) 216 #define RVC_MASK_C_JR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK) 217 #define RVC_MASK_C_JAL (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) 218 #define RVC_MASK_C_J (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) 219 #define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 220 #define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 221 #define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 222 #define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 223 #define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 224 #define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) 225 #define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) 226 #define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) 227 #define RVC_MASK_C_EBREAK 0xffff 228 #define RVG_MASK_EBREAK 0xffffffff 229 #define RVG_MASK_SRET 0xffffffff 230 231 #define __INSN_LENGTH_MASK _UL(0x3) 232 #define __INSN_LENGTH_GE_32 _UL(0x3) 233 #define __INSN_OPCODE_MASK _UL(0x7F) 234 #define __INSN_BRANCH_OPCODE _UL(RVG_OPCODE_BRANCH) 235 236 #define __RISCV_INSN_FUNCS(name, mask, val) \ 237 static __always_inline bool riscv_insn_is_##name(u32 code) \ 238 { \ 239 BUILD_BUG_ON(~(mask) & (val)); \ 240 return (code & (mask)) == (val); \ 241 } \ 242 243 #if __riscv_xlen == 32 244 /* C.JAL is an RV32C-only instruction */ 245 __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL) 246 #else 247 #define riscv_insn_is_c_jal(opcode) 0 248 #endif 249 __RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC) 250 __RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR) 251 __RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL) 252 __RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J) 253 __RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ) 254 __RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE) 255 __RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT) 256 __RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE) 257 __RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU) 258 __RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU) 259 __RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ) 260 __RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ) 261 __RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK) 262 __RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK) 263 __RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET) 264 __RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE); 265 266 /* special case to catch _any_ system instruction */ 267 static __always_inline bool riscv_insn_is_system(u32 code) 268 { 269 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_SYSTEM; 270 } 271 272 /* special case to catch _any_ branch instruction */ 273 static __always_inline bool riscv_insn_is_branch(u32 code) 274 { 275 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH; 276 } 277 278 static __always_inline bool riscv_insn_is_c_jr(u32 code) 279 { 280 return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR && 281 (code & RVC_INSN_J_RS1_MASK) != 0; 282 } 283 284 static __always_inline bool riscv_insn_is_c_jalr(u32 code) 285 { 286 return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR && 287 (code & RVC_INSN_J_RS1_MASK) != 0; 288 } 289 290 #define INSN_MATCH_LB 0x3 291 #define INSN_MASK_LB 0x707f 292 #define INSN_MATCH_LH 0x1003 293 #define INSN_MASK_LH 0x707f 294 #define INSN_MATCH_LW 0x2003 295 #define INSN_MASK_LW 0x707f 296 #define INSN_MATCH_LD 0x3003 297 #define INSN_MASK_LD 0x707f 298 #define INSN_MATCH_LBU 0x4003 299 #define INSN_MASK_LBU 0x707f 300 #define INSN_MATCH_LHU 0x5003 301 #define INSN_MASK_LHU 0x707f 302 #define INSN_MATCH_LWU 0x6003 303 #define INSN_MASK_LWU 0x707f 304 #define INSN_MATCH_SB 0x23 305 #define INSN_MASK_SB 0x707f 306 #define INSN_MATCH_SH 0x1023 307 #define INSN_MASK_SH 0x707f 308 #define INSN_MATCH_SW 0x2023 309 #define INSN_MASK_SW 0x707f 310 #define INSN_MATCH_SD 0x3023 311 #define INSN_MASK_SD 0x707f 312 313 #define INSN_MATCH_C_LD 0x6000 314 #define INSN_MASK_C_LD 0xe003 315 #define INSN_MATCH_C_SD 0xe000 316 #define INSN_MASK_C_SD 0xe003 317 #define INSN_MATCH_C_LW 0x4000 318 #define INSN_MASK_C_LW 0xe003 319 #define INSN_MATCH_C_SW 0xc000 320 #define INSN_MASK_C_SW 0xe003 321 #define INSN_MATCH_C_LDSP 0x6002 322 #define INSN_MASK_C_LDSP 0xe003 323 #define INSN_MATCH_C_SDSP 0xe002 324 #define INSN_MASK_C_SDSP 0xe003 325 #define INSN_MATCH_C_LWSP 0x4002 326 #define INSN_MASK_C_LWSP 0xe003 327 #define INSN_MATCH_C_SWSP 0xc002 328 #define INSN_MASK_C_SWSP 0xe003 329 330 #define INSN_OPCODE_MASK 0x007c 331 #define INSN_OPCODE_SHIFT 2 332 #define INSN_OPCODE_SYSTEM 28 333 334 #define INSN_MASK_WFI 0xffffffff 335 #define INSN_MATCH_WFI 0x10500073 336 337 #define INSN_MASK_WRS 0xffffffff 338 #define INSN_MATCH_WRS 0x00d00073 339 340 #define INSN_MATCH_CSRRW 0x1073 341 #define INSN_MASK_CSRRW 0x707f 342 #define INSN_MATCH_CSRRS 0x2073 343 #define INSN_MASK_CSRRS 0x707f 344 #define INSN_MATCH_CSRRC 0x3073 345 #define INSN_MASK_CSRRC 0x707f 346 #define INSN_MATCH_CSRRWI 0x5073 347 #define INSN_MASK_CSRRWI 0x707f 348 #define INSN_MATCH_CSRRSI 0x6073 349 #define INSN_MASK_CSRRSI 0x707f 350 #define INSN_MATCH_CSRRCI 0x7073 351 #define INSN_MASK_CSRRCI 0x707f 352 353 #define INSN_MATCH_FLW 0x2007 354 #define INSN_MASK_FLW 0x707f 355 #define INSN_MATCH_FLD 0x3007 356 #define INSN_MASK_FLD 0x707f 357 #define INSN_MATCH_FLQ 0x4007 358 #define INSN_MASK_FLQ 0x707f 359 #define INSN_MATCH_FSW 0x2027 360 #define INSN_MASK_FSW 0x707f 361 #define INSN_MATCH_FSD 0x3027 362 #define INSN_MASK_FSD 0x707f 363 #define INSN_MATCH_FSQ 0x4027 364 #define INSN_MASK_FSQ 0x707f 365 366 #define INSN_MATCH_C_FLD 0x2000 367 #define INSN_MASK_C_FLD 0xe003 368 #define INSN_MATCH_C_FLW 0x6000 369 #define INSN_MASK_C_FLW 0xe003 370 #define INSN_MATCH_C_FSD 0xa000 371 #define INSN_MASK_C_FSD 0xe003 372 #define INSN_MATCH_C_FSW 0xe000 373 #define INSN_MASK_C_FSW 0xe003 374 #define INSN_MATCH_C_FLDSP 0x2002 375 #define INSN_MASK_C_FLDSP 0xe003 376 #define INSN_MATCH_C_FSDSP 0xa002 377 #define INSN_MASK_C_FSDSP 0xe003 378 #define INSN_MATCH_C_FLWSP 0x6002 379 #define INSN_MASK_C_FLWSP 0xe003 380 #define INSN_MATCH_C_FSWSP 0xe002 381 #define INSN_MASK_C_FSWSP 0xe003 382 383 #define INSN_MATCH_C_LHU 0x8400 384 #define INSN_MASK_C_LHU 0xfc43 385 #define INSN_MATCH_C_LH 0x8440 386 #define INSN_MASK_C_LH 0xfc43 387 #define INSN_MATCH_C_SH 0x8c00 388 #define INSN_MASK_C_SH 0xfc43 389 390 #define INSN_16BIT_MASK 0x3 391 #define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK) 392 #define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4) 393 394 #define SHIFT_RIGHT(x, y) \ 395 ((y) < 0 ? ((x) << -(y)) : ((x) >> (y))) 396 397 #define REG_MASK \ 398 ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES)) 399 400 #define REG_OFFSET(insn, pos) \ 401 (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) 402 403 #define REG_PTR(insn, pos, regs) \ 404 ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))) 405 406 #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) 407 #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) 408 #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) 409 #define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs)) 410 #define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs)) 411 #define GET_SP(regs) (*REG_PTR(2, 0, regs)) 412 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) 413 #define IMM_I(insn) ((s32)(insn) >> 20) 414 #define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \ 415 (s32)(((insn) >> 7) & 0x1f)) 416 417 #define SH_RD 7 418 #define SH_RS1 15 419 #define SH_RS2 20 420 #define SH_RS2C 2 421 #define MASK_RX 0x1f 422 423 #if defined(CONFIG_64BIT) 424 #define LOG_REGBYTES 3 425 #else 426 #define LOG_REGBYTES 2 427 #endif 428 429 #define MASK_FUNCT3 0x7000 430 431 #define GET_FUNCT3(insn) (((insn) >> 12) & 7) 432 433 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 434 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) 435 #define RV_X_MASK(X, s, mask) (((X) >> (s)) & (mask)) 436 #define RV_X(X, s, n) RV_X_MASK(X, s, ((1 << (n)) - 1)) 437 #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ 438 (RV_X(x, 10, 3) << 3) | \ 439 (RV_X(x, 5, 1) << 6)) 440 #define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \ 441 (RV_X(x, 5, 2) << 6)) 442 #define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \ 443 (RV_X(x, 12, 1) << 5) | \ 444 (RV_X(x, 2, 2) << 6)) 445 #define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \ 446 (RV_X(x, 12, 1) << 5) | \ 447 (RV_X(x, 2, 3) << 6)) 448 #define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \ 449 (RV_X(x, 7, 2) << 6)) 450 #define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \ 451 (RV_X(x, 7, 3) << 6)) 452 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3)) 453 #define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3)) 454 #define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5) 455 #define RVC_X(X, s, mask) RV_X_MASK(X, s, mask) 456 457 #define RV_EXTRACT_FUNCT3(x) \ 458 ({typeof(x) x_ = (x); \ 459 (RV_X_MASK(x_, RV_INSN_FUNCT3_OPOFF, \ 460 RV_INSN_FUNCT3_MASK >> RV_INSN_FUNCT3_OPOFF)); }) 461 462 #define RV_EXTRACT_RS1_REG(x) \ 463 ({typeof(x) x_ = (x); \ 464 (RV_X_MASK(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); }) 465 466 #define RV_EXTRACT_RS2_REG(x) \ 467 ({typeof(x) x_ = (x); \ 468 (RV_X_MASK(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); }) 469 470 #define RV_EXTRACT_RD_REG(x) \ 471 ({typeof(x) x_ = (x); \ 472 (RV_X_MASK(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) 473 474 #define RV_EXTRACT_UTYPE_IMM(x) \ 475 ({typeof(x) x_ = (x); \ 476 (RV_X_MASK(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) 477 478 #define RV_EXTRACT_JTYPE_IMM(x) \ 479 ({typeof(x) x_ = (x); \ 480 (RV_X_MASK(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \ 481 (RV_X_MASK(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \ 482 (RV_X_MASK(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \ 483 (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); }) 484 485 #define RV_EXTRACT_ITYPE_IMM(x) \ 486 ({typeof(x) x_ = (x); \ 487 (RV_X_MASK(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \ 488 (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); }) 489 490 #define RV_EXTRACT_BTYPE_IMM(x) \ 491 ({typeof(x) x_ = (x); \ 492 (RV_X_MASK(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \ 493 (RV_X_MASK(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \ 494 (RV_X_MASK(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \ 495 (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); }) 496 497 #define RVC_EXTRACT_C2_RS1_REG(x) \ 498 ({typeof(x) x_ = (x); \ 499 (RV_X_MASK(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); }) 500 501 #define RVC_EXTRACT_JTYPE_IMM(x) \ 502 ({typeof(x) x_ = (x); \ 503 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \ 504 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \ 505 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \ 506 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \ 507 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \ 508 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \ 509 (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \ 510 (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); }) 511 512 #define RVC_EXTRACT_BTYPE_IMM(x) \ 513 ({typeof(x) x_ = (x); \ 514 (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \ 515 (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \ 516 (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \ 517 (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ 518 (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) 519 520 #define RVG_EXTRACT_SYSTEM_CSR(x) \ 521 ({typeof(x) x_ = (x); RV_X_MASK(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); }) 522 523 #define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \ 524 ({typeof(x) x_ = (x); RV_X_MASK(x_, RVFDQ_FL_FS_WIDTH_OFF, \ 525 RVFDQ_FL_FS_WIDTH_MASK); }) 526 527 #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) 528 529 /* 530 * Get the immediate from a J-type instruction. 531 * 532 * @insn: instruction to process 533 * Return: immediate 534 */ 535 static inline s32 riscv_insn_extract_jtype_imm(u32 insn) 536 { 537 return RV_EXTRACT_JTYPE_IMM(insn); 538 } 539 540 /* 541 * Update a J-type instruction with an immediate value. 542 * 543 * @insn: pointer to the jtype instruction 544 * @imm: the immediate to insert into the instruction 545 */ 546 static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm) 547 { 548 /* drop the old IMMs, all jal IMM bits sit at 31:12 */ 549 *insn &= ~GENMASK(31, 12); 550 *insn |= (RV_X_MASK(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) | 551 (RV_X_MASK(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) | 552 (RV_X_MASK(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) | 553 (RV_X_MASK(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF); 554 } 555 556 /* 557 * Put together one immediate from a U-type and I-type instruction pair. 558 * 559 * The U-type contains an upper immediate, meaning bits[31:12] with [11:0] 560 * being zero, while the I-type contains a 12bit immediate. 561 * Combined these can encode larger 32bit values and are used for example 562 * in auipc + jalr pairs to allow larger jumps. 563 * 564 * @utype_insn: instruction containing the upper immediate 565 * @itype_insn: instruction 566 * Return: combined immediate 567 */ 568 static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn) 569 { 570 s32 imm; 571 572 imm = RV_EXTRACT_UTYPE_IMM(utype_insn); 573 imm += RV_EXTRACT_ITYPE_IMM(itype_insn); 574 575 return imm; 576 } 577 578 /* 579 * Update a set of two instructions (U-type + I-type) with an immediate value. 580 * 581 * Used for example in auipc+jalrs pairs the U-type instructions contains 582 * a 20bit upper immediate representing bits[31:12], while the I-type 583 * instruction contains a 12bit immediate representing bits[11:0]. 584 * 585 * This also takes into account that both separate immediates are 586 * considered as signed values, so if the I-type immediate becomes 587 * negative (BIT(11) set) the U-type part gets adjusted. 588 * 589 * @utype_insn: pointer to the utype instruction of the pair 590 * @itype_insn: pointer to the itype instruction of the pair 591 * @imm: the immediate to insert into the two instructions 592 */ 593 static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm) 594 { 595 /* drop possible old IMM values */ 596 *utype_insn &= ~(RV_U_IMM_31_12_MASK); 597 *itype_insn &= ~(RV_I_IMM_11_0_MASK << RV_I_IMM_11_0_OPOFF); 598 599 /* add the adapted IMMs */ 600 *utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1); 601 *itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF); 602 } 603 #endif /* _ASM_RISCV_INSN_H */ 604