1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 #ifndef _ASM_RISCV_HWCAP_H 9 #define _ASM_RISCV_HWCAP_H 10 11 #include <uapi/asm/hwcap.h> 12 13 #define RISCV_ISA_EXT_a ('a' - 'a') 14 #define RISCV_ISA_EXT_b ('b' - 'a') 15 #define RISCV_ISA_EXT_c ('c' - 'a') 16 #define RISCV_ISA_EXT_d ('d' - 'a') 17 #define RISCV_ISA_EXT_f ('f' - 'a') 18 #define RISCV_ISA_EXT_h ('h' - 'a') 19 #define RISCV_ISA_EXT_i ('i' - 'a') 20 #define RISCV_ISA_EXT_j ('j' - 'a') 21 #define RISCV_ISA_EXT_k ('k' - 'a') 22 #define RISCV_ISA_EXT_m ('m' - 'a') 23 #define RISCV_ISA_EXT_p ('p' - 'a') 24 #define RISCV_ISA_EXT_q ('q' - 'a') 25 #define RISCV_ISA_EXT_s ('s' - 'a') 26 #define RISCV_ISA_EXT_u ('u' - 'a') 27 #define RISCV_ISA_EXT_v ('v' - 'a') 28 29 /* 30 * These macros represent the logical IDs of each multi-letter RISC-V ISA 31 * extension and are used in the ISA bitmap. The logical IDs start from 32 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single 33 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order 34 * to allocate the bitmap and may be increased when necessary. 35 * 36 * New extensions should just be added to the bottom, rather than added 37 * alphabetically, in order to avoid unnecessary shuffling. 38 */ 39 #define RISCV_ISA_EXT_BASE 26 40 41 #define RISCV_ISA_EXT_SSCOFPMF 26 42 #define RISCV_ISA_EXT_SSTC 27 43 #define RISCV_ISA_EXT_SVINVAL 28 44 #define RISCV_ISA_EXT_SVPBMT 29 45 #define RISCV_ISA_EXT_ZBB 30 46 #define RISCV_ISA_EXT_ZICBOM 31 47 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 48 #define RISCV_ISA_EXT_SVNAPOT 33 49 #define RISCV_ISA_EXT_ZICBOZ 34 50 #define RISCV_ISA_EXT_SMAIA 35 51 #define RISCV_ISA_EXT_SSAIA 36 52 #define RISCV_ISA_EXT_ZBA 37 53 #define RISCV_ISA_EXT_ZBS 38 54 #define RISCV_ISA_EXT_ZICNTR 39 55 #define RISCV_ISA_EXT_ZICSR 40 56 #define RISCV_ISA_EXT_ZIFENCEI 41 57 #define RISCV_ISA_EXT_ZIHPM 42 58 #define RISCV_ISA_EXT_SMSTATEEN 43 59 #define RISCV_ISA_EXT_ZICOND 44 60 61 #define RISCV_ISA_EXT_MAX 64 62 63 #ifdef CONFIG_RISCV_M_MODE 64 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 65 #else 66 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 67 #endif 68 69 #endif /* _ASM_RISCV_HWCAP_H */ 70