1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2017 Andes Technology Corporation */ 3 4 #ifndef _ASM_RISCV_FTRACE_H 5 #define _ASM_RISCV_FTRACE_H 6 7 /* 8 * The graph frame test is not possible if CONFIG_FRAME_POINTER is not enabled. 9 * Check arch/riscv/kernel/mcount.S for detail. 10 */ 11 #if defined(CONFIG_FUNCTION_GRAPH_TRACER) && defined(CONFIG_FRAME_POINTER) 12 #define HAVE_FUNCTION_GRAPH_FP_TEST 13 #endif 14 #define HAVE_FUNCTION_GRAPH_RET_ADDR_PTR 15 16 /* 17 * Clang prior to 13 had "mcount" instead of "_mcount": 18 * https://reviews.llvm.org/D98881 19 */ 20 #if defined(CONFIG_CC_IS_GCC) || CONFIG_CLANG_VERSION >= 130000 21 #define MCOUNT_NAME _mcount 22 #else 23 #define MCOUNT_NAME mcount 24 #endif 25 26 #define ARCH_SUPPORTS_FTRACE_OPS 1 27 #ifndef __ASSEMBLY__ 28 void MCOUNT_NAME(void); 29 static inline unsigned long ftrace_call_adjust(unsigned long addr) 30 { 31 return addr; 32 } 33 34 struct dyn_arch_ftrace { 35 }; 36 #endif 37 38 #ifdef CONFIG_DYNAMIC_FTRACE 39 /* 40 * A general call in RISC-V is a pair of insts: 41 * 1) auipc: setting high-20 pc-related bits to ra register 42 * 2) jalr: setting low-12 offset to ra, jump to ra, and set ra to 43 * return address (original pc + 4) 44 * 45 *<ftrace enable>: 46 * 0: auipc t0/ra, 0x? 47 * 4: jalr t0/ra, ?(t0/ra) 48 * 49 *<ftrace disable>: 50 * 0: nop 51 * 4: nop 52 * 53 * Dynamic ftrace generates probes to call sites, so we must deal with 54 * both auipc and jalr at the same time. 55 */ 56 57 #define MCOUNT_ADDR ((unsigned long)MCOUNT_NAME) 58 #define JALR_SIGN_MASK (0x00000800) 59 #define JALR_OFFSET_MASK (0x00000fff) 60 #define AUIPC_OFFSET_MASK (0xfffff000) 61 #define AUIPC_PAD (0x00001000) 62 #define JALR_SHIFT 20 63 #define JALR_RA (0x000080e7) 64 #define AUIPC_RA (0x00000097) 65 #define JALR_T0 (0x000282e7) 66 #define AUIPC_T0 (0x00000297) 67 #define NOP4 (0x00000013) 68 69 #define to_jalr_t0(offset) \ 70 (((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_T0) 71 72 #define to_auipc_t0(offset) \ 73 ((offset & JALR_SIGN_MASK) ? \ 74 (((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_T0) : \ 75 ((offset & AUIPC_OFFSET_MASK) | AUIPC_T0)) 76 77 #define make_call_t0(caller, callee, call) \ 78 do { \ 79 unsigned int offset = \ 80 (unsigned long) callee - (unsigned long) caller; \ 81 call[0] = to_auipc_t0(offset); \ 82 call[1] = to_jalr_t0(offset); \ 83 } while (0) 84 85 #define to_jalr_ra(offset) \ 86 (((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_RA) 87 88 #define to_auipc_ra(offset) \ 89 ((offset & JALR_SIGN_MASK) ? \ 90 (((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_RA) : \ 91 ((offset & AUIPC_OFFSET_MASK) | AUIPC_RA)) 92 93 #define make_call_ra(caller, callee, call) \ 94 do { \ 95 unsigned int offset = \ 96 (unsigned long) callee - (unsigned long) caller; \ 97 call[0] = to_auipc_ra(offset); \ 98 call[1] = to_jalr_ra(offset); \ 99 } while (0) 100 101 /* 102 * Let auipc+jalr be the basic *mcount unit*, so we make it 8 bytes here. 103 */ 104 #define MCOUNT_INSN_SIZE 8 105 106 #ifndef __ASSEMBLY__ 107 struct dyn_ftrace; 108 int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec); 109 #define ftrace_init_nop ftrace_init_nop 110 #endif 111 112 #endif 113 114 #endif /* _ASM_RISCV_FTRACE_H */ 115