1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021 Sifive. 4 */ 5 #ifndef ASM_ERRATA_LIST_H 6 #define ASM_ERRATA_LIST_H 7 8 #include <asm/alternative.h> 9 #include <asm/csr.h> 10 #include <asm/vendorid_list.h> 11 12 #ifdef CONFIG_ERRATA_SIFIVE 13 #define ERRATA_SIFIVE_CIP_453 0 14 #define ERRATA_SIFIVE_CIP_1200 1 15 #define ERRATA_SIFIVE_NUMBER 2 16 #endif 17 18 #ifdef CONFIG_ERRATA_THEAD 19 #define ERRATA_THEAD_PBMT 0 20 #define ERRATA_THEAD_CMO 1 21 #define ERRATA_THEAD_PMU 2 22 #define ERRATA_THEAD_NUMBER 3 23 #endif 24 25 #define CPUFEATURE_SVPBMT 0 26 #define CPUFEATURE_ZICBOM 1 27 #define CPUFEATURE_NUMBER 2 28 29 #ifdef __ASSEMBLY__ 30 31 #define ALT_INSN_FAULT(x) \ 32 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ 33 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ 34 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 35 CONFIG_ERRATA_SIFIVE_CIP_453) 36 37 #define ALT_PAGE_FAULT(x) \ 38 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ 39 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ 40 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 41 CONFIG_ERRATA_SIFIVE_CIP_453) 42 #else /* !__ASSEMBLY__ */ 43 44 #define ALT_FLUSH_TLB_PAGE(x) \ 45 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 46 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 47 : : "r" (addr) : "memory") 48 49 /* 50 * _val is marked as "will be overwritten", so need to set it to 0 51 * in the default case. 52 */ 53 #define ALT_SVPBMT_SHIFT 61 54 #define ALT_THEAD_PBMT_SHIFT 59 55 #define ALT_SVPBMT(_val, prot) \ 56 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ 57 "li %0, %1\t\nslli %0,%0,%3", 0, \ 58 CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ 59 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ 60 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 61 : "=r"(_val) \ 62 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ 63 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 64 "I"(ALT_SVPBMT_SHIFT), \ 65 "I"(ALT_THEAD_PBMT_SHIFT)) 66 67 #ifdef CONFIG_ERRATA_THEAD_PBMT 68 /* 69 * IO/NOCACHE memory types are handled together with svpbmt, 70 * so on T-Head chips, check if no other memory type is set, 71 * and set the non-0 PMA type if applicable. 72 */ 73 #define ALT_THEAD_PMA(_val) \ 74 asm volatile(ALTERNATIVE( \ 75 __nops(7), \ 76 "li t3, %1\n\t" \ 77 "slli t3, t3, %3\n\t" \ 78 "and t3, %0, t3\n\t" \ 79 "bne t3, zero, 2f\n\t" \ 80 "li t3, %2\n\t" \ 81 "slli t3, t3, %3\n\t" \ 82 "or %0, %0, t3\n\t" \ 83 "2:", THEAD_VENDOR_ID, \ 84 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ 85 : "+r"(_val) \ 86 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 87 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ 88 "I"(ALT_THEAD_PBMT_SHIFT) \ 89 : "t3") 90 #else 91 #define ALT_THEAD_PMA(_val) 92 #endif 93 94 /* 95 * dcache.ipa rs1 (invalidate, physical address) 96 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 97 * 0000001 01010 rs1 000 00000 0001011 98 * dache.iva rs1 (invalida, virtual address) 99 * 0000001 00110 rs1 000 00000 0001011 100 * 101 * dcache.cpa rs1 (clean, physical address) 102 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 103 * 0000001 01001 rs1 000 00000 0001011 104 * dcache.cva rs1 (clean, virtual address) 105 * 0000001 00100 rs1 000 00000 0001011 106 * 107 * dcache.cipa rs1 (clean then invalidate, physical address) 108 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 109 * 0000001 01011 rs1 000 00000 0001011 110 * dcache.civa rs1 (... virtual address) 111 * 0000001 00111 rs1 000 00000 0001011 112 * 113 * sync.s (make sure all cache operations finished) 114 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | 115 * 0000000 11001 00000 000 00000 0001011 116 */ 117 #define THEAD_inval_A0 ".long 0x0265000b" 118 #define THEAD_clean_A0 ".long 0x0245000b" 119 #define THEAD_flush_A0 ".long 0x0275000b" 120 #define THEAD_SYNC_S ".long 0x0190000b" 121 122 #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ 123 asm volatile(ALTERNATIVE_2( \ 124 __nops(6), \ 125 "mv a0, %1\n\t" \ 126 "j 2f\n\t" \ 127 "3:\n\t" \ 128 "cbo." __stringify(_op) " (a0)\n\t" \ 129 "add a0, a0, %0\n\t" \ 130 "2:\n\t" \ 131 "bltu a0, %2, 3b\n\t" \ 132 "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ 133 "mv a0, %1\n\t" \ 134 "j 2f\n\t" \ 135 "3:\n\t" \ 136 THEAD_##_op##_A0 "\n\t" \ 137 "add a0, a0, %0\n\t" \ 138 "2:\n\t" \ 139 "bltu a0, %2, 3b\n\t" \ 140 THEAD_SYNC_S, THEAD_VENDOR_ID, \ 141 ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ 142 : : "r"(_cachesize), \ 143 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ 144 "r"((unsigned long)(_start) + (_size)) \ 145 : "a0") 146 147 #define THEAD_C9XX_RV_IRQ_PMU 17 148 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 149 150 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ 151 asm volatile(ALTERNATIVE( \ 152 "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ 153 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ 154 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ 155 CONFIG_ERRATA_THEAD_PMU) \ 156 : "=r" (__ovl) : \ 157 : "memory") 158 159 #endif /* __ASSEMBLY__ */ 160 161 #endif 162