1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2021 Sifive. 4 */ 5 #ifndef ASM_ERRATA_LIST_H 6 #define ASM_ERRATA_LIST_H 7 8 #include <asm/alternative.h> 9 #include <asm/csr.h> 10 #include <asm/insn-def.h> 11 #include <asm/hwcap.h> 12 #include <asm/vendorid_list.h> 13 #include <asm/errata_list_vendors.h> 14 15 #ifdef __ASSEMBLER__ 16 17 #define ALT_INSN_FAULT(x) \ 18 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ 19 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ 20 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 21 CONFIG_ERRATA_SIFIVE_CIP_453) 22 23 #define ALT_PAGE_FAULT(x) \ 24 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ 25 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ 26 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ 27 CONFIG_ERRATA_SIFIVE_CIP_453) 28 #else /* !__ASSEMBLER__ */ 29 30 #define ALT_SFENCE_VMA_ASID(asid) \ 31 asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 32 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 33 : : "r" (asid) : "memory") 34 35 #define ALT_SFENCE_VMA_ADDR(addr) \ 36 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ 37 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 38 : : "r" (addr) : "memory") 39 40 #define ALT_SFENCE_VMA_ADDR_ASID(addr, asid) \ 41 asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID, \ 42 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ 43 : : "r" (addr), "r" (asid) : "memory") 44 45 /* 46 * _val is marked as "will be overwritten", so need to set it to 0 47 * in the default case. 48 */ 49 #define ALT_SVPBMT_SHIFT 61 50 #define ALT_THEAD_MAE_SHIFT 59 51 #define ALT_SVPBMT(_val, prot) \ 52 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ 53 "li %0, %1\t\nslli %0,%0,%3", 0, \ 54 RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ 55 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ 56 ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \ 57 : "=r"(_val) \ 58 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ 59 "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT), \ 60 "I"(ALT_SVPBMT_SHIFT), \ 61 "I"(ALT_THEAD_MAE_SHIFT)) 62 63 #ifdef CONFIG_ERRATA_THEAD_MAE 64 /* 65 * IO/NOCACHE memory types are handled together with svpbmt, 66 * so on T-Head chips, check if no other memory type is set, 67 * and set the non-0 PMA type if applicable. 68 */ 69 #define ALT_THEAD_PMA(_val) \ 70 asm volatile(ALTERNATIVE( \ 71 __nops(7), \ 72 "li t3, %1\n\t" \ 73 "slli t3, t3, %3\n\t" \ 74 "and t3, %0, t3\n\t" \ 75 "bne t3, zero, 2f\n\t" \ 76 "li t3, %2\n\t" \ 77 "slli t3, t3, %3\n\t" \ 78 "or %0, %0, t3\n\t" \ 79 "2:", THEAD_VENDOR_ID, \ 80 ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \ 81 : "+r"(_val) \ 82 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT), \ 83 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT), \ 84 "I"(ALT_THEAD_MAE_SHIFT) \ 85 : "t3") 86 #else 87 #define ALT_THEAD_PMA(_val) 88 #endif 89 90 #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ 91 asm volatile(ALTERNATIVE( \ 92 __nops(5), \ 93 "mv a0, %1\n\t" \ 94 "j 2f\n\t" \ 95 "3:\n\t" \ 96 CBO_##_op(a0) \ 97 "add a0, a0, %0\n\t" \ 98 "2:\n\t" \ 99 "bltu a0, %2, 3b\n\t", \ 100 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM) \ 101 : : "r"(_cachesize), \ 102 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ 103 "r"((unsigned long)(_start) + (_size)) \ 104 : "a0") 105 106 #define THEAD_C9XX_RV_IRQ_PMU 17 107 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 108 109 #endif /* __ASSEMBLER__ */ 110 111 #endif 112