1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_RISCV_ENTRY_COMMON_H 4 #define _ASM_RISCV_ENTRY_COMMON_H 5 6 #include <asm/stacktrace.h> 7 #include <asm/thread_info.h> 8 #include <asm/vector.h> 9 10 static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, 11 unsigned long ti_work) 12 { 13 if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) { 14 clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE); 15 /* 16 * We are already called with irq disabled, so go without 17 * keeping track of riscv_v_flags. 18 */ 19 riscv_v_vstate_restore(¤t->thread.vstate, regs); 20 } 21 } 22 23 #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare 24 25 void handle_page_fault(struct pt_regs *regs); 26 void handle_break(struct pt_regs *regs); 27 28 #ifdef CONFIG_RISCV_MISALIGNED 29 int handle_misaligned_load(struct pt_regs *regs); 30 int handle_misaligned_store(struct pt_regs *regs); 31 #else 32 static inline int handle_misaligned_load(struct pt_regs *regs) 33 { 34 return -1; 35 } 36 static inline int handle_misaligned_store(struct pt_regs *regs) 37 { 38 return -1; 39 } 40 #endif 41 42 #endif /* _ASM_RISCV_ENTRY_COMMON_H */ 43