1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_VS _AC(0x00000600, UL) /* Vector Status */ 28 #define SR_VS_OFF _AC(0x00000000, UL) 29 #define SR_VS_INITIAL _AC(0x00000200, UL) 30 #define SR_VS_CLEAN _AC(0x00000400, UL) 31 #define SR_VS_DIRTY _AC(0x00000600, UL) 32 33 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 34 #define SR_XS_OFF _AC(0x00000000, UL) 35 #define SR_XS_INITIAL _AC(0x00008000, UL) 36 #define SR_XS_CLEAN _AC(0x00010000, UL) 37 #define SR_XS_DIRTY _AC(0x00018000, UL) 38 39 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 40 41 #ifndef CONFIG_64BIT 42 #define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 43 #else 44 #define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 45 #endif 46 47 #ifdef CONFIG_64BIT 48 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 49 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 50 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 51 #endif 52 53 /* SATP flags */ 54 #ifndef CONFIG_64BIT 55 #define SATP_PPN _AC(0x003FFFFF, UL) 56 #define SATP_MODE_32 _AC(0x80000000, UL) 57 #define SATP_ASID_BITS 9 58 #define SATP_ASID_SHIFT 22 59 #define SATP_ASID_MASK _AC(0x1FF, UL) 60 #else 61 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 62 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 63 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 64 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 65 #define SATP_ASID_BITS 16 66 #define SATP_ASID_SHIFT 44 67 #define SATP_ASID_MASK _AC(0xFFFF, UL) 68 #endif 69 70 /* Exception cause high bit - is an interrupt if set */ 71 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 72 73 /* Interrupt causes (minus the high bit) */ 74 #define IRQ_S_SOFT 1 75 #define IRQ_VS_SOFT 2 76 #define IRQ_M_SOFT 3 77 #define IRQ_S_TIMER 5 78 #define IRQ_VS_TIMER 6 79 #define IRQ_M_TIMER 7 80 #define IRQ_S_EXT 9 81 #define IRQ_VS_EXT 10 82 #define IRQ_M_EXT 11 83 #define IRQ_S_GEXT 12 84 #define IRQ_PMU_OVF 13 85 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 86 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 87 88 /* Exception causes */ 89 #define EXC_INST_MISALIGNED 0 90 #define EXC_INST_ACCESS 1 91 #define EXC_INST_ILLEGAL 2 92 #define EXC_BREAKPOINT 3 93 #define EXC_LOAD_MISALIGNED 4 94 #define EXC_LOAD_ACCESS 5 95 #define EXC_STORE_MISALIGNED 6 96 #define EXC_STORE_ACCESS 7 97 #define EXC_SYSCALL 8 98 #define EXC_HYPERVISOR_SYSCALL 9 99 #define EXC_SUPERVISOR_SYSCALL 10 100 #define EXC_INST_PAGE_FAULT 12 101 #define EXC_LOAD_PAGE_FAULT 13 102 #define EXC_STORE_PAGE_FAULT 15 103 #define EXC_INST_GUEST_PAGE_FAULT 20 104 #define EXC_LOAD_GUEST_PAGE_FAULT 21 105 #define EXC_VIRTUAL_INST_FAULT 22 106 #define EXC_STORE_GUEST_PAGE_FAULT 23 107 108 /* PMP configuration */ 109 #define PMP_R 0x01 110 #define PMP_W 0x02 111 #define PMP_X 0x04 112 #define PMP_A 0x18 113 #define PMP_A_TOR 0x08 114 #define PMP_A_NA4 0x10 115 #define PMP_A_NAPOT 0x18 116 #define PMP_L 0x80 117 118 /* HSTATUS flags */ 119 #ifdef CONFIG_64BIT 120 #define HSTATUS_VSXL _AC(0x300000000, UL) 121 #define HSTATUS_VSXL_SHIFT 32 122 #endif 123 #define HSTATUS_VTSR _AC(0x00400000, UL) 124 #define HSTATUS_VTW _AC(0x00200000, UL) 125 #define HSTATUS_VTVM _AC(0x00100000, UL) 126 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 127 #define HSTATUS_VGEIN_SHIFT 12 128 #define HSTATUS_HU _AC(0x00000200, UL) 129 #define HSTATUS_SPVP _AC(0x00000100, UL) 130 #define HSTATUS_SPV _AC(0x00000080, UL) 131 #define HSTATUS_GVA _AC(0x00000040, UL) 132 #define HSTATUS_VSBE _AC(0x00000020, UL) 133 134 /* HGATP flags */ 135 #define HGATP_MODE_OFF _AC(0, UL) 136 #define HGATP_MODE_SV32X4 _AC(1, UL) 137 #define HGATP_MODE_SV39X4 _AC(8, UL) 138 #define HGATP_MODE_SV48X4 _AC(9, UL) 139 #define HGATP_MODE_SV57X4 _AC(10, UL) 140 141 #define HGATP32_MODE_SHIFT 31 142 #define HGATP32_VMID_SHIFT 22 143 #define HGATP32_VMID GENMASK(28, 22) 144 #define HGATP32_PPN GENMASK(21, 0) 145 146 #define HGATP64_MODE_SHIFT 60 147 #define HGATP64_VMID_SHIFT 44 148 #define HGATP64_VMID GENMASK(57, 44) 149 #define HGATP64_PPN GENMASK(43, 0) 150 151 #define HGATP_PAGE_SHIFT 12 152 153 #ifdef CONFIG_64BIT 154 #define HGATP_PPN HGATP64_PPN 155 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 156 #define HGATP_VMID HGATP64_VMID 157 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 158 #else 159 #define HGATP_PPN HGATP32_PPN 160 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 161 #define HGATP_VMID HGATP32_VMID 162 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 163 #endif 164 165 /* VSIP & HVIP relation */ 166 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 167 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 168 (_AC(1, UL) << IRQ_S_TIMER) | \ 169 (_AC(1, UL) << IRQ_S_EXT)) 170 171 /* AIA CSR bits */ 172 #define TOPI_IID_SHIFT 16 173 #define TOPI_IID_MASK GENMASK(11, 0) 174 #define TOPI_IPRIO_MASK GENMASK(7, 0) 175 #define TOPI_IPRIO_BITS 8 176 177 #define TOPEI_ID_SHIFT 16 178 #define TOPEI_ID_MASK GENMASK(10, 0) 179 #define TOPEI_PRIO_MASK GENMASK(10, 0) 180 181 #define ISELECT_IPRIO0 0x30 182 #define ISELECT_IPRIO15 0x3f 183 #define ISELECT_MASK GENMASK(8, 0) 184 185 #define HVICTL_VTI BIT(30) 186 #define HVICTL_IID GENMASK(27, 16) 187 #define HVICTL_IID_SHIFT 16 188 #define HVICTL_DPR BIT(9) 189 #define HVICTL_IPRIOM BIT(8) 190 #define HVICTL_IPRIO GENMASK(7, 0) 191 192 /* xENVCFG flags */ 193 #define ENVCFG_STCE (_AC(1, ULL) << 63) 194 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 195 #define ENVCFG_CBZE (_AC(1, UL) << 7) 196 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 197 #define ENVCFG_CBIE_SHIFT 4 198 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 199 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 200 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 201 #define ENVCFG_CBIE_INV _AC(0x3, UL) 202 #define ENVCFG_FIOM _AC(0x1, UL) 203 204 /* symbolic CSR names: */ 205 #define CSR_CYCLE 0xc00 206 #define CSR_TIME 0xc01 207 #define CSR_INSTRET 0xc02 208 #define CSR_HPMCOUNTER3 0xc03 209 #define CSR_HPMCOUNTER4 0xc04 210 #define CSR_HPMCOUNTER5 0xc05 211 #define CSR_HPMCOUNTER6 0xc06 212 #define CSR_HPMCOUNTER7 0xc07 213 #define CSR_HPMCOUNTER8 0xc08 214 #define CSR_HPMCOUNTER9 0xc09 215 #define CSR_HPMCOUNTER10 0xc0a 216 #define CSR_HPMCOUNTER11 0xc0b 217 #define CSR_HPMCOUNTER12 0xc0c 218 #define CSR_HPMCOUNTER13 0xc0d 219 #define CSR_HPMCOUNTER14 0xc0e 220 #define CSR_HPMCOUNTER15 0xc0f 221 #define CSR_HPMCOUNTER16 0xc10 222 #define CSR_HPMCOUNTER17 0xc11 223 #define CSR_HPMCOUNTER18 0xc12 224 #define CSR_HPMCOUNTER19 0xc13 225 #define CSR_HPMCOUNTER20 0xc14 226 #define CSR_HPMCOUNTER21 0xc15 227 #define CSR_HPMCOUNTER22 0xc16 228 #define CSR_HPMCOUNTER23 0xc17 229 #define CSR_HPMCOUNTER24 0xc18 230 #define CSR_HPMCOUNTER25 0xc19 231 #define CSR_HPMCOUNTER26 0xc1a 232 #define CSR_HPMCOUNTER27 0xc1b 233 #define CSR_HPMCOUNTER28 0xc1c 234 #define CSR_HPMCOUNTER29 0xc1d 235 #define CSR_HPMCOUNTER30 0xc1e 236 #define CSR_HPMCOUNTER31 0xc1f 237 #define CSR_CYCLEH 0xc80 238 #define CSR_TIMEH 0xc81 239 #define CSR_INSTRETH 0xc82 240 #define CSR_HPMCOUNTER3H 0xc83 241 #define CSR_HPMCOUNTER4H 0xc84 242 #define CSR_HPMCOUNTER5H 0xc85 243 #define CSR_HPMCOUNTER6H 0xc86 244 #define CSR_HPMCOUNTER7H 0xc87 245 #define CSR_HPMCOUNTER8H 0xc88 246 #define CSR_HPMCOUNTER9H 0xc89 247 #define CSR_HPMCOUNTER10H 0xc8a 248 #define CSR_HPMCOUNTER11H 0xc8b 249 #define CSR_HPMCOUNTER12H 0xc8c 250 #define CSR_HPMCOUNTER13H 0xc8d 251 #define CSR_HPMCOUNTER14H 0xc8e 252 #define CSR_HPMCOUNTER15H 0xc8f 253 #define CSR_HPMCOUNTER16H 0xc90 254 #define CSR_HPMCOUNTER17H 0xc91 255 #define CSR_HPMCOUNTER18H 0xc92 256 #define CSR_HPMCOUNTER19H 0xc93 257 #define CSR_HPMCOUNTER20H 0xc94 258 #define CSR_HPMCOUNTER21H 0xc95 259 #define CSR_HPMCOUNTER22H 0xc96 260 #define CSR_HPMCOUNTER23H 0xc97 261 #define CSR_HPMCOUNTER24H 0xc98 262 #define CSR_HPMCOUNTER25H 0xc99 263 #define CSR_HPMCOUNTER26H 0xc9a 264 #define CSR_HPMCOUNTER27H 0xc9b 265 #define CSR_HPMCOUNTER28H 0xc9c 266 #define CSR_HPMCOUNTER29H 0xc9d 267 #define CSR_HPMCOUNTER30H 0xc9e 268 #define CSR_HPMCOUNTER31H 0xc9f 269 270 #define CSR_SSCOUNTOVF 0xda0 271 272 #define CSR_SSTATUS 0x100 273 #define CSR_SIE 0x104 274 #define CSR_STVEC 0x105 275 #define CSR_SCOUNTEREN 0x106 276 #define CSR_SSCRATCH 0x140 277 #define CSR_SEPC 0x141 278 #define CSR_SCAUSE 0x142 279 #define CSR_STVAL 0x143 280 #define CSR_SIP 0x144 281 #define CSR_SATP 0x180 282 283 #define CSR_STIMECMP 0x14D 284 #define CSR_STIMECMPH 0x15D 285 286 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 287 #define CSR_SISELECT 0x150 288 #define CSR_SIREG 0x151 289 290 /* Supervisor-Level Interrupts (AIA) */ 291 #define CSR_STOPEI 0x15c 292 #define CSR_STOPI 0xdb0 293 294 /* Supervisor-Level High-Half CSRs (AIA) */ 295 #define CSR_SIEH 0x114 296 #define CSR_SIPH 0x154 297 298 #define CSR_VSSTATUS 0x200 299 #define CSR_VSIE 0x204 300 #define CSR_VSTVEC 0x205 301 #define CSR_VSSCRATCH 0x240 302 #define CSR_VSEPC 0x241 303 #define CSR_VSCAUSE 0x242 304 #define CSR_VSTVAL 0x243 305 #define CSR_VSIP 0x244 306 #define CSR_VSATP 0x280 307 #define CSR_VSTIMECMP 0x24D 308 #define CSR_VSTIMECMPH 0x25D 309 310 #define CSR_HSTATUS 0x600 311 #define CSR_HEDELEG 0x602 312 #define CSR_HIDELEG 0x603 313 #define CSR_HIE 0x604 314 #define CSR_HTIMEDELTA 0x605 315 #define CSR_HCOUNTEREN 0x606 316 #define CSR_HGEIE 0x607 317 #define CSR_HENVCFG 0x60a 318 #define CSR_HTIMEDELTAH 0x615 319 #define CSR_HENVCFGH 0x61a 320 #define CSR_HTVAL 0x643 321 #define CSR_HIP 0x644 322 #define CSR_HVIP 0x645 323 #define CSR_HTINST 0x64a 324 #define CSR_HGATP 0x680 325 #define CSR_HGEIP 0xe12 326 327 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 328 #define CSR_HVIEN 0x608 329 #define CSR_HVICTL 0x609 330 #define CSR_HVIPRIO1 0x646 331 #define CSR_HVIPRIO2 0x647 332 333 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 334 #define CSR_VSISELECT 0x250 335 #define CSR_VSIREG 0x251 336 337 /* VS-Level Interrupts (H-extension with AIA) */ 338 #define CSR_VSTOPEI 0x25c 339 #define CSR_VSTOPI 0xeb0 340 341 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 342 #define CSR_HIDELEGH 0x613 343 #define CSR_HVIENH 0x618 344 #define CSR_HVIPH 0x655 345 #define CSR_HVIPRIO1H 0x656 346 #define CSR_HVIPRIO2H 0x657 347 #define CSR_VSIEH 0x214 348 #define CSR_VSIPH 0x254 349 350 #define CSR_MSTATUS 0x300 351 #define CSR_MISA 0x301 352 #define CSR_MIDELEG 0x303 353 #define CSR_MIE 0x304 354 #define CSR_MTVEC 0x305 355 #define CSR_MENVCFG 0x30a 356 #define CSR_MENVCFGH 0x31a 357 #define CSR_MSCRATCH 0x340 358 #define CSR_MEPC 0x341 359 #define CSR_MCAUSE 0x342 360 #define CSR_MTVAL 0x343 361 #define CSR_MIP 0x344 362 #define CSR_PMPCFG0 0x3a0 363 #define CSR_PMPADDR0 0x3b0 364 #define CSR_MVENDORID 0xf11 365 #define CSR_MARCHID 0xf12 366 #define CSR_MIMPID 0xf13 367 #define CSR_MHARTID 0xf14 368 369 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 370 #define CSR_MISELECT 0x350 371 #define CSR_MIREG 0x351 372 373 /* Machine-Level Interrupts (AIA) */ 374 #define CSR_MTOPEI 0x35c 375 #define CSR_MTOPI 0xfb0 376 377 /* Virtual Interrupts for Supervisor Level (AIA) */ 378 #define CSR_MVIEN 0x308 379 #define CSR_MVIP 0x309 380 381 /* Machine-Level High-Half CSRs (AIA) */ 382 #define CSR_MIDELEGH 0x313 383 #define CSR_MIEH 0x314 384 #define CSR_MVIENH 0x318 385 #define CSR_MVIPH 0x319 386 #define CSR_MIPH 0x354 387 388 #define CSR_VSTART 0x8 389 #define CSR_VCSR 0xf 390 #define CSR_VL 0xc20 391 #define CSR_VTYPE 0xc21 392 #define CSR_VLENB 0xc22 393 394 #ifdef CONFIG_RISCV_M_MODE 395 # define CSR_STATUS CSR_MSTATUS 396 # define CSR_IE CSR_MIE 397 # define CSR_TVEC CSR_MTVEC 398 # define CSR_SCRATCH CSR_MSCRATCH 399 # define CSR_EPC CSR_MEPC 400 # define CSR_CAUSE CSR_MCAUSE 401 # define CSR_TVAL CSR_MTVAL 402 # define CSR_IP CSR_MIP 403 404 # define CSR_IEH CSR_MIEH 405 # define CSR_ISELECT CSR_MISELECT 406 # define CSR_IREG CSR_MIREG 407 # define CSR_IPH CSR_MIPH 408 # define CSR_TOPEI CSR_MTOPEI 409 # define CSR_TOPI CSR_MTOPI 410 411 # define SR_IE SR_MIE 412 # define SR_PIE SR_MPIE 413 # define SR_PP SR_MPP 414 415 # define RV_IRQ_SOFT IRQ_M_SOFT 416 # define RV_IRQ_TIMER IRQ_M_TIMER 417 # define RV_IRQ_EXT IRQ_M_EXT 418 #else /* CONFIG_RISCV_M_MODE */ 419 # define CSR_STATUS CSR_SSTATUS 420 # define CSR_IE CSR_SIE 421 # define CSR_TVEC CSR_STVEC 422 # define CSR_SCRATCH CSR_SSCRATCH 423 # define CSR_EPC CSR_SEPC 424 # define CSR_CAUSE CSR_SCAUSE 425 # define CSR_TVAL CSR_STVAL 426 # define CSR_IP CSR_SIP 427 428 # define CSR_IEH CSR_SIEH 429 # define CSR_ISELECT CSR_SISELECT 430 # define CSR_IREG CSR_SIREG 431 # define CSR_IPH CSR_SIPH 432 # define CSR_TOPEI CSR_STOPEI 433 # define CSR_TOPI CSR_STOPI 434 435 # define SR_IE SR_SIE 436 # define SR_PIE SR_SPIE 437 # define SR_PP SR_SPP 438 439 # define RV_IRQ_SOFT IRQ_S_SOFT 440 # define RV_IRQ_TIMER IRQ_S_TIMER 441 # define RV_IRQ_EXT IRQ_S_EXT 442 # define RV_IRQ_PMU IRQ_PMU_OVF 443 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 444 445 #endif /* !CONFIG_RISCV_M_MODE */ 446 447 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 448 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 449 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 450 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 451 452 #ifndef __ASSEMBLY__ 453 454 #define csr_swap(csr, val) \ 455 ({ \ 456 unsigned long __v = (unsigned long)(val); \ 457 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 458 : "=r" (__v) : "rK" (__v) \ 459 : "memory"); \ 460 __v; \ 461 }) 462 463 #define csr_read(csr) \ 464 ({ \ 465 register unsigned long __v; \ 466 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 467 : "=r" (__v) : \ 468 : "memory"); \ 469 __v; \ 470 }) 471 472 #define csr_write(csr, val) \ 473 ({ \ 474 unsigned long __v = (unsigned long)(val); \ 475 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 476 : : "rK" (__v) \ 477 : "memory"); \ 478 }) 479 480 #define csr_read_set(csr, val) \ 481 ({ \ 482 unsigned long __v = (unsigned long)(val); \ 483 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 484 : "=r" (__v) : "rK" (__v) \ 485 : "memory"); \ 486 __v; \ 487 }) 488 489 #define csr_set(csr, val) \ 490 ({ \ 491 unsigned long __v = (unsigned long)(val); \ 492 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 493 : : "rK" (__v) \ 494 : "memory"); \ 495 }) 496 497 #define csr_read_clear(csr, val) \ 498 ({ \ 499 unsigned long __v = (unsigned long)(val); \ 500 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 501 : "=r" (__v) : "rK" (__v) \ 502 : "memory"); \ 503 __v; \ 504 }) 505 506 #define csr_clear(csr, val) \ 507 ({ \ 508 unsigned long __v = (unsigned long)(val); \ 509 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 510 : : "rK" (__v) \ 511 : "memory"); \ 512 }) 513 514 #endif /* __ASSEMBLY__ */ 515 516 #endif /* _ASM_RISCV_CSR_H */ 517