1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 /* zicfilp landing pad status bit */ 22 #define SR_SPELP _AC(0x00800000, UL) 23 #define SR_MPELP _AC(0x020000000000, UL) 24 #ifdef CONFIG_RISCV_M_MODE 25 #define SR_ELP SR_MPELP 26 #else 27 #define SR_ELP SR_SPELP 28 #endif 29 30 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 31 #define SR_FS_OFF _AC(0x00000000, UL) 32 #define SR_FS_INITIAL _AC(0x00002000, UL) 33 #define SR_FS_CLEAN _AC(0x00004000, UL) 34 #define SR_FS_DIRTY _AC(0x00006000, UL) 35 36 #define SR_VS _AC(0x00000600, UL) /* Vector Status */ 37 #define SR_VS_OFF _AC(0x00000000, UL) 38 #define SR_VS_INITIAL _AC(0x00000200, UL) 39 #define SR_VS_CLEAN _AC(0x00000400, UL) 40 #define SR_VS_DIRTY _AC(0x00000600, UL) 41 42 #define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ 43 #define SR_VS_OFF_THEAD _AC(0x00000000, UL) 44 #define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) 45 #define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) 46 #define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) 47 48 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 49 #define SR_XS_OFF _AC(0x00000000, UL) 50 #define SR_XS_INITIAL _AC(0x00008000, UL) 51 #define SR_XS_CLEAN _AC(0x00010000, UL) 52 #define SR_XS_DIRTY _AC(0x00018000, UL) 53 54 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 55 56 #ifndef CONFIG_64BIT 57 #define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 58 #else 59 #define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 60 #endif 61 62 #ifdef CONFIG_64BIT 63 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 64 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 65 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 66 #endif 67 68 /* SATP flags */ 69 #ifndef CONFIG_64BIT 70 #define SATP_PPN _AC(0x003FFFFF, UL) 71 #define SATP_MODE_32 _AC(0x80000000, UL) 72 #define SATP_MODE_SHIFT 31 73 #define SATP_ASID_BITS 9 74 #define SATP_ASID_SHIFT 22 75 #define SATP_ASID_MASK _AC(0x1FF, UL) 76 #else 77 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 78 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 79 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 80 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 81 #define SATP_MODE_SHIFT 60 82 #define SATP_ASID_BITS 16 83 #define SATP_ASID_SHIFT 44 84 #define SATP_ASID_MASK _AC(0xFFFF, UL) 85 #endif 86 87 /* SRMCFG fields */ 88 #define SRMCFG_RCID_MASK GENMASK(11, 0) 89 #define SRMCFG_MCID_MASK GENMASK(27, 16) 90 91 /* Exception cause high bit - is an interrupt if set */ 92 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 93 94 /* Interrupt causes (minus the high bit) */ 95 #define IRQ_S_SOFT 1 96 #define IRQ_VS_SOFT 2 97 #define IRQ_M_SOFT 3 98 #define IRQ_S_TIMER 5 99 #define IRQ_VS_TIMER 6 100 #define IRQ_M_TIMER 7 101 #define IRQ_S_EXT 9 102 #define IRQ_VS_EXT 10 103 #define IRQ_M_EXT 11 104 #define IRQ_S_GEXT 12 105 #define IRQ_PMU_OVF 13 106 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 107 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 108 109 /* Exception causes */ 110 #define EXC_INST_MISALIGNED 0 111 #define EXC_INST_ACCESS 1 112 #define EXC_INST_ILLEGAL 2 113 #define EXC_BREAKPOINT 3 114 #define EXC_LOAD_MISALIGNED 4 115 #define EXC_LOAD_ACCESS 5 116 #define EXC_STORE_MISALIGNED 6 117 #define EXC_STORE_ACCESS 7 118 #define EXC_SYSCALL 8 119 #define EXC_HYPERVISOR_SYSCALL 9 120 #define EXC_SUPERVISOR_SYSCALL 10 121 #define EXC_INST_PAGE_FAULT 12 122 #define EXC_LOAD_PAGE_FAULT 13 123 #define EXC_STORE_PAGE_FAULT 15 124 #define EXC_SOFTWARE_CHECK 18 125 #define EXC_INST_GUEST_PAGE_FAULT 20 126 #define EXC_LOAD_GUEST_PAGE_FAULT 21 127 #define EXC_VIRTUAL_INST_FAULT 22 128 #define EXC_STORE_GUEST_PAGE_FAULT 23 129 130 /* PMP configuration */ 131 #define PMP_R 0x01 132 #define PMP_W 0x02 133 #define PMP_X 0x04 134 #define PMP_A 0x18 135 #define PMP_A_TOR 0x08 136 #define PMP_A_NA4 0x10 137 #define PMP_A_NAPOT 0x18 138 #define PMP_L 0x80 139 140 /* HSTATUS flags */ 141 #ifdef CONFIG_64BIT 142 #define HSTATUS_HUPMM _AC(0x3000000000000, UL) 143 #define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL) 144 #define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL) 145 #define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL) 146 #define HSTATUS_VSXL _AC(0x300000000, UL) 147 #define HSTATUS_VSXL_SHIFT 32 148 #endif 149 #define HSTATUS_VTSR _AC(0x00400000, UL) 150 #define HSTATUS_VTW _AC(0x00200000, UL) 151 #define HSTATUS_VTVM _AC(0x00100000, UL) 152 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 153 #define HSTATUS_VGEIN_SHIFT 12 154 #define HSTATUS_HU _AC(0x00000200, UL) 155 #define HSTATUS_SPVP _AC(0x00000100, UL) 156 #define HSTATUS_SPV _AC(0x00000080, UL) 157 #define HSTATUS_GVA _AC(0x00000040, UL) 158 #define HSTATUS_VSBE _AC(0x00000020, UL) 159 160 /* HGATP flags */ 161 #define HGATP_MODE_OFF _AC(0, UL) 162 #define HGATP_MODE_SV32X4 _AC(1, UL) 163 #define HGATP_MODE_SV39X4 _AC(8, UL) 164 #define HGATP_MODE_SV48X4 _AC(9, UL) 165 #define HGATP_MODE_SV57X4 _AC(10, UL) 166 167 #define HGATP32_MODE_SHIFT 31 168 #define HGATP32_VMID_SHIFT 22 169 #define HGATP32_VMID GENMASK(28, 22) 170 #define HGATP32_PPN GENMASK(21, 0) 171 172 #define HGATP64_MODE_SHIFT 60 173 #define HGATP64_VMID_SHIFT 44 174 #define HGATP64_VMID GENMASK(57, 44) 175 #define HGATP64_PPN GENMASK(43, 0) 176 177 #define HGATP_PAGE_SHIFT 12 178 179 #ifdef CONFIG_64BIT 180 #define HGATP_PPN HGATP64_PPN 181 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 182 #define HGATP_VMID HGATP64_VMID 183 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 184 #else 185 #define HGATP_PPN HGATP32_PPN 186 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 187 #define HGATP_VMID HGATP32_VMID 188 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 189 #endif 190 191 /* VSIP & HVIP relation */ 192 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 193 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 194 (_AC(1, UL) << IRQ_S_TIMER) | \ 195 (_AC(1, UL) << IRQ_S_EXT) | \ 196 (_AC(1, UL) << IRQ_PMU_OVF)) 197 198 /* AIA CSR bits */ 199 #define TOPI_IID_SHIFT 16 200 #define TOPI_IID_MASK GENMASK(11, 0) 201 #define TOPI_IPRIO_MASK GENMASK(7, 0) 202 #define TOPI_IPRIO_BITS 8 203 204 #define TOPEI_ID_SHIFT 16 205 #define TOPEI_ID_MASK GENMASK(10, 0) 206 #define TOPEI_PRIO_MASK GENMASK(10, 0) 207 208 #define ISELECT_IPRIO0 0x30 209 #define ISELECT_IPRIO15 0x3f 210 #define ISELECT_MASK GENMASK(8, 0) 211 212 #define HVICTL_VTI BIT(30) 213 #define HVICTL_IID GENMASK(27, 16) 214 #define HVICTL_IID_SHIFT 16 215 #define HVICTL_DPR BIT(9) 216 #define HVICTL_IPRIOM BIT(8) 217 #define HVICTL_IPRIO GENMASK(7, 0) 218 219 /* xENVCFG flags */ 220 #define ENVCFG_STCE (_AC(1, ULL) << 63) 221 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 222 #define ENVCFG_ADUE (_AC(1, ULL) << 61) 223 #define ENVCFG_PMM (_AC(0x3, ULL) << 32) 224 #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32) 225 #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32) 226 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) 227 #define ENVCFG_CBZE (_AC(1, UL) << 7) 228 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 229 #define ENVCFG_LPE (_AC(1, UL) << 2) 230 #define ENVCFG_SSE (_AC(1, UL) << 3) 231 #define ENVCFG_CBIE_SHIFT 4 232 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 233 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 234 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 235 #define ENVCFG_CBIE_INV _AC(0x3, UL) 236 #define ENVCFG_FIOM _AC(0x1, UL) 237 238 /* Smstateen bits */ 239 #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 240 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) 241 #define SMSTATEEN0_AIA_SHIFT 59 242 #define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) 243 #define SMSTATEEN0_AIA_ISEL_SHIFT 60 244 #define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) 245 #define SMSTATEEN0_HSENVCFG_SHIFT 62 246 #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) 247 #define SMSTATEEN0_SSTATEEN0_SHIFT 63 248 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) 249 /* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */ 250 #define HPMEVENT_OF (BIT_ULL(63)) 251 #define HPMEVENT_MINH (BIT_ULL(62)) 252 #define HPMEVENT_SINH (BIT_ULL(61)) 253 #define HPMEVENT_UINH (BIT_ULL(60)) 254 #define HPMEVENT_VSINH (BIT_ULL(59)) 255 #define HPMEVENT_VUINH (BIT_ULL(58)) 256 #ifndef CONFIG_64BIT 257 #define HPMEVENTH_OF (BIT(31)) 258 #define HPMEVENTH_MINH (BIT(30)) 259 #define HPMEVENTH_SINH (BIT(29)) 260 #define HPMEVENTH_UINH (BIT(28)) 261 #define HPMEVENTH_VSINH (BIT(27)) 262 #define HPMEVENTH_VUINH (BIT(26)) 263 #endif 264 265 #define SISELECT_SSCCFG_BASE 0x40 266 267 /* mseccfg bits */ 268 #define MSECCFG_PMM ENVCFG_PMM 269 #define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 270 #define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 271 #define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 272 273 /* symbolic CSR names: */ 274 #define CSR_CYCLE 0xc00 275 #define CSR_TIME 0xc01 276 #define CSR_INSTRET 0xc02 277 #define CSR_HPMCOUNTER3 0xc03 278 #define CSR_HPMCOUNTER4 0xc04 279 #define CSR_HPMCOUNTER5 0xc05 280 #define CSR_HPMCOUNTER6 0xc06 281 #define CSR_HPMCOUNTER7 0xc07 282 #define CSR_HPMCOUNTER8 0xc08 283 #define CSR_HPMCOUNTER9 0xc09 284 #define CSR_HPMCOUNTER10 0xc0a 285 #define CSR_HPMCOUNTER11 0xc0b 286 #define CSR_HPMCOUNTER12 0xc0c 287 #define CSR_HPMCOUNTER13 0xc0d 288 #define CSR_HPMCOUNTER14 0xc0e 289 #define CSR_HPMCOUNTER15 0xc0f 290 #define CSR_HPMCOUNTER16 0xc10 291 #define CSR_HPMCOUNTER17 0xc11 292 #define CSR_HPMCOUNTER18 0xc12 293 #define CSR_HPMCOUNTER19 0xc13 294 #define CSR_HPMCOUNTER20 0xc14 295 #define CSR_HPMCOUNTER21 0xc15 296 #define CSR_HPMCOUNTER22 0xc16 297 #define CSR_HPMCOUNTER23 0xc17 298 #define CSR_HPMCOUNTER24 0xc18 299 #define CSR_HPMCOUNTER25 0xc19 300 #define CSR_HPMCOUNTER26 0xc1a 301 #define CSR_HPMCOUNTER27 0xc1b 302 #define CSR_HPMCOUNTER28 0xc1c 303 #define CSR_HPMCOUNTER29 0xc1d 304 #define CSR_HPMCOUNTER30 0xc1e 305 #define CSR_HPMCOUNTER31 0xc1f 306 #define CSR_CYCLEH 0xc80 307 #define CSR_TIMEH 0xc81 308 #define CSR_INSTRETH 0xc82 309 #define CSR_HPMCOUNTER3H 0xc83 310 #define CSR_HPMCOUNTER4H 0xc84 311 #define CSR_HPMCOUNTER5H 0xc85 312 #define CSR_HPMCOUNTER6H 0xc86 313 #define CSR_HPMCOUNTER7H 0xc87 314 #define CSR_HPMCOUNTER8H 0xc88 315 #define CSR_HPMCOUNTER9H 0xc89 316 #define CSR_HPMCOUNTER10H 0xc8a 317 #define CSR_HPMCOUNTER11H 0xc8b 318 #define CSR_HPMCOUNTER12H 0xc8c 319 #define CSR_HPMCOUNTER13H 0xc8d 320 #define CSR_HPMCOUNTER14H 0xc8e 321 #define CSR_HPMCOUNTER15H 0xc8f 322 #define CSR_HPMCOUNTER16H 0xc90 323 #define CSR_HPMCOUNTER17H 0xc91 324 #define CSR_HPMCOUNTER18H 0xc92 325 #define CSR_HPMCOUNTER19H 0xc93 326 #define CSR_HPMCOUNTER20H 0xc94 327 #define CSR_HPMCOUNTER21H 0xc95 328 #define CSR_HPMCOUNTER22H 0xc96 329 #define CSR_HPMCOUNTER23H 0xc97 330 #define CSR_HPMCOUNTER24H 0xc98 331 #define CSR_HPMCOUNTER25H 0xc99 332 #define CSR_HPMCOUNTER26H 0xc9a 333 #define CSR_HPMCOUNTER27H 0xc9b 334 #define CSR_HPMCOUNTER28H 0xc9c 335 #define CSR_HPMCOUNTER29H 0xc9d 336 #define CSR_HPMCOUNTER30H 0xc9e 337 #define CSR_HPMCOUNTER31H 0xc9f 338 339 #define CSR_SCOUNTOVF 0xda0 340 341 #define CSR_SSTATUS 0x100 342 #define CSR_SIE 0x104 343 #define CSR_STVEC 0x105 344 #define CSR_SCOUNTEREN 0x106 345 #define CSR_SENVCFG 0x10a 346 #define CSR_SSTATEEN0 0x10c 347 #define CSR_SCOUNTINHIBIT 0x120 348 #define CSR_SSCRATCH 0x140 349 #define CSR_SEPC 0x141 350 #define CSR_SCAUSE 0x142 351 #define CSR_STVAL 0x143 352 #define CSR_SIP 0x144 353 #define CSR_SATP 0x180 354 #define CSR_SRMCFG 0x181 355 356 #define CSR_STIMECMP 0x14D 357 #define CSR_STIMECMPH 0x15D 358 359 /* zicfiss user mode csr. CSR_SSP holds current shadow stack pointer */ 360 #define CSR_SSP 0x011 361 362 /* xtheadvector symbolic CSR names */ 363 #define CSR_VXSAT 0x9 364 #define CSR_VXRM 0xa 365 366 /* xtheadvector CSR masks */ 367 #define CSR_VXRM_MASK 3 368 #define CSR_VXRM_SHIFT 1 369 #define CSR_VXSAT_MASK 1 370 371 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 372 #define CSR_SISELECT 0x150 373 #define CSR_SIREG 0x151 374 /* Supervisor-Level Window to Indirectly Accessed Registers (Sscsrind) */ 375 #define CSR_SIREG2 0x152 376 #define CSR_SIREG3 0x153 377 #define CSR_SIREG4 0x155 378 #define CSR_SIREG5 0x156 379 #define CSR_SIREG6 0x157 380 381 /* Supervisor-Level Interrupts (AIA) */ 382 #define CSR_STOPEI 0x15c 383 #define CSR_STOPI 0xdb0 384 385 /* Supervisor-Level High-Half CSRs (AIA) */ 386 #define CSR_SIEH 0x114 387 #define CSR_SIPH 0x154 388 389 #define CSR_VSSTATUS 0x200 390 #define CSR_VSIE 0x204 391 #define CSR_VSTVEC 0x205 392 #define CSR_VSSCRATCH 0x240 393 #define CSR_VSEPC 0x241 394 #define CSR_VSCAUSE 0x242 395 #define CSR_VSTVAL 0x243 396 #define CSR_VSIP 0x244 397 #define CSR_VSATP 0x280 398 #define CSR_VSTIMECMP 0x24D 399 #define CSR_VSTIMECMPH 0x25D 400 401 #define CSR_HSTATUS 0x600 402 #define CSR_HEDELEG 0x602 403 #define CSR_HIDELEG 0x603 404 #define CSR_HIE 0x604 405 #define CSR_HTIMEDELTA 0x605 406 #define CSR_HCOUNTEREN 0x606 407 #define CSR_HGEIE 0x607 408 #define CSR_HENVCFG 0x60a 409 #define CSR_HTIMEDELTAH 0x615 410 #define CSR_HENVCFGH 0x61a 411 #define CSR_HTVAL 0x643 412 #define CSR_HIP 0x644 413 #define CSR_HVIP 0x645 414 #define CSR_HTINST 0x64a 415 #define CSR_HGATP 0x680 416 #define CSR_HGEIP 0xe12 417 418 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 419 #define CSR_HVIEN 0x608 420 #define CSR_HVICTL 0x609 421 #define CSR_HVIPRIO1 0x646 422 #define CSR_HVIPRIO2 0x647 423 424 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 425 #define CSR_VSISELECT 0x250 426 #define CSR_VSIREG 0x251 427 /* 428 * VS-Level Window to Indirectly Accessed Registers (H-extension with Sscsrind) 429 */ 430 #define CSR_VSIREG2 0x252 431 #define CSR_VSIREG3 0x253 432 #define CSR_VSIREG4 0x255 433 #define CSR_VSIREG5 0x256 434 #define CSR_VSIREG6 0x257 435 436 /* VS-Level Interrupts (H-extension with AIA) */ 437 #define CSR_VSTOPEI 0x25c 438 #define CSR_VSTOPI 0xeb0 439 440 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 441 #define CSR_HIDELEGH 0x613 442 #define CSR_HVIENH 0x618 443 #define CSR_HVIPH 0x655 444 #define CSR_HVIPRIO1H 0x656 445 #define CSR_HVIPRIO2H 0x657 446 #define CSR_VSIEH 0x214 447 #define CSR_VSIPH 0x254 448 449 /* Hypervisor stateen CSRs */ 450 #define CSR_HSTATEEN0 0x60c 451 #define CSR_HSTATEEN0H 0x61c 452 453 #define CSR_MSTATUS 0x300 454 #define CSR_MISA 0x301 455 #define CSR_MIDELEG 0x303 456 #define CSR_MIE 0x304 457 #define CSR_MTVEC 0x305 458 #define CSR_MENVCFG 0x30a 459 #define CSR_MENVCFGH 0x31a 460 #define CSR_MSCRATCH 0x340 461 #define CSR_MEPC 0x341 462 #define CSR_MCAUSE 0x342 463 #define CSR_MTVAL 0x343 464 #define CSR_MIP 0x344 465 #define CSR_PMPCFG0 0x3a0 466 #define CSR_PMPADDR0 0x3b0 467 #define CSR_MSECCFG 0x747 468 #define CSR_MSECCFGH 0x757 469 #define CSR_MVENDORID 0xf11 470 #define CSR_MARCHID 0xf12 471 #define CSR_MIMPID 0xf13 472 #define CSR_MHARTID 0xf14 473 474 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 475 #define CSR_MISELECT 0x350 476 #define CSR_MIREG 0x351 477 /* Machine-Level Window to Indirectly Accessed Registers (Smcsrind) */ 478 #define CSR_MIREG2 0x352 479 #define CSR_MIREG3 0x353 480 #define CSR_MIREG4 0x355 481 #define CSR_MIREG5 0x356 482 #define CSR_MIREG6 0x357 483 484 /* Machine-Level Interrupts (AIA) */ 485 #define CSR_MTOPEI 0x35c 486 #define CSR_MTOPI 0xfb0 487 488 /* Virtual Interrupts for Supervisor Level (AIA) */ 489 #define CSR_MVIEN 0x308 490 #define CSR_MVIP 0x309 491 492 /* Machine-Level High-Half CSRs (AIA) */ 493 #define CSR_MIDELEGH 0x313 494 #define CSR_MIEH 0x314 495 #define CSR_MVIENH 0x318 496 #define CSR_MVIPH 0x319 497 #define CSR_MIPH 0x354 498 499 #define CSR_VSTART 0x8 500 #define CSR_VCSR 0xf 501 #define CSR_VL 0xc20 502 #define CSR_VTYPE 0xc21 503 #define CSR_VLENB 0xc22 504 505 #define VTYPE_VLMUL _AC(7, UL) 506 #define VTYPE_VLMUL_FRAC _AC(4, UL) 507 #define VTYPE_VSEW_SHIFT 3 508 #define VTYPE_VSEW (_AC(7, UL) << VTYPE_VSEW_SHIFT) 509 #define VTYPE_VTA_SHIFT 6 510 #define VTYPE_VTA (_AC(1, UL) << VTYPE_VTA_SHIFT) 511 #define VTYPE_VMA_SHIFT 7 512 #define VTYPE_VMA (_AC(1, UL) << VTYPE_VMA_SHIFT) 513 #define VTYPE_VILL_SHIFT (__riscv_xlen - 1) 514 #define VTYPE_VILL (_AC(1, UL) << VTYPE_VILL_SHIFT) 515 516 #define VTYPE_VLMUL_THEAD _AC(3, UL) 517 #define VTYPE_VSEW_THEAD_SHIFT 2 518 #define VTYPE_VSEW_THEAD (_AC(7, UL) << VTYPE_VSEW_THEAD_SHIFT) 519 #define VTYPE_VEDIV_THEAD_SHIFT 5 520 #define VTYPE_VEDIV_THEAD (_AC(3, UL) << VTYPE_VEDIV_THEAD_SHIFT) 521 522 /* Scalar Crypto Extension - Entropy */ 523 #define CSR_SEED 0x015 524 #define SEED_OPST_MASK _AC(0xC0000000, UL) 525 #define SEED_OPST_BIST _AC(0x00000000, UL) 526 #define SEED_OPST_WAIT _AC(0x40000000, UL) 527 #define SEED_OPST_ES16 _AC(0x80000000, UL) 528 #define SEED_OPST_DEAD _AC(0xC0000000, UL) 529 #define SEED_ENTROPY_MASK _AC(0xFFFF, UL) 530 531 #ifdef CONFIG_RISCV_M_MODE 532 # define CSR_STATUS CSR_MSTATUS 533 # define CSR_IE CSR_MIE 534 # define CSR_TVEC CSR_MTVEC 535 # define CSR_ENVCFG CSR_MENVCFG 536 # define CSR_SCRATCH CSR_MSCRATCH 537 # define CSR_EPC CSR_MEPC 538 # define CSR_CAUSE CSR_MCAUSE 539 # define CSR_TVAL CSR_MTVAL 540 # define CSR_IP CSR_MIP 541 542 # define CSR_IEH CSR_MIEH 543 # define CSR_ISELECT CSR_MISELECT 544 # define CSR_IREG CSR_MIREG 545 # define CSR_IREG2 CSR_MIREG2 546 # define CSR_IREG3 CSR_MIREG3 547 # define CSR_IREG4 CSR_MIREG4 548 # define CSR_IREG5 CSR_MIREG5 549 # define CSR_IREG6 CSR_MIREG6 550 # define CSR_IPH CSR_MIPH 551 # define CSR_TOPEI CSR_MTOPEI 552 # define CSR_TOPI CSR_MTOPI 553 554 # define SR_IE SR_MIE 555 # define SR_PIE SR_MPIE 556 # define SR_PP SR_MPP 557 558 # define RV_IRQ_SOFT IRQ_M_SOFT 559 # define RV_IRQ_TIMER IRQ_M_TIMER 560 # define RV_IRQ_EXT IRQ_M_EXT 561 #else /* CONFIG_RISCV_M_MODE */ 562 # define CSR_STATUS CSR_SSTATUS 563 # define CSR_IE CSR_SIE 564 # define CSR_TVEC CSR_STVEC 565 # define CSR_ENVCFG CSR_SENVCFG 566 # define CSR_SCRATCH CSR_SSCRATCH 567 # define CSR_EPC CSR_SEPC 568 # define CSR_CAUSE CSR_SCAUSE 569 # define CSR_TVAL CSR_STVAL 570 # define CSR_IP CSR_SIP 571 572 # define CSR_IEH CSR_SIEH 573 # define CSR_ISELECT CSR_SISELECT 574 # define CSR_IREG CSR_SIREG 575 # define CSR_IREG2 CSR_SIREG2 576 # define CSR_IREG3 CSR_SIREG3 577 # define CSR_IREG4 CSR_SIREG4 578 # define CSR_IREG5 CSR_SIREG5 579 # define CSR_IREG6 CSR_SIREG6 580 # define CSR_IPH CSR_SIPH 581 # define CSR_TOPEI CSR_STOPEI 582 # define CSR_TOPI CSR_STOPI 583 584 # define SR_IE SR_SIE 585 # define SR_PIE SR_SPIE 586 # define SR_PP SR_SPP 587 588 # define RV_IRQ_SOFT IRQ_S_SOFT 589 # define RV_IRQ_TIMER IRQ_S_TIMER 590 # define RV_IRQ_EXT IRQ_S_EXT 591 # define RV_IRQ_PMU IRQ_PMU_OVF 592 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 593 594 #endif /* !CONFIG_RISCV_M_MODE */ 595 596 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 597 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 598 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 599 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 600 601 #ifndef __ASSEMBLER__ 602 603 #define csr_swap(csr, val) \ 604 ({ \ 605 unsigned long __v = (unsigned long)(val); \ 606 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 607 : "=r" (__v) : "rK" (__v) \ 608 : "memory"); \ 609 __v; \ 610 }) 611 612 #define csr_read(csr) \ 613 ({ \ 614 register unsigned long __v; \ 615 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 616 : "=r" (__v) : \ 617 : "memory"); \ 618 __v; \ 619 }) 620 621 #define csr_write(csr, val) \ 622 ({ \ 623 unsigned long __v = (unsigned long)(val); \ 624 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 625 : : "rK" (__v) \ 626 : "memory"); \ 627 }) 628 629 #define csr_read_set(csr, val) \ 630 ({ \ 631 unsigned long __v = (unsigned long)(val); \ 632 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 633 : "=r" (__v) : "rK" (__v) \ 634 : "memory"); \ 635 __v; \ 636 }) 637 638 #define csr_set(csr, val) \ 639 ({ \ 640 unsigned long __v = (unsigned long)(val); \ 641 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 642 : : "rK" (__v) \ 643 : "memory"); \ 644 }) 645 646 #define csr_read_clear(csr, val) \ 647 ({ \ 648 unsigned long __v = (unsigned long)(val); \ 649 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 650 : "=r" (__v) : "rK" (__v) \ 651 : "memory"); \ 652 __v; \ 653 }) 654 655 #define csr_clear(csr, val) \ 656 ({ \ 657 unsigned long __v = (unsigned long)(val); \ 658 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 659 : : "rK" (__v) \ 660 : "memory"); \ 661 }) 662 663 #endif /* __ASSEMBLER__ */ 664 665 #endif /* _ASM_RISCV_CSR_H */ 666