1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CSR_H 7 #define _ASM_RISCV_CSR_H 8 9 #include <asm/asm.h> 10 #include <linux/bits.h> 11 12 /* Status register flags */ 13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 #define SR_FS_OFF _AC(0x00000000, UL) 23 #define SR_FS_INITIAL _AC(0x00002000, UL) 24 #define SR_FS_CLEAN _AC(0x00004000, UL) 25 #define SR_FS_DIRTY _AC(0x00006000, UL) 26 27 #define SR_VS _AC(0x00000600, UL) /* Vector Status */ 28 #define SR_VS_OFF _AC(0x00000000, UL) 29 #define SR_VS_INITIAL _AC(0x00000200, UL) 30 #define SR_VS_CLEAN _AC(0x00000400, UL) 31 #define SR_VS_DIRTY _AC(0x00000600, UL) 32 33 #define SR_XS _AC(0x00018000, UL) /* Extension Status */ 34 #define SR_XS_OFF _AC(0x00000000, UL) 35 #define SR_XS_INITIAL _AC(0x00008000, UL) 36 #define SR_XS_CLEAN _AC(0x00010000, UL) 37 #define SR_XS_DIRTY _AC(0x00018000, UL) 38 39 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 40 41 #ifndef CONFIG_64BIT 42 #define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 43 #else 44 #define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 45 #endif 46 47 #ifdef CONFIG_64BIT 48 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 49 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 50 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 51 #endif 52 53 /* SATP flags */ 54 #ifndef CONFIG_64BIT 55 #define SATP_PPN _AC(0x003FFFFF, UL) 56 #define SATP_MODE_32 _AC(0x80000000, UL) 57 #define SATP_MODE_SHIFT 31 58 #define SATP_ASID_BITS 9 59 #define SATP_ASID_SHIFT 22 60 #define SATP_ASID_MASK _AC(0x1FF, UL) 61 #else 62 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 63 #define SATP_MODE_39 _AC(0x8000000000000000, UL) 64 #define SATP_MODE_48 _AC(0x9000000000000000, UL) 65 #define SATP_MODE_57 _AC(0xa000000000000000, UL) 66 #define SATP_MODE_SHIFT 60 67 #define SATP_ASID_BITS 16 68 #define SATP_ASID_SHIFT 44 69 #define SATP_ASID_MASK _AC(0xFFFF, UL) 70 #endif 71 72 /* Exception cause high bit - is an interrupt if set */ 73 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 74 75 /* Interrupt causes (minus the high bit) */ 76 #define IRQ_S_SOFT 1 77 #define IRQ_VS_SOFT 2 78 #define IRQ_M_SOFT 3 79 #define IRQ_S_TIMER 5 80 #define IRQ_VS_TIMER 6 81 #define IRQ_M_TIMER 7 82 #define IRQ_S_EXT 9 83 #define IRQ_VS_EXT 10 84 #define IRQ_M_EXT 11 85 #define IRQ_S_GEXT 12 86 #define IRQ_PMU_OVF 13 87 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 88 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 89 90 /* Exception causes */ 91 #define EXC_INST_MISALIGNED 0 92 #define EXC_INST_ACCESS 1 93 #define EXC_INST_ILLEGAL 2 94 #define EXC_BREAKPOINT 3 95 #define EXC_LOAD_MISALIGNED 4 96 #define EXC_LOAD_ACCESS 5 97 #define EXC_STORE_MISALIGNED 6 98 #define EXC_STORE_ACCESS 7 99 #define EXC_SYSCALL 8 100 #define EXC_HYPERVISOR_SYSCALL 9 101 #define EXC_SUPERVISOR_SYSCALL 10 102 #define EXC_INST_PAGE_FAULT 12 103 #define EXC_LOAD_PAGE_FAULT 13 104 #define EXC_STORE_PAGE_FAULT 15 105 #define EXC_INST_GUEST_PAGE_FAULT 20 106 #define EXC_LOAD_GUEST_PAGE_FAULT 21 107 #define EXC_VIRTUAL_INST_FAULT 22 108 #define EXC_STORE_GUEST_PAGE_FAULT 23 109 110 /* PMP configuration */ 111 #define PMP_R 0x01 112 #define PMP_W 0x02 113 #define PMP_X 0x04 114 #define PMP_A 0x18 115 #define PMP_A_TOR 0x08 116 #define PMP_A_NA4 0x10 117 #define PMP_A_NAPOT 0x18 118 #define PMP_L 0x80 119 120 /* HSTATUS flags */ 121 #ifdef CONFIG_64BIT 122 #define HSTATUS_HUPMM _AC(0x3000000000000, UL) 123 #define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL) 124 #define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL) 125 #define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL) 126 #define HSTATUS_VSXL _AC(0x300000000, UL) 127 #define HSTATUS_VSXL_SHIFT 32 128 #endif 129 #define HSTATUS_VTSR _AC(0x00400000, UL) 130 #define HSTATUS_VTW _AC(0x00200000, UL) 131 #define HSTATUS_VTVM _AC(0x00100000, UL) 132 #define HSTATUS_VGEIN _AC(0x0003f000, UL) 133 #define HSTATUS_VGEIN_SHIFT 12 134 #define HSTATUS_HU _AC(0x00000200, UL) 135 #define HSTATUS_SPVP _AC(0x00000100, UL) 136 #define HSTATUS_SPV _AC(0x00000080, UL) 137 #define HSTATUS_GVA _AC(0x00000040, UL) 138 #define HSTATUS_VSBE _AC(0x00000020, UL) 139 140 /* HGATP flags */ 141 #define HGATP_MODE_OFF _AC(0, UL) 142 #define HGATP_MODE_SV32X4 _AC(1, UL) 143 #define HGATP_MODE_SV39X4 _AC(8, UL) 144 #define HGATP_MODE_SV48X4 _AC(9, UL) 145 #define HGATP_MODE_SV57X4 _AC(10, UL) 146 147 #define HGATP32_MODE_SHIFT 31 148 #define HGATP32_VMID_SHIFT 22 149 #define HGATP32_VMID GENMASK(28, 22) 150 #define HGATP32_PPN GENMASK(21, 0) 151 152 #define HGATP64_MODE_SHIFT 60 153 #define HGATP64_VMID_SHIFT 44 154 #define HGATP64_VMID GENMASK(57, 44) 155 #define HGATP64_PPN GENMASK(43, 0) 156 157 #define HGATP_PAGE_SHIFT 12 158 159 #ifdef CONFIG_64BIT 160 #define HGATP_PPN HGATP64_PPN 161 #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 162 #define HGATP_VMID HGATP64_VMID 163 #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 164 #else 165 #define HGATP_PPN HGATP32_PPN 166 #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 167 #define HGATP_VMID HGATP32_VMID 168 #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 169 #endif 170 171 /* VSIP & HVIP relation */ 172 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 173 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 174 (_AC(1, UL) << IRQ_S_TIMER) | \ 175 (_AC(1, UL) << IRQ_S_EXT) | \ 176 (_AC(1, UL) << IRQ_PMU_OVF)) 177 178 /* AIA CSR bits */ 179 #define TOPI_IID_SHIFT 16 180 #define TOPI_IID_MASK GENMASK(11, 0) 181 #define TOPI_IPRIO_MASK GENMASK(7, 0) 182 #define TOPI_IPRIO_BITS 8 183 184 #define TOPEI_ID_SHIFT 16 185 #define TOPEI_ID_MASK GENMASK(10, 0) 186 #define TOPEI_PRIO_MASK GENMASK(10, 0) 187 188 #define ISELECT_IPRIO0 0x30 189 #define ISELECT_IPRIO15 0x3f 190 #define ISELECT_MASK GENMASK(8, 0) 191 192 #define HVICTL_VTI BIT(30) 193 #define HVICTL_IID GENMASK(27, 16) 194 #define HVICTL_IID_SHIFT 16 195 #define HVICTL_DPR BIT(9) 196 #define HVICTL_IPRIOM BIT(8) 197 #define HVICTL_IPRIO GENMASK(7, 0) 198 199 /* xENVCFG flags */ 200 #define ENVCFG_STCE (_AC(1, ULL) << 63) 201 #define ENVCFG_PBMTE (_AC(1, ULL) << 62) 202 #define ENVCFG_PMM (_AC(0x3, ULL) << 32) 203 #define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32) 204 #define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32) 205 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) 206 #define ENVCFG_CBZE (_AC(1, UL) << 7) 207 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 208 #define ENVCFG_CBIE_SHIFT 4 209 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 210 #define ENVCFG_CBIE_ILL _AC(0x0, UL) 211 #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 212 #define ENVCFG_CBIE_INV _AC(0x3, UL) 213 #define ENVCFG_FIOM _AC(0x1, UL) 214 215 /* Smstateen bits */ 216 #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 217 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) 218 #define SMSTATEEN0_AIA_SHIFT 59 219 #define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) 220 #define SMSTATEEN0_AIA_ISEL_SHIFT 60 221 #define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) 222 #define SMSTATEEN0_HSENVCFG_SHIFT 62 223 #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) 224 #define SMSTATEEN0_SSTATEEN0_SHIFT 63 225 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) 226 227 /* mseccfg bits */ 228 #define MSECCFG_PMM ENVCFG_PMM 229 #define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 230 #define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 231 #define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 232 233 /* symbolic CSR names: */ 234 #define CSR_CYCLE 0xc00 235 #define CSR_TIME 0xc01 236 #define CSR_INSTRET 0xc02 237 #define CSR_HPMCOUNTER3 0xc03 238 #define CSR_HPMCOUNTER4 0xc04 239 #define CSR_HPMCOUNTER5 0xc05 240 #define CSR_HPMCOUNTER6 0xc06 241 #define CSR_HPMCOUNTER7 0xc07 242 #define CSR_HPMCOUNTER8 0xc08 243 #define CSR_HPMCOUNTER9 0xc09 244 #define CSR_HPMCOUNTER10 0xc0a 245 #define CSR_HPMCOUNTER11 0xc0b 246 #define CSR_HPMCOUNTER12 0xc0c 247 #define CSR_HPMCOUNTER13 0xc0d 248 #define CSR_HPMCOUNTER14 0xc0e 249 #define CSR_HPMCOUNTER15 0xc0f 250 #define CSR_HPMCOUNTER16 0xc10 251 #define CSR_HPMCOUNTER17 0xc11 252 #define CSR_HPMCOUNTER18 0xc12 253 #define CSR_HPMCOUNTER19 0xc13 254 #define CSR_HPMCOUNTER20 0xc14 255 #define CSR_HPMCOUNTER21 0xc15 256 #define CSR_HPMCOUNTER22 0xc16 257 #define CSR_HPMCOUNTER23 0xc17 258 #define CSR_HPMCOUNTER24 0xc18 259 #define CSR_HPMCOUNTER25 0xc19 260 #define CSR_HPMCOUNTER26 0xc1a 261 #define CSR_HPMCOUNTER27 0xc1b 262 #define CSR_HPMCOUNTER28 0xc1c 263 #define CSR_HPMCOUNTER29 0xc1d 264 #define CSR_HPMCOUNTER30 0xc1e 265 #define CSR_HPMCOUNTER31 0xc1f 266 #define CSR_CYCLEH 0xc80 267 #define CSR_TIMEH 0xc81 268 #define CSR_INSTRETH 0xc82 269 #define CSR_HPMCOUNTER3H 0xc83 270 #define CSR_HPMCOUNTER4H 0xc84 271 #define CSR_HPMCOUNTER5H 0xc85 272 #define CSR_HPMCOUNTER6H 0xc86 273 #define CSR_HPMCOUNTER7H 0xc87 274 #define CSR_HPMCOUNTER8H 0xc88 275 #define CSR_HPMCOUNTER9H 0xc89 276 #define CSR_HPMCOUNTER10H 0xc8a 277 #define CSR_HPMCOUNTER11H 0xc8b 278 #define CSR_HPMCOUNTER12H 0xc8c 279 #define CSR_HPMCOUNTER13H 0xc8d 280 #define CSR_HPMCOUNTER14H 0xc8e 281 #define CSR_HPMCOUNTER15H 0xc8f 282 #define CSR_HPMCOUNTER16H 0xc90 283 #define CSR_HPMCOUNTER17H 0xc91 284 #define CSR_HPMCOUNTER18H 0xc92 285 #define CSR_HPMCOUNTER19H 0xc93 286 #define CSR_HPMCOUNTER20H 0xc94 287 #define CSR_HPMCOUNTER21H 0xc95 288 #define CSR_HPMCOUNTER22H 0xc96 289 #define CSR_HPMCOUNTER23H 0xc97 290 #define CSR_HPMCOUNTER24H 0xc98 291 #define CSR_HPMCOUNTER25H 0xc99 292 #define CSR_HPMCOUNTER26H 0xc9a 293 #define CSR_HPMCOUNTER27H 0xc9b 294 #define CSR_HPMCOUNTER28H 0xc9c 295 #define CSR_HPMCOUNTER29H 0xc9d 296 #define CSR_HPMCOUNTER30H 0xc9e 297 #define CSR_HPMCOUNTER31H 0xc9f 298 299 #define CSR_SCOUNTOVF 0xda0 300 301 #define CSR_SSTATUS 0x100 302 #define CSR_SIE 0x104 303 #define CSR_STVEC 0x105 304 #define CSR_SCOUNTEREN 0x106 305 #define CSR_SENVCFG 0x10a 306 #define CSR_SSTATEEN0 0x10c 307 #define CSR_SSCRATCH 0x140 308 #define CSR_SEPC 0x141 309 #define CSR_SCAUSE 0x142 310 #define CSR_STVAL 0x143 311 #define CSR_SIP 0x144 312 #define CSR_SATP 0x180 313 314 #define CSR_STIMECMP 0x14D 315 #define CSR_STIMECMPH 0x15D 316 317 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 318 #define CSR_SISELECT 0x150 319 #define CSR_SIREG 0x151 320 321 /* Supervisor-Level Interrupts (AIA) */ 322 #define CSR_STOPEI 0x15c 323 #define CSR_STOPI 0xdb0 324 325 /* Supervisor-Level High-Half CSRs (AIA) */ 326 #define CSR_SIEH 0x114 327 #define CSR_SIPH 0x154 328 329 #define CSR_VSSTATUS 0x200 330 #define CSR_VSIE 0x204 331 #define CSR_VSTVEC 0x205 332 #define CSR_VSSCRATCH 0x240 333 #define CSR_VSEPC 0x241 334 #define CSR_VSCAUSE 0x242 335 #define CSR_VSTVAL 0x243 336 #define CSR_VSIP 0x244 337 #define CSR_VSATP 0x280 338 #define CSR_VSTIMECMP 0x24D 339 #define CSR_VSTIMECMPH 0x25D 340 341 #define CSR_HSTATUS 0x600 342 #define CSR_HEDELEG 0x602 343 #define CSR_HIDELEG 0x603 344 #define CSR_HIE 0x604 345 #define CSR_HTIMEDELTA 0x605 346 #define CSR_HCOUNTEREN 0x606 347 #define CSR_HGEIE 0x607 348 #define CSR_HENVCFG 0x60a 349 #define CSR_HTIMEDELTAH 0x615 350 #define CSR_HENVCFGH 0x61a 351 #define CSR_HTVAL 0x643 352 #define CSR_HIP 0x644 353 #define CSR_HVIP 0x645 354 #define CSR_HTINST 0x64a 355 #define CSR_HGATP 0x680 356 #define CSR_HGEIP 0xe12 357 358 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 359 #define CSR_HVIEN 0x608 360 #define CSR_HVICTL 0x609 361 #define CSR_HVIPRIO1 0x646 362 #define CSR_HVIPRIO2 0x647 363 364 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 365 #define CSR_VSISELECT 0x250 366 #define CSR_VSIREG 0x251 367 368 /* VS-Level Interrupts (H-extension with AIA) */ 369 #define CSR_VSTOPEI 0x25c 370 #define CSR_VSTOPI 0xeb0 371 372 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 373 #define CSR_HIDELEGH 0x613 374 #define CSR_HVIENH 0x618 375 #define CSR_HVIPH 0x655 376 #define CSR_HVIPRIO1H 0x656 377 #define CSR_HVIPRIO2H 0x657 378 #define CSR_VSIEH 0x214 379 #define CSR_VSIPH 0x254 380 381 /* Hypervisor stateen CSRs */ 382 #define CSR_HSTATEEN0 0x60c 383 #define CSR_HSTATEEN0H 0x61c 384 385 #define CSR_MSTATUS 0x300 386 #define CSR_MISA 0x301 387 #define CSR_MIDELEG 0x303 388 #define CSR_MIE 0x304 389 #define CSR_MTVEC 0x305 390 #define CSR_MENVCFG 0x30a 391 #define CSR_MENVCFGH 0x31a 392 #define CSR_MSCRATCH 0x340 393 #define CSR_MEPC 0x341 394 #define CSR_MCAUSE 0x342 395 #define CSR_MTVAL 0x343 396 #define CSR_MIP 0x344 397 #define CSR_PMPCFG0 0x3a0 398 #define CSR_PMPADDR0 0x3b0 399 #define CSR_MSECCFG 0x747 400 #define CSR_MSECCFGH 0x757 401 #define CSR_MVENDORID 0xf11 402 #define CSR_MARCHID 0xf12 403 #define CSR_MIMPID 0xf13 404 #define CSR_MHARTID 0xf14 405 406 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 407 #define CSR_MISELECT 0x350 408 #define CSR_MIREG 0x351 409 410 /* Machine-Level Interrupts (AIA) */ 411 #define CSR_MTOPEI 0x35c 412 #define CSR_MTOPI 0xfb0 413 414 /* Virtual Interrupts for Supervisor Level (AIA) */ 415 #define CSR_MVIEN 0x308 416 #define CSR_MVIP 0x309 417 418 /* Machine-Level High-Half CSRs (AIA) */ 419 #define CSR_MIDELEGH 0x313 420 #define CSR_MIEH 0x314 421 #define CSR_MVIENH 0x318 422 #define CSR_MVIPH 0x319 423 #define CSR_MIPH 0x354 424 425 #define CSR_VSTART 0x8 426 #define CSR_VCSR 0xf 427 #define CSR_VL 0xc20 428 #define CSR_VTYPE 0xc21 429 #define CSR_VLENB 0xc22 430 431 /* Scalar Crypto Extension - Entropy */ 432 #define CSR_SEED 0x015 433 #define SEED_OPST_MASK _AC(0xC0000000, UL) 434 #define SEED_OPST_BIST _AC(0x00000000, UL) 435 #define SEED_OPST_WAIT _AC(0x40000000, UL) 436 #define SEED_OPST_ES16 _AC(0x80000000, UL) 437 #define SEED_OPST_DEAD _AC(0xC0000000, UL) 438 #define SEED_ENTROPY_MASK _AC(0xFFFF, UL) 439 440 #ifdef CONFIG_RISCV_M_MODE 441 # define CSR_STATUS CSR_MSTATUS 442 # define CSR_IE CSR_MIE 443 # define CSR_TVEC CSR_MTVEC 444 # define CSR_ENVCFG CSR_MENVCFG 445 # define CSR_SCRATCH CSR_MSCRATCH 446 # define CSR_EPC CSR_MEPC 447 # define CSR_CAUSE CSR_MCAUSE 448 # define CSR_TVAL CSR_MTVAL 449 # define CSR_IP CSR_MIP 450 451 # define CSR_IEH CSR_MIEH 452 # define CSR_ISELECT CSR_MISELECT 453 # define CSR_IREG CSR_MIREG 454 # define CSR_IPH CSR_MIPH 455 # define CSR_TOPEI CSR_MTOPEI 456 # define CSR_TOPI CSR_MTOPI 457 458 # define SR_IE SR_MIE 459 # define SR_PIE SR_MPIE 460 # define SR_PP SR_MPP 461 462 # define RV_IRQ_SOFT IRQ_M_SOFT 463 # define RV_IRQ_TIMER IRQ_M_TIMER 464 # define RV_IRQ_EXT IRQ_M_EXT 465 #else /* CONFIG_RISCV_M_MODE */ 466 # define CSR_STATUS CSR_SSTATUS 467 # define CSR_IE CSR_SIE 468 # define CSR_TVEC CSR_STVEC 469 # define CSR_ENVCFG CSR_SENVCFG 470 # define CSR_SCRATCH CSR_SSCRATCH 471 # define CSR_EPC CSR_SEPC 472 # define CSR_CAUSE CSR_SCAUSE 473 # define CSR_TVAL CSR_STVAL 474 # define CSR_IP CSR_SIP 475 476 # define CSR_IEH CSR_SIEH 477 # define CSR_ISELECT CSR_SISELECT 478 # define CSR_IREG CSR_SIREG 479 # define CSR_IPH CSR_SIPH 480 # define CSR_TOPEI CSR_STOPEI 481 # define CSR_TOPI CSR_STOPI 482 483 # define SR_IE SR_SIE 484 # define SR_PIE SR_SPIE 485 # define SR_PP SR_SPP 486 487 # define RV_IRQ_SOFT IRQ_S_SOFT 488 # define RV_IRQ_TIMER IRQ_S_TIMER 489 # define RV_IRQ_EXT IRQ_S_EXT 490 # define RV_IRQ_PMU IRQ_PMU_OVF 491 # define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 492 493 #endif /* !CONFIG_RISCV_M_MODE */ 494 495 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 496 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 497 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 498 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 499 500 #ifndef __ASSEMBLY__ 501 502 #define csr_swap(csr, val) \ 503 ({ \ 504 unsigned long __v = (unsigned long)(val); \ 505 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 506 : "=r" (__v) : "rK" (__v) \ 507 : "memory"); \ 508 __v; \ 509 }) 510 511 #define csr_read(csr) \ 512 ({ \ 513 register unsigned long __v; \ 514 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 515 : "=r" (__v) : \ 516 : "memory"); \ 517 __v; \ 518 }) 519 520 #define csr_write(csr, val) \ 521 ({ \ 522 unsigned long __v = (unsigned long)(val); \ 523 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 524 : : "rK" (__v) \ 525 : "memory"); \ 526 }) 527 528 #define csr_read_set(csr, val) \ 529 ({ \ 530 unsigned long __v = (unsigned long)(val); \ 531 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 532 : "=r" (__v) : "rK" (__v) \ 533 : "memory"); \ 534 __v; \ 535 }) 536 537 #define csr_set(csr, val) \ 538 ({ \ 539 unsigned long __v = (unsigned long)(val); \ 540 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 541 : : "rK" (__v) \ 542 : "memory"); \ 543 }) 544 545 #define csr_read_clear(csr, val) \ 546 ({ \ 547 unsigned long __v = (unsigned long)(val); \ 548 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 549 : "=r" (__v) : "rK" (__v) \ 550 : "memory"); \ 551 __v; \ 552 }) 553 554 #define csr_clear(csr, val) \ 555 ({ \ 556 unsigned long __v = (unsigned long)(val); \ 557 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 558 : : "rK" (__v) \ 559 : "memory"); \ 560 }) 561 562 #endif /* __ASSEMBLY__ */ 563 564 #endif /* _ASM_RISCV_CSR_H */ 565