1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CACHEFLUSH_H 7 #define _ASM_RISCV_CACHEFLUSH_H 8 9 #include <linux/mm.h> 10 11 static inline void local_flush_icache_all(void) 12 { 13 asm volatile ("fence.i" ::: "memory"); 14 } 15 16 static inline void local_flush_icache_range(unsigned long start, 17 unsigned long end) 18 { 19 local_flush_icache_all(); 20 } 21 22 #define PG_dcache_clean PG_arch_1 23 24 static inline void flush_dcache_folio(struct folio *folio) 25 { 26 if (test_bit(PG_dcache_clean, &folio->flags.f)) 27 clear_bit(PG_dcache_clean, &folio->flags.f); 28 } 29 #define flush_dcache_folio flush_dcache_folio 30 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 31 32 static inline void flush_dcache_page(struct page *page) 33 { 34 flush_dcache_folio(page_folio(page)); 35 } 36 37 #define flush_icache_user_page(vma, pg, addr, len) \ 38 do { \ 39 if (vma->vm_flags & VM_EXEC) \ 40 flush_icache_mm(vma->vm_mm, 0); \ 41 } while (0) 42 43 #ifdef CONFIG_64BIT 44 /* This is accessed in assembly code. cpumask_var_t would be too complex. */ 45 extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); 46 extern char _end[]; 47 static inline void mark_new_valid_map(void) 48 { 49 /* 50 * We don't care if concurrently a cpu resets this value since 51 * the only place this can happen is in handle_exception() where 52 * an sfence.vma is emitted. 53 */ 54 bitmap_fill(new_valid_map_cpus, NR_CPUS); 55 } 56 #define flush_cache_vmap flush_cache_vmap 57 static inline void flush_cache_vmap(unsigned long start, unsigned long end) 58 { 59 if (is_vmalloc_or_module_addr((void *)start)) 60 mark_new_valid_map(); 61 } 62 #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) 63 #endif 64 65 #ifndef CONFIG_SMP 66 67 #define flush_icache_all() local_flush_icache_all() 68 #define flush_icache_mm(mm, local) flush_icache_all() 69 70 #else /* CONFIG_SMP */ 71 72 void flush_icache_all(void); 73 void flush_icache_mm(struct mm_struct *mm, bool local); 74 75 #endif /* CONFIG_SMP */ 76 77 /* 78 * RISC-V doesn't have an instruction to flush parts of the instruction cache, 79 * so instead we just flush the whole thing. 80 */ 81 #define flush_icache_range flush_icache_range 82 static inline void flush_icache_range(unsigned long start, unsigned long end) 83 { 84 flush_icache_all(); 85 } 86 87 extern unsigned int riscv_cbom_block_size; 88 extern unsigned int riscv_cboz_block_size; 89 extern unsigned int riscv_cbop_block_size; 90 void riscv_init_cbo_blocksizes(void); 91 92 #ifdef CONFIG_RISCV_DMA_NONCOHERENT 93 void riscv_noncoherent_supported(void); 94 void __init riscv_set_dma_cache_alignment(void); 95 #else 96 static inline void riscv_noncoherent_supported(void) {} 97 static inline void riscv_set_dma_cache_alignment(void) {} 98 #endif 99 100 /* 101 * Bits in sys_riscv_flush_icache()'s flags argument. 102 */ 103 #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL 104 #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL) 105 106 #include <asm-generic/cacheflush.h> 107 108 #endif /* _ASM_RISCV_CACHEFLUSH_H */ 109