1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6 #ifndef _ASM_RISCV_CACHEFLUSH_H 7 #define _ASM_RISCV_CACHEFLUSH_H 8 9 #include <linux/mm.h> 10 11 static inline void local_flush_icache_all(void) 12 { 13 asm volatile ("fence.i" ::: "memory"); 14 } 15 16 static inline void local_flush_icache_range(unsigned long start, 17 unsigned long end) 18 { 19 local_flush_icache_all(); 20 } 21 22 #define PG_dcache_clean PG_arch_1 23 24 static inline void flush_dcache_folio(struct folio *folio) 25 { 26 if (test_bit(PG_dcache_clean, &folio->flags)) 27 clear_bit(PG_dcache_clean, &folio->flags); 28 } 29 #define flush_dcache_folio flush_dcache_folio 30 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 31 32 static inline void flush_dcache_page(struct page *page) 33 { 34 flush_dcache_folio(page_folio(page)); 35 } 36 37 /* 38 * RISC-V doesn't have an instruction to flush parts of the instruction cache, 39 * so instead we just flush the whole thing. 40 */ 41 #define flush_icache_range(start, end) flush_icache_all() 42 #define flush_icache_user_page(vma, pg, addr, len) \ 43 do { \ 44 if (vma->vm_flags & VM_EXEC) \ 45 flush_icache_mm(vma->vm_mm, 0); \ 46 } while (0) 47 48 #ifdef CONFIG_64BIT 49 #define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) 50 #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) 51 #endif 52 53 #ifndef CONFIG_SMP 54 55 #define flush_icache_all() local_flush_icache_all() 56 #define flush_icache_mm(mm, local) flush_icache_all() 57 58 #else /* CONFIG_SMP */ 59 60 void flush_icache_all(void); 61 void flush_icache_mm(struct mm_struct *mm, bool local); 62 63 #endif /* CONFIG_SMP */ 64 65 extern unsigned int riscv_cbom_block_size; 66 extern unsigned int riscv_cboz_block_size; 67 void riscv_init_cbo_blocksizes(void); 68 69 #ifdef CONFIG_RISCV_DMA_NONCOHERENT 70 void riscv_noncoherent_supported(void); 71 void __init riscv_set_dma_cache_alignment(void); 72 #else 73 static inline void riscv_noncoherent_supported(void) {} 74 static inline void riscv_set_dma_cache_alignment(void) {} 75 #endif 76 77 /* 78 * Bits in sys_riscv_flush_icache()'s flags argument. 79 */ 80 #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL 81 #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL) 82 83 #include <asm-generic/cacheflush.h> 84 85 #endif /* _ASM_RISCV_CACHEFLUSH_H */ 86