1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013-2014, Linaro Ltd. 4 * Author: Al Stone <al.stone@linaro.org> 5 * Author: Graeme Gregory <graeme.gregory@linaro.org> 6 * Author: Hanjun Guo <hanjun.guo@linaro.org> 7 * 8 * Copyright (C) 2021-2023, Ventana Micro Systems Inc. 9 * Author: Sunil V L <sunilvl@ventanamicro.com> 10 */ 11 12 #ifndef _ASM_ACPI_H 13 #define _ASM_ACPI_H 14 15 #include <linux/cpuidle.h> 16 17 /* Basic configuration for ACPI */ 18 #ifdef CONFIG_ACPI 19 20 typedef u64 phys_cpuid_t; 21 #define PHYS_CPUID_INVALID INVALID_HARTID 22 23 /* ACPI table mapping after acpi_permanent_mmap is set */ 24 void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); 25 #define acpi_os_ioremap acpi_os_ioremap 26 27 #define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ 28 extern int acpi_disabled; 29 extern int acpi_noirq; 30 extern int acpi_pci_disabled; 31 32 static inline void disable_acpi(void) 33 { 34 acpi_disabled = 1; 35 acpi_pci_disabled = 1; 36 acpi_noirq = 1; 37 } 38 39 static inline void enable_acpi(void) 40 { 41 acpi_disabled = 0; 42 acpi_pci_disabled = 0; 43 acpi_noirq = 0; 44 } 45 46 /* 47 * The ACPI processor driver for ACPI core code needs this macro 48 * to find out whether this cpu was already mapped (mapping from CPU hardware 49 * ID to CPU logical ID) or not. 50 */ 51 #define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu) 52 53 /* 54 * Since MADT must provide at least one RINTC structure, the 55 * CPU will be always available in MADT on RISC-V. 56 */ 57 static inline bool acpi_has_cpu_in_madt(void) 58 { 59 return true; 60 } 61 62 static inline void arch_fix_phys_package_id(int num, u32 slot) { } 63 64 void acpi_init_rintc_map(void); 65 struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); 66 67 int acpi_get_riscv_isa(struct acpi_table_header *table, 68 unsigned int cpu, const char **isa); 69 70 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size, 71 u32 *cboz_size, u32 *cbop_size); 72 acpi_handle acpi_get_riscv_gsi_handle(u32 gsi); 73 74 /* 75 * RISC-V Functional Fixed Hardware Specification Version v1.0.1, 76 * Chapter 3.1.2, Table 4: Arch. Context Lost Flags 77 */ 78 #define RISCV_LPI_HART_TIMER_CTXT_LOST BIT(0) 79 80 static inline unsigned int arch_get_idle_state_flags(u32 arch_flags) 81 { 82 if (arch_flags & RISCV_LPI_HART_TIMER_CTXT_LOST) 83 return CPUIDLE_FLAG_TIMER_STOP; 84 85 return 0; 86 } 87 88 #define arch_get_idle_state_flags arch_get_idle_state_flags 89 90 #else 91 static inline void acpi_init_rintc_map(void) { } 92 static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) 93 { 94 return NULL; 95 } 96 97 static inline int acpi_get_riscv_isa(struct acpi_table_header *table, 98 unsigned int cpu, const char **isa) 99 { 100 return -EINVAL; 101 } 102 103 static inline void acpi_get_cbo_block_size(struct acpi_table_header *table, 104 u32 *cbom_size, u32 *cboz_size, 105 u32 *cbop_size) { } 106 107 #endif /* CONFIG_ACPI */ 108 109 #ifdef CONFIG_ACPI_NUMA 110 void acpi_map_cpus_to_nodes(void); 111 #else 112 static inline void acpi_map_cpus_to_nodes(void) { } 113 #endif /* CONFIG_ACPI_NUMA */ 114 115 #define ACPI_TABLE_UPGRADE_MAX_PHYS MEMBLOCK_ALLOC_ACCESSIBLE 116 117 #endif /*_ASM_ACPI_H*/ 118