1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9 10/ { 11 compatible = "thead,th1520"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus: cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <3000000>; 19 20 c910_0: cpu@0 { 21 compatible = "thead,c910", "riscv"; 22 device_type = "cpu"; 23 riscv,isa = "rv64imafdc"; 24 riscv,isa-base = "rv64i"; 25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 26 "zifencei", "zihpm"; 27 reg = <0>; 28 i-cache-block-size = <64>; 29 i-cache-size = <65536>; 30 i-cache-sets = <512>; 31 d-cache-block-size = <64>; 32 d-cache-size = <65536>; 33 d-cache-sets = <512>; 34 next-level-cache = <&l2_cache>; 35 mmu-type = "riscv,sv39"; 36 37 cpu0_intc: interrupt-controller { 38 compatible = "riscv,cpu-intc"; 39 interrupt-controller; 40 #interrupt-cells = <1>; 41 }; 42 }; 43 44 c910_1: cpu@1 { 45 compatible = "thead,c910", "riscv"; 46 device_type = "cpu"; 47 riscv,isa = "rv64imafdc"; 48 riscv,isa-base = "rv64i"; 49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 50 "zifencei", "zihpm"; 51 reg = <1>; 52 i-cache-block-size = <64>; 53 i-cache-size = <65536>; 54 i-cache-sets = <512>; 55 d-cache-block-size = <64>; 56 d-cache-size = <65536>; 57 d-cache-sets = <512>; 58 next-level-cache = <&l2_cache>; 59 mmu-type = "riscv,sv39"; 60 61 cpu1_intc: interrupt-controller { 62 compatible = "riscv,cpu-intc"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 }; 66 }; 67 68 c910_2: cpu@2 { 69 compatible = "thead,c910", "riscv"; 70 device_type = "cpu"; 71 riscv,isa = "rv64imafdc"; 72 riscv,isa-base = "rv64i"; 73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 74 "zifencei", "zihpm"; 75 reg = <2>; 76 i-cache-block-size = <64>; 77 i-cache-size = <65536>; 78 i-cache-sets = <512>; 79 d-cache-block-size = <64>; 80 d-cache-size = <65536>; 81 d-cache-sets = <512>; 82 next-level-cache = <&l2_cache>; 83 mmu-type = "riscv,sv39"; 84 85 cpu2_intc: interrupt-controller { 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 #interrupt-cells = <1>; 89 }; 90 }; 91 92 c910_3: cpu@3 { 93 compatible = "thead,c910", "riscv"; 94 device_type = "cpu"; 95 riscv,isa = "rv64imafdc"; 96 riscv,isa-base = "rv64i"; 97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 98 "zifencei", "zihpm"; 99 reg = <3>; 100 i-cache-block-size = <64>; 101 i-cache-size = <65536>; 102 i-cache-sets = <512>; 103 d-cache-block-size = <64>; 104 d-cache-size = <65536>; 105 d-cache-sets = <512>; 106 next-level-cache = <&l2_cache>; 107 mmu-type = "riscv,sv39"; 108 109 cpu3_intc: interrupt-controller { 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 }; 114 }; 115 116 l2_cache: l2-cache { 117 compatible = "cache"; 118 cache-block-size = <64>; 119 cache-level = <2>; 120 cache-size = <1048576>; 121 cache-sets = <1024>; 122 cache-unified; 123 }; 124 }; 125 126 pmu { 127 compatible = "riscv,pmu"; 128 riscv,event-to-mhpmcounters = 129 <0x00003 0x00003 0x0007fff8>, 130 <0x00004 0x00004 0x0007fff8>, 131 <0x00005 0x00005 0x0007fff8>, 132 <0x00006 0x00006 0x0007fff8>, 133 <0x00007 0x00007 0x0007fff8>, 134 <0x00008 0x00008 0x0007fff8>, 135 <0x00009 0x00009 0x0007fff8>, 136 <0x0000a 0x0000a 0x0007fff8>, 137 <0x10000 0x10000 0x0007fff8>, 138 <0x10001 0x10001 0x0007fff8>, 139 <0x10002 0x10002 0x0007fff8>, 140 <0x10003 0x10003 0x0007fff8>, 141 <0x10010 0x10010 0x0007fff8>, 142 <0x10011 0x10011 0x0007fff8>, 143 <0x10012 0x10012 0x0007fff8>, 144 <0x10013 0x10013 0x0007fff8>; 145 riscv,event-to-mhpmevent = 146 <0x00003 0x00000000 0x00000001>, 147 <0x00004 0x00000000 0x00000002>, 148 <0x00006 0x00000000 0x00000006>, 149 <0x00005 0x00000000 0x00000007>, 150 <0x00007 0x00000000 0x00000008>, 151 <0x00008 0x00000000 0x00000009>, 152 <0x00009 0x00000000 0x0000000a>, 153 <0x0000a 0x00000000 0x0000000b>, 154 <0x10000 0x00000000 0x0000000c>, 155 <0x10001 0x00000000 0x0000000d>, 156 <0x10002 0x00000000 0x0000000e>, 157 <0x10003 0x00000000 0x0000000f>, 158 <0x10010 0x00000000 0x00000010>, 159 <0x10011 0x00000000 0x00000011>, 160 <0x10012 0x00000000 0x00000012>, 161 <0x10013 0x00000000 0x00000013>; 162 riscv,raw-event-to-mhpmcounters = 163 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 164 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 165 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 205 }; 206 207 osc: oscillator { 208 compatible = "fixed-clock"; 209 clock-output-names = "osc_24m"; 210 #clock-cells = <0>; 211 }; 212 213 osc_32k: 32k-oscillator { 214 compatible = "fixed-clock"; 215 clock-output-names = "osc_32k"; 216 #clock-cells = <0>; 217 }; 218 219 aonsys_clk: clock-73728000 { 220 compatible = "fixed-clock"; 221 clock-frequency = <73728000>; 222 clock-output-names = "aonsys_clk"; 223 #clock-cells = <0>; 224 }; 225 226 soc { 227 compatible = "simple-bus"; 228 interrupt-parent = <&plic>; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 dma-noncoherent; 232 ranges; 233 234 plic: interrupt-controller@ffd8000000 { 235 compatible = "thead,th1520-plic", "thead,c900-plic"; 236 reg = <0xff 0xd8000000 0x0 0x01000000>; 237 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 238 <&cpu1_intc 11>, <&cpu1_intc 9>, 239 <&cpu2_intc 11>, <&cpu2_intc 9>, 240 <&cpu3_intc 11>, <&cpu3_intc 9>; 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <2>; 244 riscv,ndev = <240>; 245 }; 246 247 clint: timer@ffdc000000 { 248 compatible = "thead,th1520-clint", "thead,c900-clint"; 249 reg = <0xff 0xdc000000 0x0 0x00010000>; 250 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 251 <&cpu1_intc 3>, <&cpu1_intc 7>, 252 <&cpu2_intc 3>, <&cpu2_intc 7>, 253 <&cpu3_intc 3>, <&cpu3_intc 7>; 254 }; 255 256 spi0: spi@ffe700c000 { 257 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 258 reg = <0xff 0xe700c000 0x0 0x1000>; 259 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clk CLK_SPI>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 status = "disabled"; 264 }; 265 266 uart0: serial@ffe7014000 { 267 compatible = "snps,dw-apb-uart"; 268 reg = <0xff 0xe7014000 0x0 0x100>; 269 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 271 clock-names = "baudclk", "apb_pclk"; 272 reg-shift = <2>; 273 reg-io-width = <4>; 274 status = "disabled"; 275 }; 276 277 emmc: mmc@ffe7080000 { 278 compatible = "thead,th1520-dwcmshc"; 279 reg = <0xff 0xe7080000 0x0 0x10000>; 280 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk CLK_EMMC_SDIO>; 282 clock-names = "core"; 283 status = "disabled"; 284 }; 285 286 sdio0: mmc@ffe7090000 { 287 compatible = "thead,th1520-dwcmshc"; 288 reg = <0xff 0xe7090000 0x0 0x10000>; 289 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clk CLK_EMMC_SDIO>; 291 clock-names = "core"; 292 status = "disabled"; 293 }; 294 295 sdio1: mmc@ffe70a0000 { 296 compatible = "thead,th1520-dwcmshc"; 297 reg = <0xff 0xe70a0000 0x0 0x10000>; 298 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clk CLK_EMMC_SDIO>; 300 clock-names = "core"; 301 status = "disabled"; 302 }; 303 304 uart1: serial@ffe7f00000 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0xff 0xe7f00000 0x0 0x100>; 307 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 309 clock-names = "baudclk", "apb_pclk"; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 status = "disabled"; 313 }; 314 315 uart3: serial@ffe7f04000 { 316 compatible = "snps,dw-apb-uart"; 317 reg = <0xff 0xe7f04000 0x0 0x100>; 318 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 320 clock-names = "baudclk", "apb_pclk"; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 status = "disabled"; 324 }; 325 326 gpio@ffe7f34000 { 327 compatible = "snps,dw-apb-gpio"; 328 reg = <0xff 0xe7f34000 0x0 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clocks = <&clk CLK_GPIO2>; 332 clock-names = "bus"; 333 334 gpio2: gpio-controller@0 { 335 compatible = "snps,dw-apb-gpio-port"; 336 gpio-controller; 337 #gpio-cells = <2>; 338 ngpios = <32>; 339 gpio-ranges = <&padctrl0_apsys 0 0 32>; 340 reg = <0>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 }; 346 347 gpio@ffe7f38000 { 348 compatible = "snps,dw-apb-gpio"; 349 reg = <0xff 0xe7f38000 0x0 0x1000>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clocks = <&clk CLK_GPIO3>; 353 clock-names = "bus"; 354 355 gpio3: gpio-controller@0 { 356 compatible = "snps,dw-apb-gpio-port"; 357 gpio-controller; 358 #gpio-cells = <2>; 359 ngpios = <23>; 360 gpio-ranges = <&padctrl0_apsys 0 32 23>; 361 reg = <0>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 365 }; 366 }; 367 368 padctrl1_apsys: pinctrl@ffe7f3c000 { 369 compatible = "thead,th1520-pinctrl"; 370 reg = <0xff 0xe7f3c000 0x0 0x1000>; 371 clocks = <&clk CLK_PADCTRL1>; 372 thead,pad-group = <2>; 373 }; 374 375 gpio@ffec005000 { 376 compatible = "snps,dw-apb-gpio"; 377 reg = <0xff 0xec005000 0x0 0x1000>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 clocks = <&clk CLK_GPIO0>; 381 clock-names = "bus"; 382 383 gpio0: gpio-controller@0 { 384 compatible = "snps,dw-apb-gpio-port"; 385 gpio-controller; 386 #gpio-cells = <2>; 387 ngpios = <32>; 388 gpio-ranges = <&padctrl1_apsys 0 0 32>; 389 reg = <0>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 }; 395 396 gpio@ffec006000 { 397 compatible = "snps,dw-apb-gpio"; 398 reg = <0xff 0xec006000 0x0 0x1000>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 clocks = <&clk CLK_GPIO1>; 402 clock-names = "bus"; 403 404 gpio1: gpio-controller@0 { 405 compatible = "snps,dw-apb-gpio-port"; 406 gpio-controller; 407 #gpio-cells = <2>; 408 ngpios = <31>; 409 gpio-ranges = <&padctrl1_apsys 0 32 31>; 410 reg = <0>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 414 }; 415 }; 416 417 padctrl0_apsys: pinctrl@ffec007000 { 418 compatible = "thead,th1520-pinctrl"; 419 reg = <0xff 0xec007000 0x0 0x1000>; 420 clocks = <&clk CLK_PADCTRL0>; 421 thead,pad-group = <3>; 422 }; 423 424 uart2: serial@ffec010000 { 425 compatible = "snps,dw-apb-uart"; 426 reg = <0xff 0xec010000 0x0 0x4000>; 427 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 429 clock-names = "baudclk", "apb_pclk"; 430 reg-shift = <2>; 431 reg-io-width = <4>; 432 status = "disabled"; 433 }; 434 435 clk: clock-controller@ffef010000 { 436 compatible = "thead,th1520-clk-ap"; 437 reg = <0xff 0xef010000 0x0 0x1000>; 438 clocks = <&osc>; 439 #clock-cells = <1>; 440 }; 441 442 dmac0: dma-controller@ffefc00000 { 443 compatible = "snps,axi-dma-1.01a"; 444 reg = <0xff 0xefc00000 0x0 0x1000>; 445 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 447 clock-names = "core-clk", "cfgr-clk"; 448 #dma-cells = <1>; 449 dma-channels = <4>; 450 snps,block-size = <65536 65536 65536 65536>; 451 snps,priority = <0 1 2 3>; 452 snps,dma-masters = <1>; 453 snps,data-width = <4>; 454 snps,axi-max-burst-len = <16>; 455 status = "disabled"; 456 }; 457 458 timer0: timer@ffefc32000 { 459 compatible = "snps,dw-apb-timer"; 460 reg = <0xff 0xefc32000 0x0 0x14>; 461 clocks = <&clk CLK_PERI_APB_PCLK>; 462 clock-names = "timer"; 463 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 464 status = "disabled"; 465 }; 466 467 timer1: timer@ffefc32014 { 468 compatible = "snps,dw-apb-timer"; 469 reg = <0xff 0xefc32014 0x0 0x14>; 470 clocks = <&clk CLK_PERI_APB_PCLK>; 471 clock-names = "timer"; 472 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 473 status = "disabled"; 474 }; 475 476 timer2: timer@ffefc32028 { 477 compatible = "snps,dw-apb-timer"; 478 reg = <0xff 0xefc32028 0x0 0x14>; 479 clocks = <&clk CLK_PERI_APB_PCLK>; 480 clock-names = "timer"; 481 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 482 status = "disabled"; 483 }; 484 485 timer3: timer@ffefc3203c { 486 compatible = "snps,dw-apb-timer"; 487 reg = <0xff 0xefc3203c 0x0 0x14>; 488 clocks = <&clk CLK_PERI_APB_PCLK>; 489 clock-names = "timer"; 490 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 491 status = "disabled"; 492 }; 493 494 uart4: serial@fff7f08000 { 495 compatible = "snps,dw-apb-uart"; 496 reg = <0xff 0xf7f08000 0x0 0x4000>; 497 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 499 clock-names = "baudclk", "apb_pclk"; 500 reg-shift = <2>; 501 reg-io-width = <4>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@fff7f0c000 { 506 compatible = "snps,dw-apb-uart"; 507 reg = <0xff 0xf7f0c000 0x0 0x4000>; 508 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 510 clock-names = "baudclk", "apb_pclk"; 511 reg-shift = <2>; 512 reg-io-width = <4>; 513 status = "disabled"; 514 }; 515 516 timer4: timer@ffffc33000 { 517 compatible = "snps,dw-apb-timer"; 518 reg = <0xff 0xffc33000 0x0 0x14>; 519 clocks = <&clk CLK_PERI_APB_PCLK>; 520 clock-names = "timer"; 521 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 522 status = "disabled"; 523 }; 524 525 timer5: timer@ffffc33014 { 526 compatible = "snps,dw-apb-timer"; 527 reg = <0xff 0xffc33014 0x0 0x14>; 528 clocks = <&clk CLK_PERI_APB_PCLK>; 529 clock-names = "timer"; 530 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 531 status = "disabled"; 532 }; 533 534 timer6: timer@ffffc33028 { 535 compatible = "snps,dw-apb-timer"; 536 reg = <0xff 0xffc33028 0x0 0x14>; 537 clocks = <&clk CLK_PERI_APB_PCLK>; 538 clock-names = "timer"; 539 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 540 status = "disabled"; 541 }; 542 543 timer7: timer@ffffc3303c { 544 compatible = "snps,dw-apb-timer"; 545 reg = <0xff 0xffc3303c 0x0 0x14>; 546 clocks = <&clk CLK_PERI_APB_PCLK>; 547 clock-names = "timer"; 548 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 549 status = "disabled"; 550 }; 551 552 gpio@fffff41000 { 553 compatible = "snps,dw-apb-gpio"; 554 reg = <0xff 0xfff41000 0x0 0x1000>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 558 aogpio: gpio-controller@0 { 559 compatible = "snps,dw-apb-gpio-port"; 560 gpio-controller; 561 #gpio-cells = <2>; 562 ngpios = <16>; 563 gpio-ranges = <&padctrl_aosys 0 9 16>; 564 reg = <0>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 }; 570 571 padctrl_aosys: pinctrl@fffff4a000 { 572 compatible = "thead,th1520-pinctrl"; 573 reg = <0xff 0xfff4a000 0x0 0x2000>; 574 clocks = <&aonsys_clk>; 575 thead,pad-group = <1>; 576 }; 577 578 gpio@fffff52000 { 579 compatible = "snps,dw-apb-gpio"; 580 reg = <0xff 0xfff52000 0x0 0x1000>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 gpio4: gpio-controller@0 { 585 compatible = "snps,dw-apb-gpio-port"; 586 gpio-controller; 587 #gpio-cells = <2>; 588 ngpios = <23>; 589 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 590 reg = <0>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 594 }; 595 }; 596 }; 597}; 598