1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9 10/ { 11 compatible = "thead,th1520"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus: cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <3000000>; 19 20 c910_0: cpu@0 { 21 compatible = "thead,c910", "riscv"; 22 device_type = "cpu"; 23 riscv,isa = "rv64imafdc"; 24 riscv,isa-base = "rv64i"; 25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 26 "zifencei", "zihpm"; 27 reg = <0>; 28 i-cache-block-size = <64>; 29 i-cache-size = <65536>; 30 i-cache-sets = <512>; 31 d-cache-block-size = <64>; 32 d-cache-size = <65536>; 33 d-cache-sets = <512>; 34 next-level-cache = <&l2_cache>; 35 mmu-type = "riscv,sv39"; 36 37 cpu0_intc: interrupt-controller { 38 compatible = "riscv,cpu-intc"; 39 interrupt-controller; 40 #interrupt-cells = <1>; 41 }; 42 }; 43 44 c910_1: cpu@1 { 45 compatible = "thead,c910", "riscv"; 46 device_type = "cpu"; 47 riscv,isa = "rv64imafdc"; 48 riscv,isa-base = "rv64i"; 49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 50 "zifencei", "zihpm"; 51 reg = <1>; 52 i-cache-block-size = <64>; 53 i-cache-size = <65536>; 54 i-cache-sets = <512>; 55 d-cache-block-size = <64>; 56 d-cache-size = <65536>; 57 d-cache-sets = <512>; 58 next-level-cache = <&l2_cache>; 59 mmu-type = "riscv,sv39"; 60 61 cpu1_intc: interrupt-controller { 62 compatible = "riscv,cpu-intc"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 }; 66 }; 67 68 c910_2: cpu@2 { 69 compatible = "thead,c910", "riscv"; 70 device_type = "cpu"; 71 riscv,isa = "rv64imafdc"; 72 riscv,isa-base = "rv64i"; 73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 74 "zifencei", "zihpm"; 75 reg = <2>; 76 i-cache-block-size = <64>; 77 i-cache-size = <65536>; 78 i-cache-sets = <512>; 79 d-cache-block-size = <64>; 80 d-cache-size = <65536>; 81 d-cache-sets = <512>; 82 next-level-cache = <&l2_cache>; 83 mmu-type = "riscv,sv39"; 84 85 cpu2_intc: interrupt-controller { 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 #interrupt-cells = <1>; 89 }; 90 }; 91 92 c910_3: cpu@3 { 93 compatible = "thead,c910", "riscv"; 94 device_type = "cpu"; 95 riscv,isa = "rv64imafdc"; 96 riscv,isa-base = "rv64i"; 97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 98 "zifencei", "zihpm"; 99 reg = <3>; 100 i-cache-block-size = <64>; 101 i-cache-size = <65536>; 102 i-cache-sets = <512>; 103 d-cache-block-size = <64>; 104 d-cache-size = <65536>; 105 d-cache-sets = <512>; 106 next-level-cache = <&l2_cache>; 107 mmu-type = "riscv,sv39"; 108 109 cpu3_intc: interrupt-controller { 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 }; 114 }; 115 116 l2_cache: l2-cache { 117 compatible = "cache"; 118 cache-block-size = <64>; 119 cache-level = <2>; 120 cache-size = <1048576>; 121 cache-sets = <1024>; 122 cache-unified; 123 }; 124 }; 125 126 pmu { 127 compatible = "riscv,pmu"; 128 riscv,event-to-mhpmcounters = 129 <0x00003 0x00003 0x0007fff8>, 130 <0x00004 0x00004 0x0007fff8>, 131 <0x00005 0x00005 0x0007fff8>, 132 <0x00006 0x00006 0x0007fff8>, 133 <0x00007 0x00007 0x0007fff8>, 134 <0x00008 0x00008 0x0007fff8>, 135 <0x00009 0x00009 0x0007fff8>, 136 <0x0000a 0x0000a 0x0007fff8>, 137 <0x10000 0x10000 0x0007fff8>, 138 <0x10001 0x10001 0x0007fff8>, 139 <0x10002 0x10002 0x0007fff8>, 140 <0x10003 0x10003 0x0007fff8>, 141 <0x10010 0x10010 0x0007fff8>, 142 <0x10011 0x10011 0x0007fff8>, 143 <0x10012 0x10012 0x0007fff8>, 144 <0x10013 0x10013 0x0007fff8>; 145 riscv,event-to-mhpmevent = 146 <0x00003 0x00000000 0x00000001>, 147 <0x00004 0x00000000 0x00000002>, 148 <0x00006 0x00000000 0x00000006>, 149 <0x00005 0x00000000 0x00000007>, 150 <0x00007 0x00000000 0x00000008>, 151 <0x00008 0x00000000 0x00000009>, 152 <0x00009 0x00000000 0x0000000a>, 153 <0x0000a 0x00000000 0x0000000b>, 154 <0x10000 0x00000000 0x0000000c>, 155 <0x10001 0x00000000 0x0000000d>, 156 <0x10002 0x00000000 0x0000000e>, 157 <0x10003 0x00000000 0x0000000f>, 158 <0x10010 0x00000000 0x00000010>, 159 <0x10011 0x00000000 0x00000011>, 160 <0x10012 0x00000000 0x00000012>, 161 <0x10013 0x00000000 0x00000013>; 162 riscv,raw-event-to-mhpmcounters = 163 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 164 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 165 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 205 }; 206 207 osc: oscillator { 208 compatible = "fixed-clock"; 209 clock-output-names = "osc_24m"; 210 #clock-cells = <0>; 211 }; 212 213 osc_32k: 32k-oscillator { 214 compatible = "fixed-clock"; 215 clock-output-names = "osc_32k"; 216 #clock-cells = <0>; 217 }; 218 219 aonsys_clk: clock-73728000 { 220 compatible = "fixed-clock"; 221 clock-frequency = <73728000>; 222 clock-output-names = "aonsys_clk"; 223 #clock-cells = <0>; 224 }; 225 226 stmmac_axi_config: stmmac-axi-config { 227 snps,wr_osr_lmt = <15>; 228 snps,rd_osr_lmt = <15>; 229 snps,blen = <0 0 64 32 0 0 0>; 230 }; 231 232 soc { 233 compatible = "simple-bus"; 234 interrupt-parent = <&plic>; 235 #address-cells = <2>; 236 #size-cells = <2>; 237 dma-noncoherent; 238 ranges; 239 240 plic: interrupt-controller@ffd8000000 { 241 compatible = "thead,th1520-plic", "thead,c900-plic"; 242 reg = <0xff 0xd8000000 0x0 0x01000000>; 243 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 244 <&cpu1_intc 11>, <&cpu1_intc 9>, 245 <&cpu2_intc 11>, <&cpu2_intc 9>, 246 <&cpu3_intc 11>, <&cpu3_intc 9>; 247 interrupt-controller; 248 #address-cells = <0>; 249 #interrupt-cells = <2>; 250 riscv,ndev = <240>; 251 }; 252 253 clint: timer@ffdc000000 { 254 compatible = "thead,th1520-clint", "thead,c900-clint"; 255 reg = <0xff 0xdc000000 0x0 0x00010000>; 256 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 257 <&cpu1_intc 3>, <&cpu1_intc 7>, 258 <&cpu2_intc 3>, <&cpu2_intc 7>, 259 <&cpu3_intc 3>, <&cpu3_intc 7>; 260 }; 261 262 spi0: spi@ffe700c000 { 263 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 264 reg = <0xff 0xe700c000 0x0 0x1000>; 265 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&clk CLK_SPI>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 status = "disabled"; 270 }; 271 272 uart0: serial@ffe7014000 { 273 compatible = "snps,dw-apb-uart"; 274 reg = <0xff 0xe7014000 0x0 0x100>; 275 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 277 clock-names = "baudclk", "apb_pclk"; 278 reg-shift = <2>; 279 reg-io-width = <4>; 280 status = "disabled"; 281 }; 282 283 gmac1: ethernet@ffe7060000 { 284 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 285 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 286 reg-names = "dwmac", "apb"; 287 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-names = "macirq"; 289 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; 290 clock-names = "stmmaceth", "pclk"; 291 snps,pbl = <32>; 292 snps,fixed-burst; 293 snps,multicast-filter-bins = <64>; 294 snps,perfect-filter-entries = <32>; 295 snps,axi-config = <&stmmac_axi_config>; 296 status = "disabled"; 297 298 mdio1: mdio { 299 compatible = "snps,dwmac-mdio"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 }; 303 }; 304 305 gmac0: ethernet@ffe7070000 { 306 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 307 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 308 reg-names = "dwmac", "apb"; 309 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "macirq"; 311 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; 312 clock-names = "stmmaceth", "pclk"; 313 snps,pbl = <32>; 314 snps,fixed-burst; 315 snps,multicast-filter-bins = <64>; 316 snps,perfect-filter-entries = <32>; 317 snps,axi-config = <&stmmac_axi_config>; 318 status = "disabled"; 319 320 mdio0: mdio { 321 compatible = "snps,dwmac-mdio"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 }; 325 }; 326 327 emmc: mmc@ffe7080000 { 328 compatible = "thead,th1520-dwcmshc"; 329 reg = <0xff 0xe7080000 0x0 0x10000>; 330 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk CLK_EMMC_SDIO>; 332 clock-names = "core"; 333 status = "disabled"; 334 }; 335 336 sdio0: mmc@ffe7090000 { 337 compatible = "thead,th1520-dwcmshc"; 338 reg = <0xff 0xe7090000 0x0 0x10000>; 339 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clk CLK_EMMC_SDIO>; 341 clock-names = "core"; 342 status = "disabled"; 343 }; 344 345 sdio1: mmc@ffe70a0000 { 346 compatible = "thead,th1520-dwcmshc"; 347 reg = <0xff 0xe70a0000 0x0 0x10000>; 348 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clk CLK_EMMC_SDIO>; 350 clock-names = "core"; 351 status = "disabled"; 352 }; 353 354 uart1: serial@ffe7f00000 { 355 compatible = "snps,dw-apb-uart"; 356 reg = <0xff 0xe7f00000 0x0 0x100>; 357 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 359 clock-names = "baudclk", "apb_pclk"; 360 reg-shift = <2>; 361 reg-io-width = <4>; 362 status = "disabled"; 363 }; 364 365 uart3: serial@ffe7f04000 { 366 compatible = "snps,dw-apb-uart"; 367 reg = <0xff 0xe7f04000 0x0 0x100>; 368 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 370 clock-names = "baudclk", "apb_pclk"; 371 reg-shift = <2>; 372 reg-io-width = <4>; 373 status = "disabled"; 374 }; 375 376 gpio@ffe7f34000 { 377 compatible = "snps,dw-apb-gpio"; 378 reg = <0xff 0xe7f34000 0x0 0x1000>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&clk CLK_GPIO2>; 382 clock-names = "bus"; 383 384 gpio2: gpio-controller@0 { 385 compatible = "snps,dw-apb-gpio-port"; 386 gpio-controller; 387 #gpio-cells = <2>; 388 ngpios = <32>; 389 gpio-ranges = <&padctrl0_apsys 0 0 32>; 390 reg = <0>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 394 }; 395 }; 396 397 gpio@ffe7f38000 { 398 compatible = "snps,dw-apb-gpio"; 399 reg = <0xff 0xe7f38000 0x0 0x1000>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clocks = <&clk CLK_GPIO3>; 403 clock-names = "bus"; 404 405 gpio3: gpio-controller@0 { 406 compatible = "snps,dw-apb-gpio-port"; 407 gpio-controller; 408 #gpio-cells = <2>; 409 ngpios = <23>; 410 gpio-ranges = <&padctrl0_apsys 0 32 23>; 411 reg = <0>; 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 415 }; 416 }; 417 418 padctrl1_apsys: pinctrl@ffe7f3c000 { 419 compatible = "thead,th1520-pinctrl"; 420 reg = <0xff 0xe7f3c000 0x0 0x1000>; 421 clocks = <&clk CLK_PADCTRL1>; 422 thead,pad-group = <2>; 423 }; 424 425 gpio@ffec005000 { 426 compatible = "snps,dw-apb-gpio"; 427 reg = <0xff 0xec005000 0x0 0x1000>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&clk CLK_GPIO0>; 431 clock-names = "bus"; 432 433 gpio0: gpio-controller@0 { 434 compatible = "snps,dw-apb-gpio-port"; 435 gpio-controller; 436 #gpio-cells = <2>; 437 ngpios = <32>; 438 gpio-ranges = <&padctrl1_apsys 0 0 32>; 439 reg = <0>; 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 443 }; 444 }; 445 446 gpio@ffec006000 { 447 compatible = "snps,dw-apb-gpio"; 448 reg = <0xff 0xec006000 0x0 0x1000>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clocks = <&clk CLK_GPIO1>; 452 clock-names = "bus"; 453 454 gpio1: gpio-controller@0 { 455 compatible = "snps,dw-apb-gpio-port"; 456 gpio-controller; 457 #gpio-cells = <2>; 458 ngpios = <31>; 459 gpio-ranges = <&padctrl1_apsys 0 32 31>; 460 reg = <0>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 464 }; 465 }; 466 467 padctrl0_apsys: pinctrl@ffec007000 { 468 compatible = "thead,th1520-pinctrl"; 469 reg = <0xff 0xec007000 0x0 0x1000>; 470 clocks = <&clk CLK_PADCTRL0>; 471 thead,pad-group = <3>; 472 }; 473 474 uart2: serial@ffec010000 { 475 compatible = "snps,dw-apb-uart"; 476 reg = <0xff 0xec010000 0x0 0x4000>; 477 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 479 clock-names = "baudclk", "apb_pclk"; 480 reg-shift = <2>; 481 reg-io-width = <4>; 482 status = "disabled"; 483 }; 484 485 clk: clock-controller@ffef010000 { 486 compatible = "thead,th1520-clk-ap"; 487 reg = <0xff 0xef010000 0x0 0x1000>; 488 clocks = <&osc>; 489 #clock-cells = <1>; 490 }; 491 492 dmac0: dma-controller@ffefc00000 { 493 compatible = "snps,axi-dma-1.01a"; 494 reg = <0xff 0xefc00000 0x0 0x1000>; 495 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 497 clock-names = "core-clk", "cfgr-clk"; 498 #dma-cells = <1>; 499 dma-channels = <4>; 500 snps,block-size = <65536 65536 65536 65536>; 501 snps,priority = <0 1 2 3>; 502 snps,dma-masters = <1>; 503 snps,data-width = <4>; 504 snps,axi-max-burst-len = <16>; 505 status = "disabled"; 506 }; 507 508 timer0: timer@ffefc32000 { 509 compatible = "snps,dw-apb-timer"; 510 reg = <0xff 0xefc32000 0x0 0x14>; 511 clocks = <&clk CLK_PERI_APB_PCLK>; 512 clock-names = "timer"; 513 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 514 status = "disabled"; 515 }; 516 517 timer1: timer@ffefc32014 { 518 compatible = "snps,dw-apb-timer"; 519 reg = <0xff 0xefc32014 0x0 0x14>; 520 clocks = <&clk CLK_PERI_APB_PCLK>; 521 clock-names = "timer"; 522 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 523 status = "disabled"; 524 }; 525 526 timer2: timer@ffefc32028 { 527 compatible = "snps,dw-apb-timer"; 528 reg = <0xff 0xefc32028 0x0 0x14>; 529 clocks = <&clk CLK_PERI_APB_PCLK>; 530 clock-names = "timer"; 531 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 532 status = "disabled"; 533 }; 534 535 timer3: timer@ffefc3203c { 536 compatible = "snps,dw-apb-timer"; 537 reg = <0xff 0xefc3203c 0x0 0x14>; 538 clocks = <&clk CLK_PERI_APB_PCLK>; 539 clock-names = "timer"; 540 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 541 status = "disabled"; 542 }; 543 544 uart4: serial@fff7f08000 { 545 compatible = "snps,dw-apb-uart"; 546 reg = <0xff 0xf7f08000 0x0 0x4000>; 547 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 549 clock-names = "baudclk", "apb_pclk"; 550 reg-shift = <2>; 551 reg-io-width = <4>; 552 status = "disabled"; 553 }; 554 555 uart5: serial@fff7f0c000 { 556 compatible = "snps,dw-apb-uart"; 557 reg = <0xff 0xf7f0c000 0x0 0x4000>; 558 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 560 clock-names = "baudclk", "apb_pclk"; 561 reg-shift = <2>; 562 reg-io-width = <4>; 563 status = "disabled"; 564 }; 565 566 timer4: timer@ffffc33000 { 567 compatible = "snps,dw-apb-timer"; 568 reg = <0xff 0xffc33000 0x0 0x14>; 569 clocks = <&clk CLK_PERI_APB_PCLK>; 570 clock-names = "timer"; 571 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 572 status = "disabled"; 573 }; 574 575 timer5: timer@ffffc33014 { 576 compatible = "snps,dw-apb-timer"; 577 reg = <0xff 0xffc33014 0x0 0x14>; 578 clocks = <&clk CLK_PERI_APB_PCLK>; 579 clock-names = "timer"; 580 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 581 status = "disabled"; 582 }; 583 584 timer6: timer@ffffc33028 { 585 compatible = "snps,dw-apb-timer"; 586 reg = <0xff 0xffc33028 0x0 0x14>; 587 clocks = <&clk CLK_PERI_APB_PCLK>; 588 clock-names = "timer"; 589 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 590 status = "disabled"; 591 }; 592 593 timer7: timer@ffffc3303c { 594 compatible = "snps,dw-apb-timer"; 595 reg = <0xff 0xffc3303c 0x0 0x14>; 596 clocks = <&clk CLK_PERI_APB_PCLK>; 597 clock-names = "timer"; 598 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 599 status = "disabled"; 600 }; 601 602 gpio@fffff41000 { 603 compatible = "snps,dw-apb-gpio"; 604 reg = <0xff 0xfff41000 0x0 0x1000>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 608 aogpio: gpio-controller@0 { 609 compatible = "snps,dw-apb-gpio-port"; 610 gpio-controller; 611 #gpio-cells = <2>; 612 ngpios = <16>; 613 gpio-ranges = <&padctrl_aosys 0 9 16>; 614 reg = <0>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 618 }; 619 }; 620 621 padctrl_aosys: pinctrl@fffff4a000 { 622 compatible = "thead,th1520-pinctrl"; 623 reg = <0xff 0xfff4a000 0x0 0x2000>; 624 clocks = <&aonsys_clk>; 625 thead,pad-group = <1>; 626 }; 627 628 gpio@fffff52000 { 629 compatible = "snps,dw-apb-gpio"; 630 reg = <0xff 0xfff52000 0x0 0x1000>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 634 gpio4: gpio-controller@0 { 635 compatible = "snps,dw-apb-gpio-port"; 636 gpio-controller; 637 #gpio-cells = <2>; 638 ngpios = <23>; 639 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 640 reg = <0>; 641 interrupt-controller; 642 #interrupt-cells = <2>; 643 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 644 }; 645 }; 646 }; 647}; 648