1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9 10/ { 11 compatible = "thead,th1520"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus: cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <3000000>; 19 20 c910_0: cpu@0 { 21 compatible = "thead,c910", "riscv"; 22 device_type = "cpu"; 23 riscv,isa = "rv64imafdc"; 24 riscv,isa-base = "rv64i"; 25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 26 "zifencei", "zihpm"; 27 reg = <0>; 28 i-cache-block-size = <64>; 29 i-cache-size = <65536>; 30 i-cache-sets = <512>; 31 d-cache-block-size = <64>; 32 d-cache-size = <65536>; 33 d-cache-sets = <512>; 34 next-level-cache = <&l2_cache>; 35 mmu-type = "riscv,sv39"; 36 37 cpu0_intc: interrupt-controller { 38 compatible = "riscv,cpu-intc"; 39 interrupt-controller; 40 #interrupt-cells = <1>; 41 }; 42 }; 43 44 c910_1: cpu@1 { 45 compatible = "thead,c910", "riscv"; 46 device_type = "cpu"; 47 riscv,isa = "rv64imafdc"; 48 riscv,isa-base = "rv64i"; 49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 50 "zifencei", "zihpm"; 51 reg = <1>; 52 i-cache-block-size = <64>; 53 i-cache-size = <65536>; 54 i-cache-sets = <512>; 55 d-cache-block-size = <64>; 56 d-cache-size = <65536>; 57 d-cache-sets = <512>; 58 next-level-cache = <&l2_cache>; 59 mmu-type = "riscv,sv39"; 60 61 cpu1_intc: interrupt-controller { 62 compatible = "riscv,cpu-intc"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 }; 66 }; 67 68 c910_2: cpu@2 { 69 compatible = "thead,c910", "riscv"; 70 device_type = "cpu"; 71 riscv,isa = "rv64imafdc"; 72 riscv,isa-base = "rv64i"; 73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 74 "zifencei", "zihpm"; 75 reg = <2>; 76 i-cache-block-size = <64>; 77 i-cache-size = <65536>; 78 i-cache-sets = <512>; 79 d-cache-block-size = <64>; 80 d-cache-size = <65536>; 81 d-cache-sets = <512>; 82 next-level-cache = <&l2_cache>; 83 mmu-type = "riscv,sv39"; 84 85 cpu2_intc: interrupt-controller { 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 #interrupt-cells = <1>; 89 }; 90 }; 91 92 c910_3: cpu@3 { 93 compatible = "thead,c910", "riscv"; 94 device_type = "cpu"; 95 riscv,isa = "rv64imafdc"; 96 riscv,isa-base = "rv64i"; 97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 98 "zifencei", "zihpm"; 99 reg = <3>; 100 i-cache-block-size = <64>; 101 i-cache-size = <65536>; 102 i-cache-sets = <512>; 103 d-cache-block-size = <64>; 104 d-cache-size = <65536>; 105 d-cache-sets = <512>; 106 next-level-cache = <&l2_cache>; 107 mmu-type = "riscv,sv39"; 108 109 cpu3_intc: interrupt-controller { 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 }; 114 }; 115 116 l2_cache: l2-cache { 117 compatible = "cache"; 118 cache-block-size = <64>; 119 cache-level = <2>; 120 cache-size = <1048576>; 121 cache-sets = <1024>; 122 cache-unified; 123 }; 124 }; 125 126 pmu { 127 compatible = "riscv,pmu"; 128 riscv,event-to-mhpmcounters = 129 <0x00003 0x00003 0x0007fff8>, 130 <0x00004 0x00004 0x0007fff8>, 131 <0x00005 0x00005 0x0007fff8>, 132 <0x00006 0x00006 0x0007fff8>, 133 <0x00007 0x00007 0x0007fff8>, 134 <0x00008 0x00008 0x0007fff8>, 135 <0x00009 0x00009 0x0007fff8>, 136 <0x0000a 0x0000a 0x0007fff8>, 137 <0x10000 0x10000 0x0007fff8>, 138 <0x10001 0x10001 0x0007fff8>, 139 <0x10002 0x10002 0x0007fff8>, 140 <0x10003 0x10003 0x0007fff8>, 141 <0x10010 0x10010 0x0007fff8>, 142 <0x10011 0x10011 0x0007fff8>, 143 <0x10012 0x10012 0x0007fff8>, 144 <0x10013 0x10013 0x0007fff8>; 145 riscv,event-to-mhpmevent = 146 <0x00003 0x00000000 0x00000001>, 147 <0x00004 0x00000000 0x00000002>, 148 <0x00006 0x00000000 0x00000006>, 149 <0x00005 0x00000000 0x00000007>, 150 <0x00007 0x00000000 0x00000008>, 151 <0x00008 0x00000000 0x00000009>, 152 <0x00009 0x00000000 0x0000000a>, 153 <0x0000a 0x00000000 0x0000000b>, 154 <0x10000 0x00000000 0x0000000c>, 155 <0x10001 0x00000000 0x0000000d>, 156 <0x10002 0x00000000 0x0000000e>, 157 <0x10003 0x00000000 0x0000000f>, 158 <0x10010 0x00000000 0x00000010>, 159 <0x10011 0x00000000 0x00000011>, 160 <0x10012 0x00000000 0x00000012>, 161 <0x10013 0x00000000 0x00000013>; 162 riscv,raw-event-to-mhpmcounters = 163 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 164 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 165 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 205 }; 206 207 osc: oscillator { 208 compatible = "fixed-clock"; 209 clock-output-names = "osc_24m"; 210 #clock-cells = <0>; 211 }; 212 213 osc_32k: 32k-oscillator { 214 compatible = "fixed-clock"; 215 clock-output-names = "osc_32k"; 216 #clock-cells = <0>; 217 }; 218 219 aonsys_clk: clock-73728000 { 220 compatible = "fixed-clock"; 221 clock-frequency = <73728000>; 222 clock-output-names = "aonsys_clk"; 223 #clock-cells = <0>; 224 }; 225 226 soc { 227 compatible = "simple-bus"; 228 interrupt-parent = <&plic>; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 dma-noncoherent; 232 ranges; 233 234 plic: interrupt-controller@ffd8000000 { 235 compatible = "thead,th1520-plic", "thead,c900-plic"; 236 reg = <0xff 0xd8000000 0x0 0x01000000>; 237 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 238 <&cpu1_intc 11>, <&cpu1_intc 9>, 239 <&cpu2_intc 11>, <&cpu2_intc 9>, 240 <&cpu3_intc 11>, <&cpu3_intc 9>; 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <2>; 244 riscv,ndev = <240>; 245 }; 246 247 clint: timer@ffdc000000 { 248 compatible = "thead,th1520-clint", "thead,c900-clint"; 249 reg = <0xff 0xdc000000 0x0 0x00010000>; 250 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 251 <&cpu1_intc 3>, <&cpu1_intc 7>, 252 <&cpu2_intc 3>, <&cpu2_intc 7>, 253 <&cpu3_intc 3>, <&cpu3_intc 7>; 254 }; 255 256 spi0: spi@ffe700c000 { 257 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 258 reg = <0xff 0xe700c000 0x0 0x1000>; 259 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clk CLK_SPI>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 status = "disabled"; 264 }; 265 266 uart0: serial@ffe7014000 { 267 compatible = "snps,dw-apb-uart"; 268 reg = <0xff 0xe7014000 0x0 0x100>; 269 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 271 clock-names = "baudclk", "apb_pclk"; 272 reg-shift = <2>; 273 reg-io-width = <4>; 274 status = "disabled"; 275 }; 276 277 emmc: mmc@ffe7080000 { 278 compatible = "thead,th1520-dwcmshc"; 279 reg = <0xff 0xe7080000 0x0 0x10000>; 280 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk CLK_EMMC_SDIO>; 282 clock-names = "core"; 283 status = "disabled"; 284 }; 285 286 sdio0: mmc@ffe7090000 { 287 compatible = "thead,th1520-dwcmshc"; 288 reg = <0xff 0xe7090000 0x0 0x10000>; 289 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clk CLK_EMMC_SDIO>; 291 clock-names = "core"; 292 status = "disabled"; 293 }; 294 295 sdio1: mmc@ffe70a0000 { 296 compatible = "thead,th1520-dwcmshc"; 297 reg = <0xff 0xe70a0000 0x0 0x10000>; 298 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clk CLK_EMMC_SDIO>; 300 clock-names = "core"; 301 status = "disabled"; 302 }; 303 304 uart1: serial@ffe7f00000 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0xff 0xe7f00000 0x0 0x100>; 307 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 309 clock-names = "baudclk", "apb_pclk"; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 status = "disabled"; 313 }; 314 315 uart3: serial@ffe7f04000 { 316 compatible = "snps,dw-apb-uart"; 317 reg = <0xff 0xe7f04000 0x0 0x100>; 318 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 320 clock-names = "baudclk", "apb_pclk"; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 status = "disabled"; 324 }; 325 326 gpio2: gpio@ffe7f34000 { 327 compatible = "snps,dw-apb-gpio"; 328 reg = <0xff 0xe7f34000 0x0 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clocks = <&clk CLK_GPIO2>; 332 333 portc: gpio-controller@0 { 334 compatible = "snps,dw-apb-gpio-port"; 335 gpio-controller; 336 #gpio-cells = <2>; 337 ngpios = <32>; 338 reg = <0>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 342 }; 343 }; 344 345 gpio3: gpio@ffe7f38000 { 346 compatible = "snps,dw-apb-gpio"; 347 reg = <0xff 0xe7f38000 0x0 0x1000>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clocks = <&clk CLK_GPIO3>; 351 352 portd: gpio-controller@0 { 353 compatible = "snps,dw-apb-gpio-port"; 354 gpio-controller; 355 #gpio-cells = <2>; 356 ngpios = <32>; 357 reg = <0>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 361 }; 362 }; 363 364 padctrl1_apsys: pinctrl@ffe7f3c000 { 365 compatible = "thead,th1520-pinctrl"; 366 reg = <0xff 0xe7f3c000 0x0 0x1000>; 367 clocks = <&clk CLK_PADCTRL1>; 368 thead,pad-group = <2>; 369 }; 370 371 gpio0: gpio@ffec005000 { 372 compatible = "snps,dw-apb-gpio"; 373 reg = <0xff 0xec005000 0x0 0x1000>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&clk CLK_GPIO0>; 377 378 porta: gpio-controller@0 { 379 compatible = "snps,dw-apb-gpio-port"; 380 gpio-controller; 381 #gpio-cells = <2>; 382 ngpios = <32>; 383 reg = <0>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 387 }; 388 }; 389 390 gpio1: gpio@ffec006000 { 391 compatible = "snps,dw-apb-gpio"; 392 reg = <0xff 0xec006000 0x0 0x1000>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clocks = <&clk CLK_GPIO1>; 396 397 portb: gpio-controller@0 { 398 compatible = "snps,dw-apb-gpio-port"; 399 gpio-controller; 400 #gpio-cells = <2>; 401 ngpios = <32>; 402 reg = <0>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 406 }; 407 }; 408 409 padctrl0_apsys: pinctrl@ffec007000 { 410 compatible = "thead,th1520-pinctrl"; 411 reg = <0xff 0xec007000 0x0 0x1000>; 412 clocks = <&clk CLK_PADCTRL0>; 413 thead,pad-group = <3>; 414 }; 415 416 uart2: serial@ffec010000 { 417 compatible = "snps,dw-apb-uart"; 418 reg = <0xff 0xec010000 0x0 0x4000>; 419 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 421 clock-names = "baudclk", "apb_pclk"; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 status = "disabled"; 425 }; 426 427 clk: clock-controller@ffef010000 { 428 compatible = "thead,th1520-clk-ap"; 429 reg = <0xff 0xef010000 0x0 0x1000>; 430 clocks = <&osc>; 431 #clock-cells = <1>; 432 }; 433 434 dmac0: dma-controller@ffefc00000 { 435 compatible = "snps,axi-dma-1.01a"; 436 reg = <0xff 0xefc00000 0x0 0x1000>; 437 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 439 clock-names = "core-clk", "cfgr-clk"; 440 #dma-cells = <1>; 441 dma-channels = <4>; 442 snps,block-size = <65536 65536 65536 65536>; 443 snps,priority = <0 1 2 3>; 444 snps,dma-masters = <1>; 445 snps,data-width = <4>; 446 snps,axi-max-burst-len = <16>; 447 status = "disabled"; 448 }; 449 450 timer0: timer@ffefc32000 { 451 compatible = "snps,dw-apb-timer"; 452 reg = <0xff 0xefc32000 0x0 0x14>; 453 clocks = <&clk CLK_PERI_APB_PCLK>; 454 clock-names = "timer"; 455 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 456 status = "disabled"; 457 }; 458 459 timer1: timer@ffefc32014 { 460 compatible = "snps,dw-apb-timer"; 461 reg = <0xff 0xefc32014 0x0 0x14>; 462 clocks = <&clk CLK_PERI_APB_PCLK>; 463 clock-names = "timer"; 464 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 465 status = "disabled"; 466 }; 467 468 timer2: timer@ffefc32028 { 469 compatible = "snps,dw-apb-timer"; 470 reg = <0xff 0xefc32028 0x0 0x14>; 471 clocks = <&clk CLK_PERI_APB_PCLK>; 472 clock-names = "timer"; 473 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 474 status = "disabled"; 475 }; 476 477 timer3: timer@ffefc3203c { 478 compatible = "snps,dw-apb-timer"; 479 reg = <0xff 0xefc3203c 0x0 0x14>; 480 clocks = <&clk CLK_PERI_APB_PCLK>; 481 clock-names = "timer"; 482 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 483 status = "disabled"; 484 }; 485 486 uart4: serial@fff7f08000 { 487 compatible = "snps,dw-apb-uart"; 488 reg = <0xff 0xf7f08000 0x0 0x4000>; 489 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 491 clock-names = "baudclk", "apb_pclk"; 492 reg-shift = <2>; 493 reg-io-width = <4>; 494 status = "disabled"; 495 }; 496 497 uart5: serial@fff7f0c000 { 498 compatible = "snps,dw-apb-uart"; 499 reg = <0xff 0xf7f0c000 0x0 0x4000>; 500 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 502 clock-names = "baudclk", "apb_pclk"; 503 reg-shift = <2>; 504 reg-io-width = <4>; 505 status = "disabled"; 506 }; 507 508 timer4: timer@ffffc33000 { 509 compatible = "snps,dw-apb-timer"; 510 reg = <0xff 0xffc33000 0x0 0x14>; 511 clocks = <&clk CLK_PERI_APB_PCLK>; 512 clock-names = "timer"; 513 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 514 status = "disabled"; 515 }; 516 517 timer5: timer@ffffc33014 { 518 compatible = "snps,dw-apb-timer"; 519 reg = <0xff 0xffc33014 0x0 0x14>; 520 clocks = <&clk CLK_PERI_APB_PCLK>; 521 clock-names = "timer"; 522 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 523 status = "disabled"; 524 }; 525 526 timer6: timer@ffffc33028 { 527 compatible = "snps,dw-apb-timer"; 528 reg = <0xff 0xffc33028 0x0 0x14>; 529 clocks = <&clk CLK_PERI_APB_PCLK>; 530 clock-names = "timer"; 531 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 532 status = "disabled"; 533 }; 534 535 timer7: timer@ffffc3303c { 536 compatible = "snps,dw-apb-timer"; 537 reg = <0xff 0xffc3303c 0x0 0x14>; 538 clocks = <&clk CLK_PERI_APB_PCLK>; 539 clock-names = "timer"; 540 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 541 status = "disabled"; 542 }; 543 544 ao_gpio0: gpio@fffff41000 { 545 compatible = "snps,dw-apb-gpio"; 546 reg = <0xff 0xfff41000 0x0 0x1000>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 550 porte: gpio-controller@0 { 551 compatible = "snps,dw-apb-gpio-port"; 552 gpio-controller; 553 #gpio-cells = <2>; 554 ngpios = <32>; 555 reg = <0>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 559 }; 560 }; 561 562 padctrl_aosys: pinctrl@fffff4a000 { 563 compatible = "thead,th1520-pinctrl"; 564 reg = <0xff 0xfff4a000 0x0 0x2000>; 565 clocks = <&aonsys_clk>; 566 thead,pad-group = <1>; 567 }; 568 569 ao_gpio1: gpio@fffff52000 { 570 compatible = "snps,dw-apb-gpio"; 571 reg = <0xff 0xfff52000 0x0 0x1000>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 575 portf: gpio-controller@0 { 576 compatible = "snps,dw-apb-gpio-port"; 577 gpio-controller; 578 #gpio-cells = <2>; 579 ngpios = <32>; 580 reg = <0>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 584 }; 585 }; 586 }; 587}; 588