1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9#include <dt-bindings/power/thead,th1520-power.h> 10#include <dt-bindings/reset/thead,th1520-reset.h> 11 12/ { 13 compatible = "thead,th1520"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 timebase-frequency = <3000000>; 21 22 c910_0: cpu@0 { 23 compatible = "thead,c910", "riscv"; 24 device_type = "cpu"; 25 riscv,isa = "rv64imafdc"; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 28 "zifencei", "zihpm"; 29 reg = <0>; 30 i-cache-block-size = <64>; 31 i-cache-size = <65536>; 32 i-cache-sets = <512>; 33 d-cache-block-size = <64>; 34 d-cache-size = <65536>; 35 d-cache-sets = <512>; 36 next-level-cache = <&l2_cache>; 37 mmu-type = "riscv,sv39"; 38 39 cpu0_intc: interrupt-controller { 40 compatible = "riscv,cpu-intc"; 41 interrupt-controller; 42 #interrupt-cells = <1>; 43 }; 44 }; 45 46 c910_1: cpu@1 { 47 compatible = "thead,c910", "riscv"; 48 device_type = "cpu"; 49 riscv,isa = "rv64imafdc"; 50 riscv,isa-base = "rv64i"; 51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 52 "zifencei", "zihpm"; 53 reg = <1>; 54 i-cache-block-size = <64>; 55 i-cache-size = <65536>; 56 i-cache-sets = <512>; 57 d-cache-block-size = <64>; 58 d-cache-size = <65536>; 59 d-cache-sets = <512>; 60 next-level-cache = <&l2_cache>; 61 mmu-type = "riscv,sv39"; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 70 c910_2: cpu@2 { 71 compatible = "thead,c910", "riscv"; 72 device_type = "cpu"; 73 riscv,isa = "rv64imafdc"; 74 riscv,isa-base = "rv64i"; 75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 76 "zifencei", "zihpm"; 77 reg = <2>; 78 i-cache-block-size = <64>; 79 i-cache-size = <65536>; 80 i-cache-sets = <512>; 81 d-cache-block-size = <64>; 82 d-cache-size = <65536>; 83 d-cache-sets = <512>; 84 next-level-cache = <&l2_cache>; 85 mmu-type = "riscv,sv39"; 86 87 cpu2_intc: interrupt-controller { 88 compatible = "riscv,cpu-intc"; 89 interrupt-controller; 90 #interrupt-cells = <1>; 91 }; 92 }; 93 94 c910_3: cpu@3 { 95 compatible = "thead,c910", "riscv"; 96 device_type = "cpu"; 97 riscv,isa = "rv64imafdc"; 98 riscv,isa-base = "rv64i"; 99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 100 "zifencei", "zihpm"; 101 reg = <3>; 102 i-cache-block-size = <64>; 103 i-cache-size = <65536>; 104 i-cache-sets = <512>; 105 d-cache-block-size = <64>; 106 d-cache-size = <65536>; 107 d-cache-sets = <512>; 108 next-level-cache = <&l2_cache>; 109 mmu-type = "riscv,sv39"; 110 111 cpu3_intc: interrupt-controller { 112 compatible = "riscv,cpu-intc"; 113 interrupt-controller; 114 #interrupt-cells = <1>; 115 }; 116 }; 117 118 l2_cache: l2-cache { 119 compatible = "cache"; 120 cache-block-size = <64>; 121 cache-level = <2>; 122 cache-size = <1048576>; 123 cache-sets = <1024>; 124 cache-unified; 125 }; 126 }; 127 128 pmu { 129 compatible = "riscv,pmu"; 130 riscv,event-to-mhpmcounters = 131 <0x00003 0x00003 0x0007fff8>, 132 <0x00004 0x00004 0x0007fff8>, 133 <0x00005 0x00005 0x0007fff8>, 134 <0x00006 0x00006 0x0007fff8>, 135 <0x00007 0x00007 0x0007fff8>, 136 <0x00008 0x00008 0x0007fff8>, 137 <0x00009 0x00009 0x0007fff8>, 138 <0x0000a 0x0000a 0x0007fff8>, 139 <0x10000 0x10000 0x0007fff8>, 140 <0x10001 0x10001 0x0007fff8>, 141 <0x10002 0x10002 0x0007fff8>, 142 <0x10003 0x10003 0x0007fff8>, 143 <0x10010 0x10010 0x0007fff8>, 144 <0x10011 0x10011 0x0007fff8>, 145 <0x10012 0x10012 0x0007fff8>, 146 <0x10013 0x10013 0x0007fff8>; 147 riscv,event-to-mhpmevent = 148 <0x00003 0x00000000 0x00000001>, 149 <0x00004 0x00000000 0x00000002>, 150 <0x00006 0x00000000 0x00000006>, 151 <0x00005 0x00000000 0x00000007>, 152 <0x00007 0x00000000 0x00000008>, 153 <0x00008 0x00000000 0x00000009>, 154 <0x00009 0x00000000 0x0000000a>, 155 <0x0000a 0x00000000 0x0000000b>, 156 <0x10000 0x00000000 0x0000000c>, 157 <0x10001 0x00000000 0x0000000d>, 158 <0x10002 0x00000000 0x0000000e>, 159 <0x10003 0x00000000 0x0000000f>, 160 <0x10010 0x00000000 0x00000010>, 161 <0x10011 0x00000000 0x00000011>, 162 <0x10012 0x00000000 0x00000012>, 163 <0x10013 0x00000000 0x00000013>; 164 riscv,raw-event-to-mhpmcounters = 165 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 205 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 206 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 207 }; 208 209 osc: oscillator { 210 compatible = "fixed-clock"; 211 clock-output-names = "osc_24m"; 212 #clock-cells = <0>; 213 }; 214 215 osc_32k: 32k-oscillator { 216 compatible = "fixed-clock"; 217 clock-output-names = "osc_32k"; 218 #clock-cells = <0>; 219 }; 220 221 aonsys_clk: clock-73728000 { 222 compatible = "fixed-clock"; 223 clock-frequency = <73728000>; 224 clock-output-names = "aonsys_clk"; 225 #clock-cells = <0>; 226 }; 227 228 gpu_mem_clk: mem-clk { 229 compatible = "fixed-clock"; 230 clock-frequency = <0>; 231 clock-output-names = "gpu_mem_clk"; 232 #clock-cells = <0>; 233 }; 234 235 stmmac_axi_config: stmmac-axi-config { 236 snps,wr_osr_lmt = <15>; 237 snps,rd_osr_lmt = <15>; 238 snps,blen = <0 0 64 32 0 0 0>; 239 }; 240 241 aon: aon { 242 compatible = "thead,th1520-aon"; 243 mboxes = <&mbox_910t 1>; 244 mbox-names = "aon"; 245 resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; 246 reset-names = "gpu-clkgen"; 247 #power-domain-cells = <1>; 248 }; 249 250 soc { 251 compatible = "simple-bus"; 252 interrupt-parent = <&plic>; 253 #address-cells = <2>; 254 #size-cells = <2>; 255 dma-noncoherent; 256 ranges; 257 258 plic: interrupt-controller@ffd8000000 { 259 compatible = "thead,th1520-plic", "thead,c900-plic"; 260 reg = <0xff 0xd8000000 0x0 0x01000000>; 261 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 262 <&cpu1_intc 11>, <&cpu1_intc 9>, 263 <&cpu2_intc 11>, <&cpu2_intc 9>, 264 <&cpu3_intc 11>, <&cpu3_intc 9>; 265 interrupt-controller; 266 #address-cells = <0>; 267 #interrupt-cells = <2>; 268 riscv,ndev = <240>; 269 }; 270 271 clint: timer@ffdc000000 { 272 compatible = "thead,th1520-clint", "thead,c900-clint"; 273 reg = <0xff 0xdc000000 0x0 0x00010000>; 274 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 275 <&cpu1_intc 3>, <&cpu1_intc 7>, 276 <&cpu2_intc 3>, <&cpu2_intc 7>, 277 <&cpu3_intc 3>, <&cpu3_intc 7>; 278 }; 279 280 spi0: spi@ffe700c000 { 281 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 282 reg = <0xff 0xe700c000 0x0 0x1000>; 283 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clk CLK_SPI>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 status = "disabled"; 288 }; 289 290 uart0: serial@ffe7014000 { 291 compatible = "snps,dw-apb-uart"; 292 reg = <0xff 0xe7014000 0x0 0x100>; 293 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 295 clock-names = "baudclk", "apb_pclk"; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 status = "disabled"; 299 }; 300 301 gmac1: ethernet@ffe7060000 { 302 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 303 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 304 reg-names = "dwmac", "apb"; 305 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "macirq"; 307 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>, 308 <&clk CLK_PERISYS_APB4_HCLK>; 309 clock-names = "stmmaceth", "pclk", "apb"; 310 snps,pbl = <32>; 311 snps,fixed-burst; 312 snps,multicast-filter-bins = <64>; 313 snps,perfect-filter-entries = <32>; 314 snps,axi-config = <&stmmac_axi_config>; 315 status = "disabled"; 316 317 mdio1: mdio { 318 compatible = "snps,dwmac-mdio"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 }; 322 }; 323 324 gmac0: ethernet@ffe7070000 { 325 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 326 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 327 reg-names = "dwmac", "apb"; 328 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-names = "macirq"; 330 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>, 331 <&clk CLK_PERISYS_APB4_HCLK>; 332 clock-names = "stmmaceth", "pclk", "apb"; 333 snps,pbl = <32>; 334 snps,fixed-burst; 335 snps,multicast-filter-bins = <64>; 336 snps,perfect-filter-entries = <32>; 337 snps,axi-config = <&stmmac_axi_config>; 338 status = "disabled"; 339 340 mdio0: mdio { 341 compatible = "snps,dwmac-mdio"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 }; 345 }; 346 347 emmc: mmc@ffe7080000 { 348 compatible = "thead,th1520-dwcmshc"; 349 reg = <0xff 0xe7080000 0x0 0x10000>; 350 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clk CLK_EMMC_SDIO>; 352 clock-names = "core"; 353 status = "disabled"; 354 }; 355 356 sdio0: mmc@ffe7090000 { 357 compatible = "thead,th1520-dwcmshc"; 358 reg = <0xff 0xe7090000 0x0 0x10000>; 359 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk CLK_EMMC_SDIO>; 361 clock-names = "core"; 362 status = "disabled"; 363 }; 364 365 sdio1: mmc@ffe70a0000 { 366 compatible = "thead,th1520-dwcmshc"; 367 reg = <0xff 0xe70a0000 0x0 0x10000>; 368 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk CLK_EMMC_SDIO>; 370 clock-names = "core"; 371 status = "disabled"; 372 }; 373 374 uart1: serial@ffe7f00000 { 375 compatible = "snps,dw-apb-uart"; 376 reg = <0xff 0xe7f00000 0x0 0x100>; 377 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 379 clock-names = "baudclk", "apb_pclk"; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 status = "disabled"; 383 }; 384 385 uart3: serial@ffe7f04000 { 386 compatible = "snps,dw-apb-uart"; 387 reg = <0xff 0xe7f04000 0x0 0x100>; 388 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 390 clock-names = "baudclk", "apb_pclk"; 391 reg-shift = <2>; 392 reg-io-width = <4>; 393 status = "disabled"; 394 }; 395 396 gpio@ffe7f34000 { 397 compatible = "snps,dw-apb-gpio"; 398 reg = <0xff 0xe7f34000 0x0 0x1000>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 clocks = <&clk CLK_GPIO2>; 402 clock-names = "bus"; 403 404 gpio2: gpio-controller@0 { 405 compatible = "snps,dw-apb-gpio-port"; 406 gpio-controller; 407 #gpio-cells = <2>; 408 ngpios = <32>; 409 gpio-ranges = <&padctrl0_apsys 0 0 32>; 410 reg = <0>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 414 }; 415 }; 416 417 gpio@ffe7f38000 { 418 compatible = "snps,dw-apb-gpio"; 419 reg = <0xff 0xe7f38000 0x0 0x1000>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 clocks = <&clk CLK_GPIO3>; 423 clock-names = "bus"; 424 425 gpio3: gpio-controller@0 { 426 compatible = "snps,dw-apb-gpio-port"; 427 gpio-controller; 428 #gpio-cells = <2>; 429 ngpios = <23>; 430 gpio-ranges = <&padctrl0_apsys 0 32 23>; 431 reg = <0>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 435 }; 436 }; 437 438 padctrl1_apsys: pinctrl@ffe7f3c000 { 439 compatible = "thead,th1520-pinctrl"; 440 reg = <0xff 0xe7f3c000 0x0 0x1000>; 441 clocks = <&clk CLK_PADCTRL1>; 442 thead,pad-group = <2>; 443 }; 444 445 gpio@ffec005000 { 446 compatible = "snps,dw-apb-gpio"; 447 reg = <0xff 0xec005000 0x0 0x1000>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clocks = <&clk CLK_GPIO0>; 451 clock-names = "bus"; 452 453 gpio0: gpio-controller@0 { 454 compatible = "snps,dw-apb-gpio-port"; 455 gpio-controller; 456 #gpio-cells = <2>; 457 ngpios = <32>; 458 gpio-ranges = <&padctrl1_apsys 0 0 32>; 459 reg = <0>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 463 }; 464 }; 465 466 gpio@ffec006000 { 467 compatible = "snps,dw-apb-gpio"; 468 reg = <0xff 0xec006000 0x0 0x1000>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 clocks = <&clk CLK_GPIO1>; 472 clock-names = "bus"; 473 474 gpio1: gpio-controller@0 { 475 compatible = "snps,dw-apb-gpio-port"; 476 gpio-controller; 477 #gpio-cells = <2>; 478 ngpios = <31>; 479 gpio-ranges = <&padctrl1_apsys 0 32 31>; 480 reg = <0>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 484 }; 485 }; 486 487 padctrl0_apsys: pinctrl@ffec007000 { 488 compatible = "thead,th1520-pinctrl"; 489 reg = <0xff 0xec007000 0x0 0x1000>; 490 clocks = <&clk CLK_PADCTRL0>; 491 thead,pad-group = <3>; 492 }; 493 494 uart2: serial@ffec010000 { 495 compatible = "snps,dw-apb-uart"; 496 reg = <0xff 0xec010000 0x0 0x4000>; 497 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 499 clock-names = "baudclk", "apb_pclk"; 500 reg-shift = <2>; 501 reg-io-width = <4>; 502 status = "disabled"; 503 }; 504 505 clk: clock-controller@ffef010000 { 506 compatible = "thead,th1520-clk-ap"; 507 reg = <0xff 0xef010000 0x0 0x1000>; 508 clocks = <&osc>; 509 #clock-cells = <1>; 510 }; 511 512 gpu: gpu@ffef400000 { 513 compatible = "thead,th1520-gpu", "img,img-bxm-4-64", 514 "img,img-rogue"; 515 reg = <0xff 0xef400000 0x0 0x100000>; 516 interrupt-parent = <&plic>; 517 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk_vo CLK_GPU_CORE>, 519 <&gpu_mem_clk>, 520 <&clk_vo CLK_GPU_CFG_ACLK>; 521 clock-names = "core", "mem", "sys"; 522 power-domains = <&aon TH1520_GPU_PD>; 523 resets = <&rst TH1520_RESET_ID_GPU>; 524 }; 525 526 rst: reset-controller@ffef528000 { 527 compatible = "thead,th1520-reset"; 528 reg = <0xff 0xef528000 0x0 0x4f>; 529 #reset-cells = <1>; 530 }; 531 532 clk_vo: clock-controller@ffef528050 { 533 compatible = "thead,th1520-clk-vo"; 534 reg = <0xff 0xef528050 0x0 0xfb0>; 535 clocks = <&clk CLK_VIDEO_PLL>; 536 #clock-cells = <1>; 537 }; 538 539 dmac0: dma-controller@ffefc00000 { 540 compatible = "snps,axi-dma-1.01a"; 541 reg = <0xff 0xefc00000 0x0 0x1000>; 542 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 544 clock-names = "core-clk", "cfgr-clk"; 545 #dma-cells = <1>; 546 dma-channels = <4>; 547 snps,block-size = <65536 65536 65536 65536>; 548 snps,priority = <0 1 2 3>; 549 snps,dma-masters = <1>; 550 snps,data-width = <4>; 551 snps,axi-max-burst-len = <16>; 552 status = "disabled"; 553 }; 554 555 timer0: timer@ffefc32000 { 556 compatible = "snps,dw-apb-timer"; 557 reg = <0xff 0xefc32000 0x0 0x14>; 558 clocks = <&clk CLK_PERI_APB_PCLK>; 559 clock-names = "timer"; 560 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 561 status = "disabled"; 562 }; 563 564 timer1: timer@ffefc32014 { 565 compatible = "snps,dw-apb-timer"; 566 reg = <0xff 0xefc32014 0x0 0x14>; 567 clocks = <&clk CLK_PERI_APB_PCLK>; 568 clock-names = "timer"; 569 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 570 status = "disabled"; 571 }; 572 573 timer2: timer@ffefc32028 { 574 compatible = "snps,dw-apb-timer"; 575 reg = <0xff 0xefc32028 0x0 0x14>; 576 clocks = <&clk CLK_PERI_APB_PCLK>; 577 clock-names = "timer"; 578 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 582 timer3: timer@ffefc3203c { 583 compatible = "snps,dw-apb-timer"; 584 reg = <0xff 0xefc3203c 0x0 0x14>; 585 clocks = <&clk CLK_PERI_APB_PCLK>; 586 clock-names = "timer"; 587 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 588 status = "disabled"; 589 }; 590 591 uart4: serial@fff7f08000 { 592 compatible = "snps,dw-apb-uart"; 593 reg = <0xff 0xf7f08000 0x0 0x4000>; 594 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 596 clock-names = "baudclk", "apb_pclk"; 597 reg-shift = <2>; 598 reg-io-width = <4>; 599 status = "disabled"; 600 }; 601 602 uart5: serial@fff7f0c000 { 603 compatible = "snps,dw-apb-uart"; 604 reg = <0xff 0xf7f0c000 0x0 0x4000>; 605 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 607 clock-names = "baudclk", "apb_pclk"; 608 reg-shift = <2>; 609 reg-io-width = <4>; 610 status = "disabled"; 611 }; 612 613 timer4: timer@ffffc33000 { 614 compatible = "snps,dw-apb-timer"; 615 reg = <0xff 0xffc33000 0x0 0x14>; 616 clocks = <&clk CLK_PERI_APB_PCLK>; 617 clock-names = "timer"; 618 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 619 status = "disabled"; 620 }; 621 622 timer5: timer@ffffc33014 { 623 compatible = "snps,dw-apb-timer"; 624 reg = <0xff 0xffc33014 0x0 0x14>; 625 clocks = <&clk CLK_PERI_APB_PCLK>; 626 clock-names = "timer"; 627 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 628 status = "disabled"; 629 }; 630 631 timer6: timer@ffffc33028 { 632 compatible = "snps,dw-apb-timer"; 633 reg = <0xff 0xffc33028 0x0 0x14>; 634 clocks = <&clk CLK_PERI_APB_PCLK>; 635 clock-names = "timer"; 636 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 637 status = "disabled"; 638 }; 639 640 timer7: timer@ffffc3303c { 641 compatible = "snps,dw-apb-timer"; 642 reg = <0xff 0xffc3303c 0x0 0x14>; 643 clocks = <&clk CLK_PERI_APB_PCLK>; 644 clock-names = "timer"; 645 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 646 status = "disabled"; 647 }; 648 649 mbox_910t: mailbox@ffffc38000 { 650 compatible = "thead,th1520-mbox"; 651 reg = <0xff 0xffc38000 0x0 0x6000>, 652 <0xff 0xffc40000 0x0 0x6000>, 653 <0xff 0xffc4c000 0x0 0x2000>, 654 <0xff 0xffc54000 0x0 0x2000>; 655 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; 656 clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, 657 <&clk CLK_MBOX3>; 658 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", 659 "clk-remote-icu2"; 660 interrupt-parent = <&plic>; 661 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 662 #mbox-cells = <1>; 663 }; 664 665 gpio@fffff41000 { 666 compatible = "snps,dw-apb-gpio"; 667 reg = <0xff 0xfff41000 0x0 0x1000>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 671 aogpio: gpio-controller@0 { 672 compatible = "snps,dw-apb-gpio-port"; 673 gpio-controller; 674 #gpio-cells = <2>; 675 ngpios = <16>; 676 gpio-ranges = <&padctrl_aosys 0 9 16>; 677 reg = <0>; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 }; 683 684 padctrl_aosys: pinctrl@fffff4a000 { 685 compatible = "thead,th1520-pinctrl"; 686 reg = <0xff 0xfff4a000 0x0 0x2000>; 687 clocks = <&aonsys_clk>; 688 thead,pad-group = <1>; 689 }; 690 691 pvt: pvt@fffff4e000 { 692 compatible = "moortec,mr75203"; 693 reg = <0xff 0xfff4e000 0x0 0x80>, 694 <0xff 0xfff4e080 0x0 0x100>, 695 <0xff 0xfff4e180 0x0 0x680>, 696 <0xff 0xfff4e800 0x0 0x600>; 697 reg-names = "common", "ts", "pd", "vm"; 698 clocks = <&aonsys_clk>; 699 #thermal-sensor-cells = <1>; 700 }; 701 702 gpio@fffff52000 { 703 compatible = "snps,dw-apb-gpio"; 704 reg = <0xff 0xfff52000 0x0 0x1000>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 gpio4: gpio-controller@0 { 709 compatible = "snps,dw-apb-gpio-port"; 710 gpio-controller; 711 #gpio-cells = <2>; 712 ngpios = <23>; 713 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 714 reg = <0>; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 718 }; 719 }; 720 }; 721}; 722