1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "thead,th1520"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus: cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 timebase-frequency = <3000000>; 18 19 c910_0: cpu@0 { 20 compatible = "thead,c910", "riscv"; 21 device_type = "cpu"; 22 riscv,isa = "rv64imafdc"; 23 riscv,isa-base = "rv64i"; 24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 25 "zifencei", "zihpm"; 26 reg = <0>; 27 i-cache-block-size = <64>; 28 i-cache-size = <65536>; 29 i-cache-sets = <512>; 30 d-cache-block-size = <64>; 31 d-cache-size = <65536>; 32 d-cache-sets = <512>; 33 next-level-cache = <&l2_cache>; 34 mmu-type = "riscv,sv39"; 35 36 cpu0_intc: interrupt-controller { 37 compatible = "riscv,cpu-intc"; 38 interrupt-controller; 39 #interrupt-cells = <1>; 40 }; 41 }; 42 43 c910_1: cpu@1 { 44 compatible = "thead,c910", "riscv"; 45 device_type = "cpu"; 46 riscv,isa = "rv64imafdc"; 47 riscv,isa-base = "rv64i"; 48 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 49 "zifencei", "zihpm"; 50 reg = <1>; 51 i-cache-block-size = <64>; 52 i-cache-size = <65536>; 53 i-cache-sets = <512>; 54 d-cache-block-size = <64>; 55 d-cache-size = <65536>; 56 d-cache-sets = <512>; 57 next-level-cache = <&l2_cache>; 58 mmu-type = "riscv,sv39"; 59 60 cpu1_intc: interrupt-controller { 61 compatible = "riscv,cpu-intc"; 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 }; 65 }; 66 67 c910_2: cpu@2 { 68 compatible = "thead,c910", "riscv"; 69 device_type = "cpu"; 70 riscv,isa = "rv64imafdc"; 71 riscv,isa-base = "rv64i"; 72 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 73 "zifencei", "zihpm"; 74 reg = <2>; 75 i-cache-block-size = <64>; 76 i-cache-size = <65536>; 77 i-cache-sets = <512>; 78 d-cache-block-size = <64>; 79 d-cache-size = <65536>; 80 d-cache-sets = <512>; 81 next-level-cache = <&l2_cache>; 82 mmu-type = "riscv,sv39"; 83 84 cpu2_intc: interrupt-controller { 85 compatible = "riscv,cpu-intc"; 86 interrupt-controller; 87 #interrupt-cells = <1>; 88 }; 89 }; 90 91 c910_3: cpu@3 { 92 compatible = "thead,c910", "riscv"; 93 device_type = "cpu"; 94 riscv,isa = "rv64imafdc"; 95 riscv,isa-base = "rv64i"; 96 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 97 "zifencei", "zihpm"; 98 reg = <3>; 99 i-cache-block-size = <64>; 100 i-cache-size = <65536>; 101 i-cache-sets = <512>; 102 d-cache-block-size = <64>; 103 d-cache-size = <65536>; 104 d-cache-sets = <512>; 105 next-level-cache = <&l2_cache>; 106 mmu-type = "riscv,sv39"; 107 108 cpu3_intc: interrupt-controller { 109 compatible = "riscv,cpu-intc"; 110 interrupt-controller; 111 #interrupt-cells = <1>; 112 }; 113 }; 114 115 l2_cache: l2-cache { 116 compatible = "cache"; 117 cache-block-size = <64>; 118 cache-level = <2>; 119 cache-size = <1048576>; 120 cache-sets = <1024>; 121 cache-unified; 122 }; 123 }; 124 125 osc: oscillator { 126 compatible = "fixed-clock"; 127 clock-output-names = "osc_24m"; 128 #clock-cells = <0>; 129 }; 130 131 osc_32k: 32k-oscillator { 132 compatible = "fixed-clock"; 133 clock-output-names = "osc_32k"; 134 #clock-cells = <0>; 135 }; 136 137 apb_clk: apb-clk-clock { 138 compatible = "fixed-clock"; 139 clock-output-names = "apb_clk"; 140 #clock-cells = <0>; 141 }; 142 143 uart_sclk: uart-sclk-clock { 144 compatible = "fixed-clock"; 145 clock-output-names = "uart_sclk"; 146 #clock-cells = <0>; 147 }; 148 149 soc { 150 compatible = "simple-bus"; 151 interrupt-parent = <&plic>; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 dma-noncoherent; 155 ranges; 156 157 plic: interrupt-controller@ffd8000000 { 158 compatible = "thead,th1520-plic", "thead,c900-plic"; 159 reg = <0xff 0xd8000000 0x0 0x01000000>; 160 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 161 <&cpu1_intc 11>, <&cpu1_intc 9>, 162 <&cpu2_intc 11>, <&cpu2_intc 9>, 163 <&cpu3_intc 11>, <&cpu3_intc 9>; 164 interrupt-controller; 165 #address-cells = <0>; 166 #interrupt-cells = <2>; 167 riscv,ndev = <240>; 168 }; 169 170 clint: timer@ffdc000000 { 171 compatible = "thead,th1520-clint", "thead,c900-clint"; 172 reg = <0xff 0xdc000000 0x0 0x00010000>; 173 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 174 <&cpu1_intc 3>, <&cpu1_intc 7>, 175 <&cpu2_intc 3>, <&cpu2_intc 7>, 176 <&cpu3_intc 3>, <&cpu3_intc 7>; 177 }; 178 179 uart0: serial@ffe7014000 { 180 compatible = "snps,dw-apb-uart"; 181 reg = <0xff 0xe7014000 0x0 0x100>; 182 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&uart_sclk>; 184 reg-shift = <2>; 185 reg-io-width = <4>; 186 status = "disabled"; 187 }; 188 189 uart1: serial@ffe7f00000 { 190 compatible = "snps,dw-apb-uart"; 191 reg = <0xff 0xe7f00000 0x0 0x100>; 192 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&uart_sclk>; 194 reg-shift = <2>; 195 reg-io-width = <4>; 196 status = "disabled"; 197 }; 198 199 uart3: serial@ffe7f04000 { 200 compatible = "snps,dw-apb-uart"; 201 reg = <0xff 0xe7f04000 0x0 0x100>; 202 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&uart_sclk>; 204 reg-shift = <2>; 205 reg-io-width = <4>; 206 status = "disabled"; 207 }; 208 209 gpio2: gpio@ffe7f34000 { 210 compatible = "snps,dw-apb-gpio"; 211 reg = <0xff 0xe7f34000 0x0 0x1000>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 portc: gpio-controller@0 { 216 compatible = "snps,dw-apb-gpio-port"; 217 gpio-controller; 218 #gpio-cells = <2>; 219 ngpios = <32>; 220 reg = <0>; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 224 }; 225 }; 226 227 gpio3: gpio@ffe7f38000 { 228 compatible = "snps,dw-apb-gpio"; 229 reg = <0xff 0xe7f38000 0x0 0x1000>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 233 portd: gpio-controller@0 { 234 compatible = "snps,dw-apb-gpio-port"; 235 gpio-controller; 236 #gpio-cells = <2>; 237 ngpios = <32>; 238 reg = <0>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 }; 244 245 gpio0: gpio@ffec005000 { 246 compatible = "snps,dw-apb-gpio"; 247 reg = <0xff 0xec005000 0x0 0x1000>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 porta: gpio-controller@0 { 252 compatible = "snps,dw-apb-gpio-port"; 253 gpio-controller; 254 #gpio-cells = <2>; 255 ngpios = <32>; 256 reg = <0>; 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 260 }; 261 }; 262 263 gpio1: gpio@ffec006000 { 264 compatible = "snps,dw-apb-gpio"; 265 reg = <0xff 0xec006000 0x0 0x1000>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 portb: gpio-controller@0 { 270 compatible = "snps,dw-apb-gpio-port"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 ngpios = <32>; 274 reg = <0>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 278 }; 279 }; 280 281 uart2: serial@ffec010000 { 282 compatible = "snps,dw-apb-uart"; 283 reg = <0xff 0xec010000 0x0 0x4000>; 284 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&uart_sclk>; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 status = "disabled"; 289 }; 290 291 dmac0: dma-controller@ffefc00000 { 292 compatible = "snps,axi-dma-1.01a"; 293 reg = <0xff 0xefc00000 0x0 0x1000>; 294 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&apb_clk>, <&apb_clk>; 296 clock-names = "core-clk", "cfgr-clk"; 297 #dma-cells = <1>; 298 dma-channels = <4>; 299 snps,block-size = <65536 65536 65536 65536>; 300 snps,priority = <0 1 2 3>; 301 snps,dma-masters = <1>; 302 snps,data-width = <4>; 303 snps,axi-max-burst-len = <16>; 304 status = "disabled"; 305 }; 306 307 timer0: timer@ffefc32000 { 308 compatible = "snps,dw-apb-timer"; 309 reg = <0xff 0xefc32000 0x0 0x14>; 310 clocks = <&apb_clk>; 311 clock-names = "timer"; 312 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 313 status = "disabled"; 314 }; 315 316 timer1: timer@ffefc32014 { 317 compatible = "snps,dw-apb-timer"; 318 reg = <0xff 0xefc32014 0x0 0x14>; 319 clocks = <&apb_clk>; 320 clock-names = "timer"; 321 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 322 status = "disabled"; 323 }; 324 325 timer2: timer@ffefc32028 { 326 compatible = "snps,dw-apb-timer"; 327 reg = <0xff 0xefc32028 0x0 0x14>; 328 clocks = <&apb_clk>; 329 clock-names = "timer"; 330 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 331 status = "disabled"; 332 }; 333 334 timer3: timer@ffefc3203c { 335 compatible = "snps,dw-apb-timer"; 336 reg = <0xff 0xefc3203c 0x0 0x14>; 337 clocks = <&apb_clk>; 338 clock-names = "timer"; 339 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 340 status = "disabled"; 341 }; 342 343 uart4: serial@fff7f08000 { 344 compatible = "snps,dw-apb-uart"; 345 reg = <0xff 0xf7f08000 0x0 0x4000>; 346 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&uart_sclk>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 status = "disabled"; 351 }; 352 353 uart5: serial@fff7f0c000 { 354 compatible = "snps,dw-apb-uart"; 355 reg = <0xff 0xf7f0c000 0x0 0x4000>; 356 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&uart_sclk>; 358 reg-shift = <2>; 359 reg-io-width = <4>; 360 status = "disabled"; 361 }; 362 363 timer4: timer@ffffc33000 { 364 compatible = "snps,dw-apb-timer"; 365 reg = <0xff 0xffc33000 0x0 0x14>; 366 clocks = <&apb_clk>; 367 clock-names = "timer"; 368 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 369 status = "disabled"; 370 }; 371 372 timer5: timer@ffffc33014 { 373 compatible = "snps,dw-apb-timer"; 374 reg = <0xff 0xffc33014 0x0 0x14>; 375 clocks = <&apb_clk>; 376 clock-names = "timer"; 377 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 378 status = "disabled"; 379 }; 380 381 timer6: timer@ffffc33028 { 382 compatible = "snps,dw-apb-timer"; 383 reg = <0xff 0xffc33028 0x0 0x14>; 384 clocks = <&apb_clk>; 385 clock-names = "timer"; 386 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 387 status = "disabled"; 388 }; 389 390 timer7: timer@ffffc3303c { 391 compatible = "snps,dw-apb-timer"; 392 reg = <0xff 0xffc3303c 0x0 0x14>; 393 clocks = <&apb_clk>; 394 clock-names = "timer"; 395 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 }; 398 399 ao_gpio0: gpio@fffff41000 { 400 compatible = "snps,dw-apb-gpio"; 401 reg = <0xff 0xfff41000 0x0 0x1000>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 405 porte: gpio-controller@0 { 406 compatible = "snps,dw-apb-gpio-port"; 407 gpio-controller; 408 #gpio-cells = <2>; 409 ngpios = <32>; 410 reg = <0>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 414 }; 415 }; 416 417 ao_gpio1: gpio@fffff52000 { 418 compatible = "snps,dw-apb-gpio"; 419 reg = <0xff 0xfff52000 0x0 0x1000>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 423 portf: gpio-controller@0 { 424 compatible = "snps,dw-apb-gpio-port"; 425 gpio-controller; 426 #gpio-cells = <2>; 427 ngpios = <32>; 428 reg = <0>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 432 }; 433 }; 434 }; 435}; 436