1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9#include <dt-bindings/power/thead,th1520-power.h> 10#include <dt-bindings/reset/thead,th1520-reset.h> 11 12/ { 13 compatible = "thead,th1520"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 timebase-frequency = <3000000>; 21 22 c910_0: cpu@0 { 23 compatible = "thead,c910", "riscv"; 24 device_type = "cpu"; 25 riscv,isa = "rv64imafdc"; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 28 "zifencei", "zihpm"; 29 reg = <0>; 30 i-cache-block-size = <64>; 31 i-cache-size = <65536>; 32 i-cache-sets = <512>; 33 d-cache-block-size = <64>; 34 d-cache-size = <65536>; 35 d-cache-sets = <512>; 36 next-level-cache = <&l2_cache>; 37 mmu-type = "riscv,sv39"; 38 39 cpu0_intc: interrupt-controller { 40 compatible = "riscv,cpu-intc"; 41 interrupt-controller; 42 #interrupt-cells = <1>; 43 }; 44 }; 45 46 c910_1: cpu@1 { 47 compatible = "thead,c910", "riscv"; 48 device_type = "cpu"; 49 riscv,isa = "rv64imafdc"; 50 riscv,isa-base = "rv64i"; 51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 52 "zifencei", "zihpm"; 53 reg = <1>; 54 i-cache-block-size = <64>; 55 i-cache-size = <65536>; 56 i-cache-sets = <512>; 57 d-cache-block-size = <64>; 58 d-cache-size = <65536>; 59 d-cache-sets = <512>; 60 next-level-cache = <&l2_cache>; 61 mmu-type = "riscv,sv39"; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 70 c910_2: cpu@2 { 71 compatible = "thead,c910", "riscv"; 72 device_type = "cpu"; 73 riscv,isa = "rv64imafdc"; 74 riscv,isa-base = "rv64i"; 75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 76 "zifencei", "zihpm"; 77 reg = <2>; 78 i-cache-block-size = <64>; 79 i-cache-size = <65536>; 80 i-cache-sets = <512>; 81 d-cache-block-size = <64>; 82 d-cache-size = <65536>; 83 d-cache-sets = <512>; 84 next-level-cache = <&l2_cache>; 85 mmu-type = "riscv,sv39"; 86 87 cpu2_intc: interrupt-controller { 88 compatible = "riscv,cpu-intc"; 89 interrupt-controller; 90 #interrupt-cells = <1>; 91 }; 92 }; 93 94 c910_3: cpu@3 { 95 compatible = "thead,c910", "riscv"; 96 device_type = "cpu"; 97 riscv,isa = "rv64imafdc"; 98 riscv,isa-base = "rv64i"; 99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 100 "zifencei", "zihpm"; 101 reg = <3>; 102 i-cache-block-size = <64>; 103 i-cache-size = <65536>; 104 i-cache-sets = <512>; 105 d-cache-block-size = <64>; 106 d-cache-size = <65536>; 107 d-cache-sets = <512>; 108 next-level-cache = <&l2_cache>; 109 mmu-type = "riscv,sv39"; 110 111 cpu3_intc: interrupt-controller { 112 compatible = "riscv,cpu-intc"; 113 interrupt-controller; 114 #interrupt-cells = <1>; 115 }; 116 }; 117 118 l2_cache: l2-cache { 119 compatible = "cache"; 120 cache-block-size = <64>; 121 cache-level = <2>; 122 cache-size = <1048576>; 123 cache-sets = <1024>; 124 cache-unified; 125 }; 126 }; 127 128 pmu { 129 compatible = "riscv,pmu"; 130 riscv,event-to-mhpmcounters = 131 <0x00003 0x00003 0x0007fff8>, 132 <0x00004 0x00004 0x0007fff8>, 133 <0x00005 0x00005 0x0007fff8>, 134 <0x00006 0x00006 0x0007fff8>, 135 <0x00007 0x00007 0x0007fff8>, 136 <0x00008 0x00008 0x0007fff8>, 137 <0x00009 0x00009 0x0007fff8>, 138 <0x0000a 0x0000a 0x0007fff8>, 139 <0x10000 0x10000 0x0007fff8>, 140 <0x10001 0x10001 0x0007fff8>, 141 <0x10002 0x10002 0x0007fff8>, 142 <0x10003 0x10003 0x0007fff8>, 143 <0x10010 0x10010 0x0007fff8>, 144 <0x10011 0x10011 0x0007fff8>, 145 <0x10012 0x10012 0x0007fff8>, 146 <0x10013 0x10013 0x0007fff8>; 147 riscv,event-to-mhpmevent = 148 <0x00003 0x00000000 0x00000001>, 149 <0x00004 0x00000000 0x00000002>, 150 <0x00006 0x00000000 0x00000006>, 151 <0x00005 0x00000000 0x00000007>, 152 <0x00007 0x00000000 0x00000008>, 153 <0x00008 0x00000000 0x00000009>, 154 <0x00009 0x00000000 0x0000000a>, 155 <0x0000a 0x00000000 0x0000000b>, 156 <0x10000 0x00000000 0x0000000c>, 157 <0x10001 0x00000000 0x0000000d>, 158 <0x10002 0x00000000 0x0000000e>, 159 <0x10003 0x00000000 0x0000000f>, 160 <0x10010 0x00000000 0x00000010>, 161 <0x10011 0x00000000 0x00000011>, 162 <0x10012 0x00000000 0x00000012>, 163 <0x10013 0x00000000 0x00000013>; 164 riscv,raw-event-to-mhpmcounters = 165 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 205 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 206 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 207 }; 208 209 osc: oscillator { 210 compatible = "fixed-clock"; 211 clock-output-names = "osc_24m"; 212 #clock-cells = <0>; 213 }; 214 215 osc_32k: 32k-oscillator { 216 compatible = "fixed-clock"; 217 clock-output-names = "osc_32k"; 218 #clock-cells = <0>; 219 }; 220 221 aonsys_clk: clock-73728000 { 222 compatible = "fixed-clock"; 223 clock-frequency = <73728000>; 224 clock-output-names = "aonsys_clk"; 225 #clock-cells = <0>; 226 }; 227 228 stmmac_axi_config: stmmac-axi-config { 229 snps,wr_osr_lmt = <15>; 230 snps,rd_osr_lmt = <15>; 231 snps,blen = <0 0 64 32 0 0 0>; 232 }; 233 234 aon: aon { 235 compatible = "thead,th1520-aon"; 236 mboxes = <&mbox_910t 1>; 237 mbox-names = "aon"; 238 resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; 239 reset-names = "gpu-clkgen"; 240 #power-domain-cells = <1>; 241 }; 242 243 soc { 244 compatible = "simple-bus"; 245 interrupt-parent = <&plic>; 246 #address-cells = <2>; 247 #size-cells = <2>; 248 dma-noncoherent; 249 ranges; 250 251 plic: interrupt-controller@ffd8000000 { 252 compatible = "thead,th1520-plic", "thead,c900-plic"; 253 reg = <0xff 0xd8000000 0x0 0x01000000>; 254 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 255 <&cpu1_intc 11>, <&cpu1_intc 9>, 256 <&cpu2_intc 11>, <&cpu2_intc 9>, 257 <&cpu3_intc 11>, <&cpu3_intc 9>; 258 interrupt-controller; 259 #address-cells = <0>; 260 #interrupt-cells = <2>; 261 riscv,ndev = <240>; 262 }; 263 264 clint: timer@ffdc000000 { 265 compatible = "thead,th1520-clint", "thead,c900-clint"; 266 reg = <0xff 0xdc000000 0x0 0x00010000>; 267 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 268 <&cpu1_intc 3>, <&cpu1_intc 7>, 269 <&cpu2_intc 3>, <&cpu2_intc 7>, 270 <&cpu3_intc 3>, <&cpu3_intc 7>; 271 }; 272 273 spi0: spi@ffe700c000 { 274 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 275 reg = <0xff 0xe700c000 0x0 0x1000>; 276 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk CLK_SPI>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 uart0: serial@ffe7014000 { 284 compatible = "snps,dw-apb-uart"; 285 reg = <0xff 0xe7014000 0x0 0x100>; 286 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 288 clock-names = "baudclk", "apb_pclk"; 289 reg-shift = <2>; 290 reg-io-width = <4>; 291 status = "disabled"; 292 }; 293 294 gmac1: ethernet@ffe7060000 { 295 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 296 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 297 reg-names = "dwmac", "apb"; 298 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "macirq"; 300 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; 301 clock-names = "stmmaceth", "pclk"; 302 snps,pbl = <32>; 303 snps,fixed-burst; 304 snps,multicast-filter-bins = <64>; 305 snps,perfect-filter-entries = <32>; 306 snps,axi-config = <&stmmac_axi_config>; 307 status = "disabled"; 308 309 mdio1: mdio { 310 compatible = "snps,dwmac-mdio"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 }; 314 }; 315 316 gmac0: ethernet@ffe7070000 { 317 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 318 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 319 reg-names = "dwmac", "apb"; 320 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-names = "macirq"; 322 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; 323 clock-names = "stmmaceth", "pclk"; 324 snps,pbl = <32>; 325 snps,fixed-burst; 326 snps,multicast-filter-bins = <64>; 327 snps,perfect-filter-entries = <32>; 328 snps,axi-config = <&stmmac_axi_config>; 329 status = "disabled"; 330 331 mdio0: mdio { 332 compatible = "snps,dwmac-mdio"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 }; 336 }; 337 338 emmc: mmc@ffe7080000 { 339 compatible = "thead,th1520-dwcmshc"; 340 reg = <0xff 0xe7080000 0x0 0x10000>; 341 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clk CLK_EMMC_SDIO>; 343 clock-names = "core"; 344 status = "disabled"; 345 }; 346 347 sdio0: mmc@ffe7090000 { 348 compatible = "thead,th1520-dwcmshc"; 349 reg = <0xff 0xe7090000 0x0 0x10000>; 350 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clk CLK_EMMC_SDIO>; 352 clock-names = "core"; 353 status = "disabled"; 354 }; 355 356 sdio1: mmc@ffe70a0000 { 357 compatible = "thead,th1520-dwcmshc"; 358 reg = <0xff 0xe70a0000 0x0 0x10000>; 359 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk CLK_EMMC_SDIO>; 361 clock-names = "core"; 362 status = "disabled"; 363 }; 364 365 uart1: serial@ffe7f00000 { 366 compatible = "snps,dw-apb-uart"; 367 reg = <0xff 0xe7f00000 0x0 0x100>; 368 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 370 clock-names = "baudclk", "apb_pclk"; 371 reg-shift = <2>; 372 reg-io-width = <4>; 373 status = "disabled"; 374 }; 375 376 uart3: serial@ffe7f04000 { 377 compatible = "snps,dw-apb-uart"; 378 reg = <0xff 0xe7f04000 0x0 0x100>; 379 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 381 clock-names = "baudclk", "apb_pclk"; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 status = "disabled"; 385 }; 386 387 gpio@ffe7f34000 { 388 compatible = "snps,dw-apb-gpio"; 389 reg = <0xff 0xe7f34000 0x0 0x1000>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&clk CLK_GPIO2>; 393 clock-names = "bus"; 394 395 gpio2: gpio-controller@0 { 396 compatible = "snps,dw-apb-gpio-port"; 397 gpio-controller; 398 #gpio-cells = <2>; 399 ngpios = <32>; 400 gpio-ranges = <&padctrl0_apsys 0 0 32>; 401 reg = <0>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 405 }; 406 }; 407 408 gpio@ffe7f38000 { 409 compatible = "snps,dw-apb-gpio"; 410 reg = <0xff 0xe7f38000 0x0 0x1000>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 clocks = <&clk CLK_GPIO3>; 414 clock-names = "bus"; 415 416 gpio3: gpio-controller@0 { 417 compatible = "snps,dw-apb-gpio-port"; 418 gpio-controller; 419 #gpio-cells = <2>; 420 ngpios = <23>; 421 gpio-ranges = <&padctrl0_apsys 0 32 23>; 422 reg = <0>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 426 }; 427 }; 428 429 padctrl1_apsys: pinctrl@ffe7f3c000 { 430 compatible = "thead,th1520-pinctrl"; 431 reg = <0xff 0xe7f3c000 0x0 0x1000>; 432 clocks = <&clk CLK_PADCTRL1>; 433 thead,pad-group = <2>; 434 }; 435 436 gpio@ffec005000 { 437 compatible = "snps,dw-apb-gpio"; 438 reg = <0xff 0xec005000 0x0 0x1000>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&clk CLK_GPIO0>; 442 clock-names = "bus"; 443 444 gpio0: gpio-controller@0 { 445 compatible = "snps,dw-apb-gpio-port"; 446 gpio-controller; 447 #gpio-cells = <2>; 448 ngpios = <32>; 449 gpio-ranges = <&padctrl1_apsys 0 0 32>; 450 reg = <0>; 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 454 }; 455 }; 456 457 gpio@ffec006000 { 458 compatible = "snps,dw-apb-gpio"; 459 reg = <0xff 0xec006000 0x0 0x1000>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&clk CLK_GPIO1>; 463 clock-names = "bus"; 464 465 gpio1: gpio-controller@0 { 466 compatible = "snps,dw-apb-gpio-port"; 467 gpio-controller; 468 #gpio-cells = <2>; 469 ngpios = <31>; 470 gpio-ranges = <&padctrl1_apsys 0 32 31>; 471 reg = <0>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 475 }; 476 }; 477 478 padctrl0_apsys: pinctrl@ffec007000 { 479 compatible = "thead,th1520-pinctrl"; 480 reg = <0xff 0xec007000 0x0 0x1000>; 481 clocks = <&clk CLK_PADCTRL0>; 482 thead,pad-group = <3>; 483 }; 484 485 uart2: serial@ffec010000 { 486 compatible = "snps,dw-apb-uart"; 487 reg = <0xff 0xec010000 0x0 0x4000>; 488 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 490 clock-names = "baudclk", "apb_pclk"; 491 reg-shift = <2>; 492 reg-io-width = <4>; 493 status = "disabled"; 494 }; 495 496 clk: clock-controller@ffef010000 { 497 compatible = "thead,th1520-clk-ap"; 498 reg = <0xff 0xef010000 0x0 0x1000>; 499 clocks = <&osc>; 500 #clock-cells = <1>; 501 }; 502 503 rst: reset-controller@ffef528000 { 504 compatible = "thead,th1520-reset"; 505 reg = <0xff 0xef528000 0x0 0x4f>; 506 #reset-cells = <1>; 507 }; 508 509 clk_vo: clock-controller@ffef528050 { 510 compatible = "thead,th1520-clk-vo"; 511 reg = <0xff 0xef528050 0x0 0xfb0>; 512 clocks = <&clk CLK_VIDEO_PLL>; 513 #clock-cells = <1>; 514 }; 515 516 dmac0: dma-controller@ffefc00000 { 517 compatible = "snps,axi-dma-1.01a"; 518 reg = <0xff 0xefc00000 0x0 0x1000>; 519 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 521 clock-names = "core-clk", "cfgr-clk"; 522 #dma-cells = <1>; 523 dma-channels = <4>; 524 snps,block-size = <65536 65536 65536 65536>; 525 snps,priority = <0 1 2 3>; 526 snps,dma-masters = <1>; 527 snps,data-width = <4>; 528 snps,axi-max-burst-len = <16>; 529 status = "disabled"; 530 }; 531 532 timer0: timer@ffefc32000 { 533 compatible = "snps,dw-apb-timer"; 534 reg = <0xff 0xefc32000 0x0 0x14>; 535 clocks = <&clk CLK_PERI_APB_PCLK>; 536 clock-names = "timer"; 537 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 538 status = "disabled"; 539 }; 540 541 timer1: timer@ffefc32014 { 542 compatible = "snps,dw-apb-timer"; 543 reg = <0xff 0xefc32014 0x0 0x14>; 544 clocks = <&clk CLK_PERI_APB_PCLK>; 545 clock-names = "timer"; 546 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 547 status = "disabled"; 548 }; 549 550 timer2: timer@ffefc32028 { 551 compatible = "snps,dw-apb-timer"; 552 reg = <0xff 0xefc32028 0x0 0x14>; 553 clocks = <&clk CLK_PERI_APB_PCLK>; 554 clock-names = "timer"; 555 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 556 status = "disabled"; 557 }; 558 559 timer3: timer@ffefc3203c { 560 compatible = "snps,dw-apb-timer"; 561 reg = <0xff 0xefc3203c 0x0 0x14>; 562 clocks = <&clk CLK_PERI_APB_PCLK>; 563 clock-names = "timer"; 564 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 565 status = "disabled"; 566 }; 567 568 uart4: serial@fff7f08000 { 569 compatible = "snps,dw-apb-uart"; 570 reg = <0xff 0xf7f08000 0x0 0x4000>; 571 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 573 clock-names = "baudclk", "apb_pclk"; 574 reg-shift = <2>; 575 reg-io-width = <4>; 576 status = "disabled"; 577 }; 578 579 uart5: serial@fff7f0c000 { 580 compatible = "snps,dw-apb-uart"; 581 reg = <0xff 0xf7f0c000 0x0 0x4000>; 582 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 584 clock-names = "baudclk", "apb_pclk"; 585 reg-shift = <2>; 586 reg-io-width = <4>; 587 status = "disabled"; 588 }; 589 590 timer4: timer@ffffc33000 { 591 compatible = "snps,dw-apb-timer"; 592 reg = <0xff 0xffc33000 0x0 0x14>; 593 clocks = <&clk CLK_PERI_APB_PCLK>; 594 clock-names = "timer"; 595 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 596 status = "disabled"; 597 }; 598 599 timer5: timer@ffffc33014 { 600 compatible = "snps,dw-apb-timer"; 601 reg = <0xff 0xffc33014 0x0 0x14>; 602 clocks = <&clk CLK_PERI_APB_PCLK>; 603 clock-names = "timer"; 604 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 605 status = "disabled"; 606 }; 607 608 timer6: timer@ffffc33028 { 609 compatible = "snps,dw-apb-timer"; 610 reg = <0xff 0xffc33028 0x0 0x14>; 611 clocks = <&clk CLK_PERI_APB_PCLK>; 612 clock-names = "timer"; 613 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 614 status = "disabled"; 615 }; 616 617 timer7: timer@ffffc3303c { 618 compatible = "snps,dw-apb-timer"; 619 reg = <0xff 0xffc3303c 0x0 0x14>; 620 clocks = <&clk CLK_PERI_APB_PCLK>; 621 clock-names = "timer"; 622 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 623 status = "disabled"; 624 }; 625 626 mbox_910t: mailbox@ffffc38000 { 627 compatible = "thead,th1520-mbox"; 628 reg = <0xff 0xffc38000 0x0 0x6000>, 629 <0xff 0xffc40000 0x0 0x6000>, 630 <0xff 0xffc4c000 0x0 0x2000>, 631 <0xff 0xffc54000 0x0 0x2000>; 632 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; 633 clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, 634 <&clk CLK_MBOX3>; 635 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", 636 "clk-remote-icu2"; 637 interrupt-parent = <&plic>; 638 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 639 #mbox-cells = <1>; 640 }; 641 642 gpio@fffff41000 { 643 compatible = "snps,dw-apb-gpio"; 644 reg = <0xff 0xfff41000 0x0 0x1000>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 aogpio: gpio-controller@0 { 649 compatible = "snps,dw-apb-gpio-port"; 650 gpio-controller; 651 #gpio-cells = <2>; 652 ngpios = <16>; 653 gpio-ranges = <&padctrl_aosys 0 9 16>; 654 reg = <0>; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 }; 660 661 padctrl_aosys: pinctrl@fffff4a000 { 662 compatible = "thead,th1520-pinctrl"; 663 reg = <0xff 0xfff4a000 0x0 0x2000>; 664 clocks = <&aonsys_clk>; 665 thead,pad-group = <1>; 666 }; 667 668 pvt: pvt@fffff4e000 { 669 compatible = "moortec,mr75203"; 670 reg = <0xff 0xfff4e000 0x0 0x80>, 671 <0xff 0xfff4e080 0x0 0x100>, 672 <0xff 0xfff4e180 0x0 0x680>, 673 <0xff 0xfff4e800 0x0 0x600>; 674 reg-names = "common", "ts", "pd", "vm"; 675 clocks = <&aonsys_clk>; 676 #thermal-sensor-cells = <1>; 677 }; 678 679 gpio@fffff52000 { 680 compatible = "snps,dw-apb-gpio"; 681 reg = <0xff 0xfff52000 0x0 0x1000>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 685 gpio4: gpio-controller@0 { 686 compatible = "snps,dw-apb-gpio-port"; 687 gpio-controller; 688 #gpio-cells = <2>; 689 ngpios = <23>; 690 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 691 reg = <0>; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 695 }; 696 }; 697 }; 698}; 699