1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include "jh7110.dtsi" 9#include "jh7110-pinfunc.h" 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h> 13 14/ { 15 aliases { 16 ethernet0 = &gmac0; 17 i2c0 = &i2c0; 18 i2c2 = &i2c2; 19 i2c5 = &i2c5; 20 i2c6 = &i2c6; 21 mmc0 = &mmc0; 22 mmc1 = &mmc1; 23 serial0 = &uart0; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0x0 0x40000000 0x1 0x0>; 33 bootph-pre-ram; 34 }; 35 36 gpio-restart { 37 compatible = "gpio-restart"; 38 gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; 39 priority = <224>; 40 }; 41 42 leds { 43 compatible = "gpio-leds"; 44 45 led_status_power: led-0 { 46 gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>; 47 }; 48 }; 49 50 pwmdac_codec: audio-codec { 51 compatible = "linux,spdif-dit"; 52 #sound-dai-cells = <0>; 53 }; 54 55 sound { 56 compatible = "simple-audio-card"; 57 simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 simple-audio-card,dai-link@0 { 62 reg = <0>; 63 format = "left_j"; 64 bitclock-master = <&sndcpu0>; 65 frame-master = <&sndcpu0>; 66 67 sndcpu0: cpu { 68 sound-dai = <&pwmdac>; 69 }; 70 71 codec { 72 sound-dai = <&pwmdac_codec>; 73 }; 74 }; 75 }; 76}; 77 78&cpus { 79 timebase-frequency = <4000000>; 80}; 81 82&dvp_clk { 83 clock-frequency = <74250000>; 84}; 85 86&gmac0_rgmii_rxin { 87 clock-frequency = <125000000>; 88}; 89 90&gmac0_rmii_refin { 91 clock-frequency = <50000000>; 92}; 93 94&gmac1_rgmii_rxin { 95 clock-frequency = <125000000>; 96}; 97 98&gmac1_rmii_refin { 99 clock-frequency = <50000000>; 100}; 101 102&hdmitx0_pixelclk { 103 clock-frequency = <297000000>; 104}; 105 106&i2srx_bclk_ext { 107 clock-frequency = <12288000>; 108}; 109 110&i2srx_lrck_ext { 111 clock-frequency = <192000>; 112}; 113 114&i2stx_bclk_ext { 115 clock-frequency = <12288000>; 116}; 117 118&i2stx_lrck_ext { 119 clock-frequency = <192000>; 120}; 121 122&mclk_ext { 123 clock-frequency = <12288000>; 124}; 125 126&osc { 127 clock-frequency = <24000000>; 128}; 129 130&rtc_osc { 131 clock-frequency = <32768>; 132}; 133 134&tdm_ext { 135 clock-frequency = <49152000>; 136}; 137 138&camss { 139 assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, 140 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; 141 assigned-clock-rates = <49500000>, <198000000>; 142 143 ports { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 147 port@0 { 148 reg = <0>; 149 }; 150 151 port@1 { 152 reg = <1>; 153 154 camss_from_csi2rx: endpoint { 155 remote-endpoint = <&csi2rx_to_camss>; 156 }; 157 }; 158 }; 159}; 160 161&csi2rx { 162 assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; 163 assigned-clock-rates = <297000000>; 164 165 ports { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 169 port@0 { 170 reg = <0>; 171 172 /* remote MIPI sensor endpoint */ 173 }; 174 175 port@1 { 176 reg = <1>; 177 178 csi2rx_to_camss: endpoint { 179 remote-endpoint = <&camss_from_csi2rx>; 180 }; 181 }; 182 }; 183}; 184 185&gmac0 { 186 phy-handle = <&phy0>; 187 phy-mode = "rgmii-id"; 188 189 mdio { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 compatible = "snps,dwmac-mdio"; 193 194 phy0: ethernet-phy@0 { 195 reg = <0>; 196 }; 197 }; 198}; 199 200&i2c0 { 201 clock-frequency = <100000>; 202 i2c-sda-hold-time-ns = <300>; 203 i2c-sda-falling-time-ns = <510>; 204 i2c-scl-falling-time-ns = <510>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&i2c0_pins>; 207}; 208 209&i2c2 { 210 clock-frequency = <100000>; 211 i2c-sda-hold-time-ns = <300>; 212 i2c-sda-falling-time-ns = <510>; 213 i2c-scl-falling-time-ns = <510>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&i2c2_pins>; 216 status = "okay"; 217}; 218 219&i2c5 { 220 clock-frequency = <100000>; 221 i2c-sda-hold-time-ns = <300>; 222 i2c-sda-falling-time-ns = <510>; 223 i2c-scl-falling-time-ns = <510>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&i2c5_pins>; 226 status = "okay"; 227 228 axp15060: pmic@36 { 229 compatible = "x-powers,axp15060"; 230 reg = <0x36>; 231 interrupt-controller; 232 #interrupt-cells = <1>; 233 234 regulators { 235 vcc_3v3: dcdc1 { 236 regulator-boot-on; 237 regulator-always-on; 238 regulator-min-microvolt = <3300000>; 239 regulator-max-microvolt = <3300000>; 240 regulator-name = "vcc_3v3"; 241 }; 242 243 vdd_cpu: dcdc2 { 244 regulator-always-on; 245 regulator-min-microvolt = <500000>; 246 regulator-max-microvolt = <1540000>; 247 regulator-name = "vdd_cpu"; 248 }; 249 250 emmc_vdd: aldo4 { 251 regulator-boot-on; 252 regulator-always-on; 253 regulator-min-microvolt = <1800000>; 254 regulator-max-microvolt = <3300000>; 255 regulator-name = "emmc_vdd"; 256 }; 257 }; 258 }; 259 260 eeprom@50 { 261 compatible = "atmel,24c04"; 262 reg = <0x50>; 263 bootph-pre-ram; 264 pagesize = <16>; 265 }; 266}; 267 268&i2c6 { 269 clock-frequency = <100000>; 270 i2c-sda-hold-time-ns = <300>; 271 i2c-sda-falling-time-ns = <510>; 272 i2c-scl-falling-time-ns = <510>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&i2c6_pins>; 275 status = "okay"; 276}; 277 278&mmc0 { 279 max-frequency = <100000000>; 280 assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; 281 assigned-clock-rates = <50000000>; 282 bus-width = <8>; 283 bootph-pre-ram; 284 cap-mmc-highspeed; 285 mmc-ddr-1_8v; 286 mmc-hs200-1_8v; 287 cap-mmc-hw-reset; 288 post-power-on-delay-ms = <200>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&mmc0_pins>; 291 vmmc-supply = <&vcc_3v3>; 292 vqmmc-supply = <&emmc_vdd>; 293 status = "okay"; 294}; 295 296&mmc1 { 297 max-frequency = <100000000>; 298 assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; 299 assigned-clock-rates = <50000000>; 300 bus-width = <4>; 301 bootph-pre-ram; 302 no-sdio; 303 no-mmc; 304 cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; 305 disable-wp; 306 cap-sd-highspeed; 307 post-power-on-delay-ms = <200>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&mmc1_pins>; 310 status = "okay"; 311}; 312 313&pcie0 { 314 perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; 315 phys = <&pciephy0>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pcie0_pins>; 318}; 319 320&pcie1 { 321 perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; 322 phys = <&pciephy1>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pcie1_pins>; 325}; 326 327&pwmdac { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pwmdac_pins>; 330}; 331 332&qspi { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 status = "okay"; 336 337 nor_flash: flash@0 { 338 compatible = "jedec,spi-nor"; 339 reg = <0>; 340 bootph-pre-ram; 341 cdns,read-delay = <2>; 342 spi-max-frequency = <100000000>; 343 cdns,tshsl-ns = <1>; 344 cdns,tsd2d-ns = <1>; 345 cdns,tchsh-ns = <1>; 346 cdns,tslch-ns = <1>; 347 348 partitions { 349 compatible = "fixed-partitions"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 353 spl@0 { 354 reg = <0x0 0xf0000>; 355 }; 356 uboot-env@f0000 { 357 reg = <0xf0000 0x10000>; 358 }; 359 uboot@100000 { 360 reg = <0x100000 0xf00000>; 361 }; 362 }; 363 }; 364}; 365 366&pwm { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pwm_pins>; 369}; 370 371&spi0 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi0_pins>; 374}; 375 376&syscrg { 377 assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, 378 <&syscrg JH7110_SYSCLK_BUS_ROOT>, 379 <&syscrg JH7110_SYSCLK_PERH_ROOT>, 380 <&syscrg JH7110_SYSCLK_QSPI_REF>, 381 <&syscrg JH7110_SYSCLK_CPU_CORE>, 382 <&pllclk JH7110_PLLCLK_PLL0_OUT>; 383 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, 384 <&pllclk JH7110_PLLCLK_PLL2_OUT>, 385 <&pllclk JH7110_PLLCLK_PLL2_OUT>, 386 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; 387 assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>; 388}; 389 390&sysgpio { 391 i2c0_pins: i2c0-0 { 392 i2c-pins { 393 pinmux = <GPIOMUX(57, GPOUT_LOW, 394 GPOEN_SYS_I2C0_CLK, 395 GPI_SYS_I2C0_CLK)>, 396 <GPIOMUX(58, GPOUT_LOW, 397 GPOEN_SYS_I2C0_DATA, 398 GPI_SYS_I2C0_DATA)>; 399 bias-disable; /* external pull-up */ 400 input-enable; 401 input-schmitt-enable; 402 }; 403 }; 404 405 i2c2_pins: i2c2-0 { 406 i2c-pins { 407 pinmux = <GPIOMUX(3, GPOUT_LOW, 408 GPOEN_SYS_I2C2_CLK, 409 GPI_SYS_I2C2_CLK)>, 410 <GPIOMUX(2, GPOUT_LOW, 411 GPOEN_SYS_I2C2_DATA, 412 GPI_SYS_I2C2_DATA)>; 413 bias-disable; /* external pull-up */ 414 input-enable; 415 input-schmitt-enable; 416 }; 417 }; 418 419 i2c5_pins: i2c5-0 { 420 bootph-pre-ram; 421 422 i2c-pins { 423 pinmux = <GPIOMUX(19, GPOUT_LOW, 424 GPOEN_SYS_I2C5_CLK, 425 GPI_SYS_I2C5_CLK)>, 426 <GPIOMUX(20, GPOUT_LOW, 427 GPOEN_SYS_I2C5_DATA, 428 GPI_SYS_I2C5_DATA)>; 429 bias-disable; /* external pull-up */ 430 bootph-pre-ram; 431 input-enable; 432 input-schmitt-enable; 433 }; 434 }; 435 436 i2c6_pins: i2c6-0 { 437 i2c-pins { 438 pinmux = <GPIOMUX(16, GPOUT_LOW, 439 GPOEN_SYS_I2C6_CLK, 440 GPI_SYS_I2C6_CLK)>, 441 <GPIOMUX(17, GPOUT_LOW, 442 GPOEN_SYS_I2C6_DATA, 443 GPI_SYS_I2C6_DATA)>; 444 bias-disable; /* external pull-up */ 445 input-enable; 446 input-schmitt-enable; 447 }; 448 }; 449 450 mmc0_pins: mmc0-0 { 451 rst-pins { 452 pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, 453 GPOEN_ENABLE, 454 GPI_NONE)>; 455 bias-pull-up; 456 drive-strength = <12>; 457 input-disable; 458 input-schmitt-disable; 459 slew-rate = <0>; 460 }; 461 462 mmc-pins { 463 pinmux = <PINMUX(PAD_SD0_CLK, 0)>, 464 <PINMUX(PAD_SD0_CMD, 0)>, 465 <PINMUX(PAD_SD0_DATA0, 0)>, 466 <PINMUX(PAD_SD0_DATA1, 0)>, 467 <PINMUX(PAD_SD0_DATA2, 0)>, 468 <PINMUX(PAD_SD0_DATA3, 0)>, 469 <PINMUX(PAD_SD0_DATA4, 0)>, 470 <PINMUX(PAD_SD0_DATA5, 0)>, 471 <PINMUX(PAD_SD0_DATA6, 0)>, 472 <PINMUX(PAD_SD0_DATA7, 0)>; 473 bias-pull-up; 474 drive-strength = <12>; 475 input-enable; 476 }; 477 }; 478 479 mmc1_pins: mmc1-0 { 480 clk-pins { 481 pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, 482 GPOEN_ENABLE, 483 GPI_NONE)>; 484 bias-pull-up; 485 drive-strength = <12>; 486 input-disable; 487 input-schmitt-disable; 488 slew-rate = <0>; 489 }; 490 491 mmc-pins { 492 pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, 493 GPOEN_SYS_SDIO1_CMD, 494 GPI_SYS_SDIO1_CMD)>, 495 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, 496 GPOEN_SYS_SDIO1_DATA0, 497 GPI_SYS_SDIO1_DATA0)>, 498 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, 499 GPOEN_SYS_SDIO1_DATA1, 500 GPI_SYS_SDIO1_DATA1)>, 501 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, 502 GPOEN_SYS_SDIO1_DATA2, 503 GPI_SYS_SDIO1_DATA2)>, 504 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, 505 GPOEN_SYS_SDIO1_DATA3, 506 GPI_SYS_SDIO1_DATA3)>; 507 bias-pull-up; 508 drive-strength = <12>; 509 input-enable; 510 input-schmitt-enable; 511 slew-rate = <0>; 512 }; 513 }; 514 515 pcie0_pins: pcie0-0 { 516 clkreq-pins { 517 pinmux = <GPIOMUX(27, GPOUT_LOW, 518 GPOEN_DISABLE, 519 GPI_NONE)>; 520 bias-pull-down; 521 drive-strength = <2>; 522 input-enable; 523 input-schmitt-disable; 524 slew-rate = <0>; 525 }; 526 527 wake-pins { 528 pinmux = <GPIOMUX(32, GPOUT_LOW, 529 GPOEN_DISABLE, 530 GPI_NONE)>; 531 bias-pull-up; 532 drive-strength = <2>; 533 input-enable; 534 input-schmitt-disable; 535 slew-rate = <0>; 536 }; 537 }; 538 539 pcie1_pins: pcie1-0 { 540 clkreq-pins { 541 pinmux = <GPIOMUX(29, GPOUT_LOW, 542 GPOEN_DISABLE, 543 GPI_NONE)>; 544 bias-pull-down; 545 drive-strength = <2>; 546 input-enable; 547 input-schmitt-disable; 548 slew-rate = <0>; 549 }; 550 551 wake-pins { 552 pinmux = <GPIOMUX(21, GPOUT_LOW, 553 GPOEN_DISABLE, 554 GPI_NONE)>; 555 bias-pull-up; 556 drive-strength = <2>; 557 input-enable; 558 input-schmitt-disable; 559 slew-rate = <0>; 560 }; 561 }; 562 563 pwmdac_pins: pwmdac-0 { 564 pwmdac-pins { 565 pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, 566 GPOEN_ENABLE, 567 GPI_NONE)>, 568 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT, 569 GPOEN_ENABLE, 570 GPI_NONE)>; 571 bias-disable; 572 drive-strength = <2>; 573 input-disable; 574 input-schmitt-disable; 575 slew-rate = <0>; 576 }; 577 }; 578 579 pwm_pins: pwm-0 { 580 pwm-pins { 581 pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0, 582 GPOEN_SYS_PWM0_CHANNEL0, 583 GPI_NONE)>, 584 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1, 585 GPOEN_SYS_PWM0_CHANNEL1, 586 GPI_NONE)>; 587 bias-disable; 588 drive-strength = <12>; 589 input-disable; 590 input-schmitt-disable; 591 slew-rate = <0>; 592 }; 593 }; 594 595 spi0_pins: spi0-0 { 596 mosi-pins { 597 pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, 598 GPOEN_ENABLE, 599 GPI_NONE)>; 600 bias-disable; 601 input-disable; 602 input-schmitt-disable; 603 }; 604 605 miso-pins { 606 pinmux = <GPIOMUX(53, GPOUT_LOW, 607 GPOEN_DISABLE, 608 GPI_SYS_SPI0_RXD)>; 609 bias-pull-up; 610 input-enable; 611 input-schmitt-enable; 612 }; 613 614 sck-pins { 615 pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, 616 GPOEN_ENABLE, 617 GPI_SYS_SPI0_CLK)>; 618 bias-disable; 619 input-disable; 620 input-schmitt-disable; 621 }; 622 623 ss-pins { 624 pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, 625 GPOEN_ENABLE, 626 GPI_SYS_SPI0_FSS)>; 627 bias-disable; 628 input-disable; 629 input-schmitt-disable; 630 }; 631 }; 632 633 uart0_pins: uart0-0 { 634 tx-pins { 635 pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, 636 GPOEN_ENABLE, 637 GPI_NONE)>; 638 bias-disable; 639 drive-strength = <12>; 640 input-disable; 641 input-schmitt-disable; 642 slew-rate = <0>; 643 }; 644 645 rx-pins { 646 pinmux = <GPIOMUX(6, GPOUT_LOW, 647 GPOEN_DISABLE, 648 GPI_SYS_UART0_RX)>; 649 bias-disable; /* external pull-up */ 650 drive-strength = <2>; 651 input-enable; 652 input-schmitt-enable; 653 slew-rate = <0>; 654 }; 655 }; 656}; 657 658&uart0 { 659 bootph-pre-ram; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&uart0_pins>; 662 status = "okay"; 663}; 664 665&U74_1 { 666 cpu-supply = <&vdd_cpu>; 667}; 668 669&U74_2 { 670 cpu-supply = <&vdd_cpu>; 671}; 672 673&U74_3 { 674 cpu-supply = <&vdd_cpu>; 675}; 676 677&U74_4 { 678 cpu-supply = <&vdd_cpu>; 679}; 680