xref: /linux/arch/riscv/boot/dts/starfive/jh7110-common.dtsi (revision 55a42f78ffd386e01a5404419f8c5ded7db70a21) 
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include "jh7110.dtsi"
9#include "jh7110-pinfunc.h"
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
13
14/ {
15	aliases {
16		ethernet0 = &gmac0;
17		i2c0 = &i2c0;
18		i2c2 = &i2c2;
19		i2c5 = &i2c5;
20		i2c6 = &i2c6;
21		mmc0 = &mmc0;
22		mmc1 = &mmc1;
23		serial0 = &uart0;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0x1 0x0>;
33		bootph-pre-ram;
34	};
35
36	gpio-restart {
37		compatible = "gpio-restart";
38		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
39		priority = <224>;
40	};
41
42	leds {
43		compatible = "gpio-leds";
44
45		led_status_power: led-0 {
46			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
47		};
48	};
49
50	pwmdac_codec: audio-codec {
51		compatible = "linux,spdif-dit";
52		#sound-dai-cells = <0>;
53	};
54
55	sound {
56		compatible = "simple-audio-card";
57		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
58		#address-cells = <1>;
59		#size-cells = <0>;
60
61		simple-audio-card,dai-link@0 {
62			reg = <0>;
63			format = "left_j";
64			bitclock-master = <&sndcpu0>;
65			frame-master = <&sndcpu0>;
66
67			sndcpu0: cpu {
68				sound-dai = <&pwmdac>;
69			};
70
71			codec {
72				sound-dai = <&pwmdac_codec>;
73			};
74		};
75	};
76};
77
78&cpus {
79	timebase-frequency = <4000000>;
80};
81
82&dvp_clk {
83	clock-frequency = <74250000>;
84};
85
86&gmac0_rgmii_rxin {
87	clock-frequency = <125000000>;
88};
89
90&gmac0_rmii_refin {
91	clock-frequency = <50000000>;
92};
93
94&gmac1_rgmii_rxin {
95	clock-frequency = <125000000>;
96};
97
98&gmac1_rmii_refin {
99	clock-frequency = <50000000>;
100};
101
102&hdmitx0_pixelclk {
103	clock-frequency = <297000000>;
104};
105
106&i2srx_bclk_ext {
107	clock-frequency = <12288000>;
108};
109
110&i2srx_lrck_ext {
111	clock-frequency = <192000>;
112};
113
114&i2stx_bclk_ext {
115	clock-frequency = <12288000>;
116};
117
118&i2stx_lrck_ext {
119	clock-frequency = <192000>;
120};
121
122&mclk_ext {
123	clock-frequency = <12288000>;
124};
125
126&osc {
127	clock-frequency = <24000000>;
128};
129
130&rtc_osc {
131	clock-frequency = <32768>;
132};
133
134&tdm_ext {
135	clock-frequency = <49152000>;
136};
137
138&camss {
139	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
140			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
141	assigned-clock-rates = <49500000>, <198000000>;
142
143	ports {
144		#address-cells = <1>;
145		#size-cells = <0>;
146
147		port@0 {
148			reg = <0>;
149		};
150
151		port@1 {
152			reg = <1>;
153
154			camss_from_csi2rx: endpoint {
155				remote-endpoint = <&csi2rx_to_camss>;
156			};
157		};
158	};
159};
160
161&csi2rx {
162	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
163	assigned-clock-rates = <297000000>;
164
165	ports {
166		#address-cells = <1>;
167		#size-cells = <0>;
168
169		port@0 {
170			reg = <0>;
171
172			/* remote MIPI sensor endpoint */
173		};
174
175		port@1 {
176			reg = <1>;
177
178			csi2rx_to_camss: endpoint {
179				remote-endpoint = <&camss_from_csi2rx>;
180			};
181		};
182	};
183};
184
185&gmac0 {
186	phy-handle = <&phy0>;
187	phy-mode = "rgmii-id";
188
189	mdio {
190		#address-cells = <1>;
191		#size-cells = <0>;
192		compatible = "snps,dwmac-mdio";
193
194		phy0: ethernet-phy@0 {
195			reg = <0>;
196		};
197	};
198};
199
200&i2c0 {
201	clock-frequency = <100000>;
202	i2c-sda-hold-time-ns = <300>;
203	i2c-sda-falling-time-ns = <510>;
204	i2c-scl-falling-time-ns = <510>;
205	pinctrl-names = "default";
206	pinctrl-0 = <&i2c0_pins>;
207};
208
209&i2c2 {
210	clock-frequency = <100000>;
211	i2c-sda-hold-time-ns = <300>;
212	i2c-sda-falling-time-ns = <510>;
213	i2c-scl-falling-time-ns = <510>;
214	pinctrl-names = "default";
215	pinctrl-0 = <&i2c2_pins>;
216	status = "okay";
217};
218
219&i2c5 {
220	clock-frequency = <100000>;
221	i2c-sda-hold-time-ns = <300>;
222	i2c-sda-falling-time-ns = <510>;
223	i2c-scl-falling-time-ns = <510>;
224	pinctrl-names = "default";
225	pinctrl-0 = <&i2c5_pins>;
226	status = "okay";
227
228	axp15060: pmic@36 {
229		compatible = "x-powers,axp15060";
230		reg = <0x36>;
231		interrupt-controller;
232		#interrupt-cells = <1>;
233
234		regulators {
235			vcc_3v3: dcdc1 {
236				regulator-boot-on;
237				regulator-always-on;
238				regulator-min-microvolt = <3300000>;
239				regulator-max-microvolt = <3300000>;
240				regulator-name = "vcc_3v3";
241			};
242
243			vdd_cpu: dcdc2 {
244				regulator-always-on;
245				regulator-min-microvolt = <500000>;
246				regulator-max-microvolt = <1540000>;
247				regulator-name = "vdd_cpu";
248			};
249
250			emmc_vdd: aldo4 {
251				regulator-boot-on;
252				regulator-always-on;
253				regulator-min-microvolt = <1800000>;
254				regulator-max-microvolt = <3300000>;
255				regulator-name = "emmc_vdd";
256			};
257		};
258	};
259
260	eeprom@50 {
261		compatible = "atmel,24c04";
262		reg = <0x50>;
263		bootph-pre-ram;
264		pagesize = <16>;
265	};
266};
267
268&i2c6 {
269	clock-frequency = <100000>;
270	i2c-sda-hold-time-ns = <300>;
271	i2c-sda-falling-time-ns = <510>;
272	i2c-scl-falling-time-ns = <510>;
273	pinctrl-names = "default";
274	pinctrl-0 = <&i2c6_pins>;
275	status = "okay";
276};
277
278&mmc0 {
279	max-frequency = <100000000>;
280	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
281	assigned-clock-rates = <50000000>;
282	bus-width = <8>;
283	bootph-pre-ram;
284	cap-mmc-highspeed;
285	mmc-ddr-1_8v;
286	mmc-hs200-1_8v;
287	cap-mmc-hw-reset;
288	pinctrl-names = "default";
289	pinctrl-0 = <&mmc0_pins>;
290	vmmc-supply = <&vcc_3v3>;
291	vqmmc-supply = <&emmc_vdd>;
292	status = "okay";
293};
294
295&mmc1 {
296	max-frequency = <100000000>;
297	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
298	assigned-clock-rates = <50000000>;
299	bus-width = <4>;
300	bootph-pre-ram;
301	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
302	disable-wp;
303	cap-sd-highspeed;
304	pinctrl-names = "default";
305	pinctrl-0 = <&mmc1_pins>;
306	status = "okay";
307};
308
309&pcie0 {
310	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
311	phys = <&pciephy0>;
312	pinctrl-names = "default";
313	pinctrl-0 = <&pcie0_pins>;
314};
315
316&pcie1 {
317	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
318	phys = <&pciephy1>;
319	pinctrl-names = "default";
320	pinctrl-0 = <&pcie1_pins>;
321};
322
323&pwmdac {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pwmdac_pins>;
326};
327
328&qspi {
329	#address-cells = <1>;
330	#size-cells = <0>;
331	status = "okay";
332
333	nor_flash: flash@0 {
334		compatible = "jedec,spi-nor";
335		reg = <0>;
336		bootph-pre-ram;
337		cdns,read-delay = <2>;
338		spi-max-frequency = <100000000>;
339		cdns,tshsl-ns = <1>;
340		cdns,tsd2d-ns = <1>;
341		cdns,tchsh-ns = <1>;
342		cdns,tslch-ns = <1>;
343
344		partitions {
345			compatible = "fixed-partitions";
346			#address-cells = <1>;
347			#size-cells = <1>;
348
349			spl@0 {
350				reg = <0x0 0xf0000>;
351			};
352			uboot-env@f0000 {
353				reg = <0xf0000 0x10000>;
354			};
355			uboot@100000 {
356				reg = <0x100000 0xf00000>;
357			};
358		};
359	};
360};
361
362&pwm {
363	pinctrl-names = "default";
364	pinctrl-0 = <&pwm_pins>;
365};
366
367&spi0 {
368	pinctrl-names = "default";
369	pinctrl-0 = <&spi0_pins>;
370};
371
372&syscrg {
373	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
374			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
375			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
376			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
377			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
378			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
379	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
380				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
381				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
382				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
383	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
384};
385
386&sysgpio {
387	i2c0_pins: i2c0-0 {
388		i2c-pins {
389			pinmux = <GPIOMUX(57, GPOUT_LOW,
390					      GPOEN_SYS_I2C0_CLK,
391					      GPI_SYS_I2C0_CLK)>,
392				 <GPIOMUX(58, GPOUT_LOW,
393					      GPOEN_SYS_I2C0_DATA,
394					      GPI_SYS_I2C0_DATA)>;
395			bias-disable; /* external pull-up */
396			input-enable;
397			input-schmitt-enable;
398		};
399	};
400
401	i2c2_pins: i2c2-0 {
402		i2c-pins {
403			pinmux = <GPIOMUX(3, GPOUT_LOW,
404					     GPOEN_SYS_I2C2_CLK,
405					     GPI_SYS_I2C2_CLK)>,
406				 <GPIOMUX(2, GPOUT_LOW,
407					     GPOEN_SYS_I2C2_DATA,
408					     GPI_SYS_I2C2_DATA)>;
409			bias-disable; /* external pull-up */
410			input-enable;
411			input-schmitt-enable;
412		};
413	};
414
415	i2c5_pins: i2c5-0 {
416		bootph-pre-ram;
417
418		i2c-pins {
419			pinmux = <GPIOMUX(19, GPOUT_LOW,
420					      GPOEN_SYS_I2C5_CLK,
421					      GPI_SYS_I2C5_CLK)>,
422				 <GPIOMUX(20, GPOUT_LOW,
423					      GPOEN_SYS_I2C5_DATA,
424					      GPI_SYS_I2C5_DATA)>;
425			bias-disable; /* external pull-up */
426			bootph-pre-ram;
427			input-enable;
428			input-schmitt-enable;
429		};
430	};
431
432	i2c6_pins: i2c6-0 {
433		i2c-pins {
434			pinmux = <GPIOMUX(16, GPOUT_LOW,
435					      GPOEN_SYS_I2C6_CLK,
436					      GPI_SYS_I2C6_CLK)>,
437				 <GPIOMUX(17, GPOUT_LOW,
438					      GPOEN_SYS_I2C6_DATA,
439					      GPI_SYS_I2C6_DATA)>;
440			bias-disable; /* external pull-up */
441			input-enable;
442			input-schmitt-enable;
443		};
444	};
445
446	mmc0_pins: mmc0-0 {
447		 rst-pins {
448			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
449					      GPOEN_ENABLE,
450					      GPI_NONE)>;
451			bias-pull-up;
452			drive-strength = <12>;
453			input-disable;
454			input-schmitt-disable;
455			slew-rate = <0>;
456		};
457
458		mmc-pins {
459			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
460				 <PINMUX(PAD_SD0_CMD, 0)>,
461				 <PINMUX(PAD_SD0_DATA0, 0)>,
462				 <PINMUX(PAD_SD0_DATA1, 0)>,
463				 <PINMUX(PAD_SD0_DATA2, 0)>,
464				 <PINMUX(PAD_SD0_DATA3, 0)>,
465				 <PINMUX(PAD_SD0_DATA4, 0)>,
466				 <PINMUX(PAD_SD0_DATA5, 0)>,
467				 <PINMUX(PAD_SD0_DATA6, 0)>,
468				 <PINMUX(PAD_SD0_DATA7, 0)>;
469			bias-pull-up;
470			drive-strength = <12>;
471			input-enable;
472		};
473	};
474
475	mmc1_pins: mmc1-0 {
476		clk-pins {
477			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
478					      GPOEN_ENABLE,
479					      GPI_NONE)>;
480			bias-pull-up;
481			drive-strength = <12>;
482			input-disable;
483			input-schmitt-disable;
484			slew-rate = <0>;
485		};
486
487		mmc-pins {
488			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
489					     GPOEN_SYS_SDIO1_CMD,
490					     GPI_SYS_SDIO1_CMD)>,
491				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
492					      GPOEN_SYS_SDIO1_DATA0,
493					      GPI_SYS_SDIO1_DATA0)>,
494				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
495					      GPOEN_SYS_SDIO1_DATA1,
496					      GPI_SYS_SDIO1_DATA1)>,
497				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
498					     GPOEN_SYS_SDIO1_DATA2,
499					     GPI_SYS_SDIO1_DATA2)>,
500				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
501					     GPOEN_SYS_SDIO1_DATA3,
502					     GPI_SYS_SDIO1_DATA3)>;
503			bias-pull-up;
504			drive-strength = <12>;
505			input-enable;
506			input-schmitt-enable;
507			slew-rate = <0>;
508		};
509	};
510
511	pcie0_pins: pcie0-0 {
512		clkreq-pins {
513			pinmux = <GPIOMUX(27, GPOUT_LOW,
514					      GPOEN_DISABLE,
515					      GPI_NONE)>;
516			bias-pull-down;
517			drive-strength = <2>;
518			input-enable;
519			input-schmitt-disable;
520			slew-rate = <0>;
521		};
522
523		wake-pins {
524			pinmux = <GPIOMUX(32, GPOUT_LOW,
525					      GPOEN_DISABLE,
526					      GPI_NONE)>;
527			bias-pull-up;
528			drive-strength = <2>;
529			input-enable;
530			input-schmitt-disable;
531			slew-rate = <0>;
532		};
533	};
534
535	pcie1_pins: pcie1-0 {
536		clkreq-pins {
537			pinmux = <GPIOMUX(29, GPOUT_LOW,
538					      GPOEN_DISABLE,
539					      GPI_NONE)>;
540			bias-pull-down;
541			drive-strength = <2>;
542			input-enable;
543			input-schmitt-disable;
544			slew-rate = <0>;
545		};
546
547		wake-pins {
548			pinmux = <GPIOMUX(21, GPOUT_LOW,
549				      GPOEN_DISABLE,
550					      GPI_NONE)>;
551			bias-pull-up;
552			drive-strength = <2>;
553			input-enable;
554			input-schmitt-disable;
555			slew-rate = <0>;
556		};
557	};
558
559	pwmdac_pins: pwmdac-0 {
560		pwmdac-pins {
561			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
562					      GPOEN_ENABLE,
563					      GPI_NONE)>,
564				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
565					      GPOEN_ENABLE,
566					      GPI_NONE)>;
567			bias-disable;
568			drive-strength = <2>;
569			input-disable;
570			input-schmitt-disable;
571			slew-rate = <0>;
572		};
573	};
574
575	pwm_pins: pwm-0 {
576		pwm-pins {
577			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
578					      GPOEN_SYS_PWM0_CHANNEL0,
579					      GPI_NONE)>,
580				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
581					      GPOEN_SYS_PWM0_CHANNEL1,
582					      GPI_NONE)>;
583			bias-disable;
584			drive-strength = <12>;
585			input-disable;
586			input-schmitt-disable;
587			slew-rate = <0>;
588		};
589	};
590
591	spi0_pins: spi0-0 {
592		mosi-pins {
593			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
594					      GPOEN_ENABLE,
595					      GPI_NONE)>;
596			bias-disable;
597			input-disable;
598			input-schmitt-disable;
599		};
600
601		miso-pins {
602			pinmux = <GPIOMUX(53, GPOUT_LOW,
603					      GPOEN_DISABLE,
604					      GPI_SYS_SPI0_RXD)>;
605			bias-pull-up;
606			input-enable;
607			input-schmitt-enable;
608		};
609
610		sck-pins {
611			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
612					      GPOEN_ENABLE,
613					      GPI_SYS_SPI0_CLK)>;
614			bias-disable;
615			input-disable;
616			input-schmitt-disable;
617		};
618
619		ss-pins {
620			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
621					      GPOEN_ENABLE,
622					      GPI_SYS_SPI0_FSS)>;
623			bias-disable;
624			input-disable;
625			input-schmitt-disable;
626		};
627	};
628
629	uart0_pins: uart0-0 {
630		tx-pins {
631			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
632					     GPOEN_ENABLE,
633					     GPI_NONE)>;
634			bias-disable;
635			drive-strength = <12>;
636			input-disable;
637			input-schmitt-disable;
638			slew-rate = <0>;
639		};
640
641		rx-pins {
642			pinmux = <GPIOMUX(6, GPOUT_LOW,
643					     GPOEN_DISABLE,
644					     GPI_SYS_UART0_RX)>;
645			bias-disable; /* external pull-up */
646			drive-strength = <2>;
647			input-enable;
648			input-schmitt-enable;
649			slew-rate = <0>;
650		};
651	};
652};
653
654&uart0 {
655	bootph-pre-ram;
656	pinctrl-names = "default";
657	pinctrl-0 = <&uart0_pins>;
658	status = "okay";
659};
660
661&U74_1 {
662	cpu-supply = <&vdd_cpu>;
663};
664
665&U74_2 {
666	cpu-supply = <&vdd_cpu>;
667};
668
669&U74_3 {
670	cpu-supply = <&vdd_cpu>;
671};
672
673&U74_4 {
674	cpu-supply = <&vdd_cpu>;
675};
676