1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include "jh7110.dtsi" 9#include "jh7110-pinfunc.h" 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h> 12 13/ { 14 aliases { 15 ethernet0 = &gmac0; 16 i2c0 = &i2c0; 17 i2c2 = &i2c2; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0x0 0x40000000 0x1 0x0>; 32 bootph-pre-ram; 33 }; 34 35 gpio-restart { 36 compatible = "gpio-restart"; 37 gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; 38 priority = <224>; 39 }; 40 41 pwmdac_codec: audio-codec { 42 compatible = "linux,spdif-dit"; 43 #sound-dai-cells = <0>; 44 }; 45 46 sound { 47 compatible = "simple-audio-card"; 48 simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 simple-audio-card,dai-link@0 { 53 reg = <0>; 54 format = "left_j"; 55 bitclock-master = <&sndcpu0>; 56 frame-master = <&sndcpu0>; 57 58 sndcpu0: cpu { 59 sound-dai = <&pwmdac>; 60 }; 61 62 codec { 63 sound-dai = <&pwmdac_codec>; 64 }; 65 }; 66 }; 67}; 68 69&cpus { 70 timebase-frequency = <4000000>; 71}; 72 73&dvp_clk { 74 clock-frequency = <74250000>; 75}; 76 77&gmac0_rgmii_rxin { 78 clock-frequency = <125000000>; 79}; 80 81&gmac0_rmii_refin { 82 clock-frequency = <50000000>; 83}; 84 85&gmac1_rgmii_rxin { 86 clock-frequency = <125000000>; 87}; 88 89&gmac1_rmii_refin { 90 clock-frequency = <50000000>; 91}; 92 93&hdmitx0_pixelclk { 94 clock-frequency = <297000000>; 95}; 96 97&i2srx_bclk_ext { 98 clock-frequency = <12288000>; 99}; 100 101&i2srx_lrck_ext { 102 clock-frequency = <192000>; 103}; 104 105&i2stx_bclk_ext { 106 clock-frequency = <12288000>; 107}; 108 109&i2stx_lrck_ext { 110 clock-frequency = <192000>; 111}; 112 113&mclk_ext { 114 clock-frequency = <12288000>; 115}; 116 117&osc { 118 clock-frequency = <24000000>; 119}; 120 121&rtc_osc { 122 clock-frequency = <32768>; 123}; 124 125&tdm_ext { 126 clock-frequency = <49152000>; 127}; 128 129&camss { 130 assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, 131 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; 132 assigned-clock-rates = <49500000>, <198000000>; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 port@0 { 139 reg = <0>; 140 }; 141 142 port@1 { 143 reg = <1>; 144 145 camss_from_csi2rx: endpoint { 146 remote-endpoint = <&csi2rx_to_camss>; 147 }; 148 }; 149 }; 150}; 151 152&csi2rx { 153 assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; 154 assigned-clock-rates = <297000000>; 155 156 ports { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 160 port@0 { 161 reg = <0>; 162 163 /* remote MIPI sensor endpoint */ 164 }; 165 166 port@1 { 167 reg = <1>; 168 169 csi2rx_to_camss: endpoint { 170 remote-endpoint = <&camss_from_csi2rx>; 171 }; 172 }; 173 }; 174}; 175 176&gmac0 { 177 phy-handle = <&phy0>; 178 phy-mode = "rgmii-id"; 179 180 mdio { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 compatible = "snps,dwmac-mdio"; 184 185 phy0: ethernet-phy@0 { 186 reg = <0>; 187 }; 188 }; 189}; 190 191&i2c0 { 192 clock-frequency = <100000>; 193 i2c-sda-hold-time-ns = <300>; 194 i2c-sda-falling-time-ns = <510>; 195 i2c-scl-falling-time-ns = <510>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&i2c0_pins>; 198}; 199 200&i2c2 { 201 clock-frequency = <100000>; 202 i2c-sda-hold-time-ns = <300>; 203 i2c-sda-falling-time-ns = <510>; 204 i2c-scl-falling-time-ns = <510>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&i2c2_pins>; 207 status = "okay"; 208}; 209 210&i2c5 { 211 clock-frequency = <100000>; 212 i2c-sda-hold-time-ns = <300>; 213 i2c-sda-falling-time-ns = <510>; 214 i2c-scl-falling-time-ns = <510>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&i2c5_pins>; 217 status = "okay"; 218 219 axp15060: pmic@36 { 220 compatible = "x-powers,axp15060"; 221 reg = <0x36>; 222 interrupt-controller; 223 #interrupt-cells = <1>; 224 225 regulators { 226 vcc_3v3: dcdc1 { 227 regulator-boot-on; 228 regulator-always-on; 229 regulator-min-microvolt = <3300000>; 230 regulator-max-microvolt = <3300000>; 231 regulator-name = "vcc_3v3"; 232 }; 233 234 vdd_cpu: dcdc2 { 235 regulator-always-on; 236 regulator-min-microvolt = <500000>; 237 regulator-max-microvolt = <1540000>; 238 regulator-name = "vdd_cpu"; 239 }; 240 241 emmc_vdd: aldo4 { 242 regulator-boot-on; 243 regulator-always-on; 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-name = "emmc_vdd"; 247 }; 248 }; 249 }; 250 251 eeprom@50 { 252 compatible = "atmel,24c04"; 253 reg = <0x50>; 254 bootph-pre-ram; 255 pagesize = <16>; 256 }; 257}; 258 259&i2c6 { 260 clock-frequency = <100000>; 261 i2c-sda-hold-time-ns = <300>; 262 i2c-sda-falling-time-ns = <510>; 263 i2c-scl-falling-time-ns = <510>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&i2c6_pins>; 266 status = "okay"; 267}; 268 269&mmc0 { 270 max-frequency = <100000000>; 271 assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; 272 assigned-clock-rates = <50000000>; 273 bus-width = <8>; 274 bootph-pre-ram; 275 cap-mmc-highspeed; 276 mmc-ddr-1_8v; 277 mmc-hs200-1_8v; 278 cap-mmc-hw-reset; 279 post-power-on-delay-ms = <200>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&mmc0_pins>; 282 vmmc-supply = <&vcc_3v3>; 283 vqmmc-supply = <&emmc_vdd>; 284 status = "okay"; 285}; 286 287&mmc1 { 288 max-frequency = <100000000>; 289 assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; 290 assigned-clock-rates = <50000000>; 291 bus-width = <4>; 292 bootph-pre-ram; 293 no-sdio; 294 no-mmc; 295 cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; 296 disable-wp; 297 cap-sd-highspeed; 298 post-power-on-delay-ms = <200>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&mmc1_pins>; 301 status = "okay"; 302}; 303 304&pcie0 { 305 perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; 306 phys = <&pciephy0>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pcie0_pins>; 309}; 310 311&pcie1 { 312 perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; 313 phys = <&pciephy1>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pcie1_pins>; 316}; 317 318&pwmdac { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pwmdac_pins>; 321}; 322 323&qspi { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "okay"; 327 328 nor_flash: flash@0 { 329 compatible = "jedec,spi-nor"; 330 reg = <0>; 331 bootph-pre-ram; 332 cdns,read-delay = <2>; 333 spi-max-frequency = <100000000>; 334 cdns,tshsl-ns = <1>; 335 cdns,tsd2d-ns = <1>; 336 cdns,tchsh-ns = <1>; 337 cdns,tslch-ns = <1>; 338 339 partitions { 340 compatible = "fixed-partitions"; 341 #address-cells = <1>; 342 #size-cells = <1>; 343 344 spl@0 { 345 reg = <0x0 0xf0000>; 346 }; 347 uboot-env@f0000 { 348 reg = <0xf0000 0x10000>; 349 }; 350 uboot@100000 { 351 reg = <0x100000 0xf00000>; 352 }; 353 }; 354 }; 355}; 356 357&pwm { 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pwm_pins>; 360}; 361 362&spi0 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&spi0_pins>; 365}; 366 367&syscrg { 368 assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, 369 <&syscrg JH7110_SYSCLK_BUS_ROOT>, 370 <&syscrg JH7110_SYSCLK_PERH_ROOT>, 371 <&syscrg JH7110_SYSCLK_QSPI_REF>, 372 <&syscrg JH7110_SYSCLK_CPU_CORE>, 373 <&pllclk JH7110_PLLCLK_PLL0_OUT>; 374 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, 375 <&pllclk JH7110_PLLCLK_PLL2_OUT>, 376 <&pllclk JH7110_PLLCLK_PLL2_OUT>, 377 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; 378 assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>; 379}; 380 381&sysgpio { 382 i2c0_pins: i2c0-0 { 383 i2c-pins { 384 pinmux = <GPIOMUX(57, GPOUT_LOW, 385 GPOEN_SYS_I2C0_CLK, 386 GPI_SYS_I2C0_CLK)>, 387 <GPIOMUX(58, GPOUT_LOW, 388 GPOEN_SYS_I2C0_DATA, 389 GPI_SYS_I2C0_DATA)>; 390 bias-disable; /* external pull-up */ 391 input-enable; 392 input-schmitt-enable; 393 }; 394 }; 395 396 i2c2_pins: i2c2-0 { 397 i2c-pins { 398 pinmux = <GPIOMUX(3, GPOUT_LOW, 399 GPOEN_SYS_I2C2_CLK, 400 GPI_SYS_I2C2_CLK)>, 401 <GPIOMUX(2, GPOUT_LOW, 402 GPOEN_SYS_I2C2_DATA, 403 GPI_SYS_I2C2_DATA)>; 404 bias-disable; /* external pull-up */ 405 input-enable; 406 input-schmitt-enable; 407 }; 408 }; 409 410 i2c5_pins: i2c5-0 { 411 bootph-pre-ram; 412 413 i2c-pins { 414 pinmux = <GPIOMUX(19, GPOUT_LOW, 415 GPOEN_SYS_I2C5_CLK, 416 GPI_SYS_I2C5_CLK)>, 417 <GPIOMUX(20, GPOUT_LOW, 418 GPOEN_SYS_I2C5_DATA, 419 GPI_SYS_I2C5_DATA)>; 420 bias-disable; /* external pull-up */ 421 bootph-pre-ram; 422 input-enable; 423 input-schmitt-enable; 424 }; 425 }; 426 427 i2c6_pins: i2c6-0 { 428 i2c-pins { 429 pinmux = <GPIOMUX(16, GPOUT_LOW, 430 GPOEN_SYS_I2C6_CLK, 431 GPI_SYS_I2C6_CLK)>, 432 <GPIOMUX(17, GPOUT_LOW, 433 GPOEN_SYS_I2C6_DATA, 434 GPI_SYS_I2C6_DATA)>; 435 bias-disable; /* external pull-up */ 436 input-enable; 437 input-schmitt-enable; 438 }; 439 }; 440 441 mmc0_pins: mmc0-0 { 442 rst-pins { 443 pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, 444 GPOEN_ENABLE, 445 GPI_NONE)>; 446 bias-pull-up; 447 drive-strength = <12>; 448 input-disable; 449 input-schmitt-disable; 450 slew-rate = <0>; 451 }; 452 453 mmc-pins { 454 pinmux = <PINMUX(PAD_SD0_CLK, 0)>, 455 <PINMUX(PAD_SD0_CMD, 0)>, 456 <PINMUX(PAD_SD0_DATA0, 0)>, 457 <PINMUX(PAD_SD0_DATA1, 0)>, 458 <PINMUX(PAD_SD0_DATA2, 0)>, 459 <PINMUX(PAD_SD0_DATA3, 0)>, 460 <PINMUX(PAD_SD0_DATA4, 0)>, 461 <PINMUX(PAD_SD0_DATA5, 0)>, 462 <PINMUX(PAD_SD0_DATA6, 0)>, 463 <PINMUX(PAD_SD0_DATA7, 0)>; 464 bias-pull-up; 465 drive-strength = <12>; 466 input-enable; 467 }; 468 }; 469 470 mmc1_pins: mmc1-0 { 471 clk-pins { 472 pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, 473 GPOEN_ENABLE, 474 GPI_NONE)>; 475 bias-pull-up; 476 drive-strength = <12>; 477 input-disable; 478 input-schmitt-disable; 479 slew-rate = <0>; 480 }; 481 482 mmc-pins { 483 pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, 484 GPOEN_SYS_SDIO1_CMD, 485 GPI_SYS_SDIO1_CMD)>, 486 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, 487 GPOEN_SYS_SDIO1_DATA0, 488 GPI_SYS_SDIO1_DATA0)>, 489 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, 490 GPOEN_SYS_SDIO1_DATA1, 491 GPI_SYS_SDIO1_DATA1)>, 492 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, 493 GPOEN_SYS_SDIO1_DATA2, 494 GPI_SYS_SDIO1_DATA2)>, 495 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, 496 GPOEN_SYS_SDIO1_DATA3, 497 GPI_SYS_SDIO1_DATA3)>; 498 bias-pull-up; 499 drive-strength = <12>; 500 input-enable; 501 input-schmitt-enable; 502 slew-rate = <0>; 503 }; 504 }; 505 506 pcie0_pins: pcie0-0 { 507 clkreq-pins { 508 pinmux = <GPIOMUX(27, GPOUT_LOW, 509 GPOEN_DISABLE, 510 GPI_NONE)>; 511 bias-pull-down; 512 drive-strength = <2>; 513 input-enable; 514 input-schmitt-disable; 515 slew-rate = <0>; 516 }; 517 518 wake-pins { 519 pinmux = <GPIOMUX(32, GPOUT_LOW, 520 GPOEN_DISABLE, 521 GPI_NONE)>; 522 bias-pull-up; 523 drive-strength = <2>; 524 input-enable; 525 input-schmitt-disable; 526 slew-rate = <0>; 527 }; 528 }; 529 530 pcie1_pins: pcie1-0 { 531 clkreq-pins { 532 pinmux = <GPIOMUX(29, GPOUT_LOW, 533 GPOEN_DISABLE, 534 GPI_NONE)>; 535 bias-pull-down; 536 drive-strength = <2>; 537 input-enable; 538 input-schmitt-disable; 539 slew-rate = <0>; 540 }; 541 542 wake-pins { 543 pinmux = <GPIOMUX(21, GPOUT_LOW, 544 GPOEN_DISABLE, 545 GPI_NONE)>; 546 bias-pull-up; 547 drive-strength = <2>; 548 input-enable; 549 input-schmitt-disable; 550 slew-rate = <0>; 551 }; 552 }; 553 554 pwmdac_pins: pwmdac-0 { 555 pwmdac-pins { 556 pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, 557 GPOEN_ENABLE, 558 GPI_NONE)>, 559 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT, 560 GPOEN_ENABLE, 561 GPI_NONE)>; 562 bias-disable; 563 drive-strength = <2>; 564 input-disable; 565 input-schmitt-disable; 566 slew-rate = <0>; 567 }; 568 }; 569 570 pwm_pins: pwm-0 { 571 pwm-pins { 572 pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0, 573 GPOEN_SYS_PWM0_CHANNEL0, 574 GPI_NONE)>, 575 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1, 576 GPOEN_SYS_PWM0_CHANNEL1, 577 GPI_NONE)>; 578 bias-disable; 579 drive-strength = <12>; 580 input-disable; 581 input-schmitt-disable; 582 slew-rate = <0>; 583 }; 584 }; 585 586 spi0_pins: spi0-0 { 587 mosi-pins { 588 pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, 589 GPOEN_ENABLE, 590 GPI_NONE)>; 591 bias-disable; 592 input-disable; 593 input-schmitt-disable; 594 }; 595 596 miso-pins { 597 pinmux = <GPIOMUX(53, GPOUT_LOW, 598 GPOEN_DISABLE, 599 GPI_SYS_SPI0_RXD)>; 600 bias-pull-up; 601 input-enable; 602 input-schmitt-enable; 603 }; 604 605 sck-pins { 606 pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, 607 GPOEN_ENABLE, 608 GPI_SYS_SPI0_CLK)>; 609 bias-disable; 610 input-disable; 611 input-schmitt-disable; 612 }; 613 614 ss-pins { 615 pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, 616 GPOEN_ENABLE, 617 GPI_SYS_SPI0_FSS)>; 618 bias-disable; 619 input-disable; 620 input-schmitt-disable; 621 }; 622 }; 623 624 uart0_pins: uart0-0 { 625 tx-pins { 626 pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, 627 GPOEN_ENABLE, 628 GPI_NONE)>; 629 bias-disable; 630 drive-strength = <12>; 631 input-disable; 632 input-schmitt-disable; 633 slew-rate = <0>; 634 }; 635 636 rx-pins { 637 pinmux = <GPIOMUX(6, GPOUT_LOW, 638 GPOEN_DISABLE, 639 GPI_SYS_UART0_RX)>; 640 bias-disable; /* external pull-up */ 641 drive-strength = <2>; 642 input-enable; 643 input-schmitt-enable; 644 slew-rate = <0>; 645 }; 646 }; 647}; 648 649&uart0 { 650 bootph-pre-ram; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&uart0_pins>; 653 status = "okay"; 654}; 655 656&U74_1 { 657 cpu-supply = <&vdd_cpu>; 658}; 659 660&U74_2 { 661 cpu-supply = <&vdd_cpu>; 662}; 663 664&U74_3 { 665 cpu-supply = <&vdd_cpu>; 666}; 667 668&U74_4 { 669 cpu-supply = <&vdd_cpu>; 670}; 671