1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive-jh7100.h> 9#include <dt-bindings/reset/starfive-jh7100.h> 10 11/ { 12 compatible = "starfive,jh7100"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 U74_0: cpu@0 { 21 compatible = "sifive,u74-mc", "riscv"; 22 reg = <0>; 23 d-cache-block-size = <64>; 24 d-cache-sets = <64>; 25 d-cache-size = <32768>; 26 d-tlb-sets = <1>; 27 d-tlb-size = <32>; 28 device_type = "cpu"; 29 i-cache-block-size = <64>; 30 i-cache-sets = <64>; 31 i-cache-size = <32768>; 32 i-tlb-sets = <1>; 33 i-tlb-size = <32>; 34 mmu-type = "riscv,sv39"; 35 riscv,isa = "rv64imafdc"; 36 tlb-split; 37 38 cpu0_intc: interrupt-controller { 39 compatible = "riscv,cpu-intc"; 40 interrupt-controller; 41 #interrupt-cells = <1>; 42 }; 43 }; 44 45 U74_1: cpu@1 { 46 compatible = "sifive,u74-mc", "riscv"; 47 reg = <1>; 48 d-cache-block-size = <64>; 49 d-cache-sets = <64>; 50 d-cache-size = <32768>; 51 d-tlb-sets = <1>; 52 d-tlb-size = <32>; 53 device_type = "cpu"; 54 i-cache-block-size = <64>; 55 i-cache-sets = <64>; 56 i-cache-size = <32768>; 57 i-tlb-sets = <1>; 58 i-tlb-size = <32>; 59 mmu-type = "riscv,sv39"; 60 riscv,isa = "rv64imafdc"; 61 tlb-split; 62 63 cpu1_intc: interrupt-controller { 64 compatible = "riscv,cpu-intc"; 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 }; 68 }; 69 70 cpu-map { 71 cluster0 { 72 core0 { 73 cpu = <&U74_0>; 74 }; 75 76 core1 { 77 cpu = <&U74_1>; 78 }; 79 }; 80 }; 81 }; 82 83 thermal-zones { 84 cpu-thermal { 85 polling-delay-passive = <250>; 86 polling-delay = <15000>; 87 88 thermal-sensors = <&sfctemp>; 89 90 trips { 91 cpu_alert0 { 92 /* milliCelsius */ 93 temperature = <75000>; 94 hysteresis = <2000>; 95 type = "passive"; 96 }; 97 98 cpu_crit { 99 /* milliCelsius */ 100 temperature = <90000>; 101 hysteresis = <2000>; 102 type = "critical"; 103 }; 104 }; 105 }; 106 }; 107 108 osc_sys: osc_sys { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 /* This value must be overridden by the board */ 112 clock-frequency = <0>; 113 }; 114 115 osc_aud: osc_aud { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 /* This value must be overridden by the board */ 119 clock-frequency = <0>; 120 }; 121 122 gmac_rmii_ref: gmac_rmii_ref { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 /* Should be overridden by the board when needed */ 126 clock-frequency = <0>; 127 }; 128 129 gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 /* Should be overridden by the board when needed */ 133 clock-frequency = <0>; 134 }; 135 136 soc { 137 compatible = "simple-bus"; 138 interrupt-parent = <&plic>; 139 #address-cells = <2>; 140 #size-cells = <2>; 141 ranges; 142 143 clint: clint@2000000 { 144 compatible = "starfive,jh7100-clint", "sifive,clint0"; 145 reg = <0x0 0x2000000 0x0 0x10000>; 146 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 147 &cpu1_intc 3 &cpu1_intc 7>; 148 }; 149 150 plic: interrupt-controller@c000000 { 151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; 152 reg = <0x0 0xc000000 0x0 0x4000000>; 153 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 154 &cpu1_intc 11 &cpu1_intc 9>; 155 interrupt-controller; 156 #address-cells = <0>; 157 #interrupt-cells = <1>; 158 riscv,ndev = <133>; 159 }; 160 161 clkgen: clock-controller@11800000 { 162 compatible = "starfive,jh7100-clkgen"; 163 reg = <0x0 0x11800000 0x0 0x10000>; 164 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; 165 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; 166 #clock-cells = <1>; 167 }; 168 169 rstgen: reset-controller@11840000 { 170 compatible = "starfive,jh7100-reset"; 171 reg = <0x0 0x11840000 0x0 0x10000>; 172 #reset-cells = <1>; 173 }; 174 175 i2c0: i2c@118b0000 { 176 compatible = "snps,designware-i2c"; 177 reg = <0x0 0x118b0000 0x0 0x10000>; 178 clocks = <&clkgen JH7100_CLK_I2C0_CORE>, 179 <&clkgen JH7100_CLK_I2C0_APB>; 180 clock-names = "ref", "pclk"; 181 resets = <&rstgen JH7100_RSTN_I2C0_APB>; 182 interrupts = <96>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 status = "disabled"; 186 }; 187 188 i2c1: i2c@118c0000 { 189 compatible = "snps,designware-i2c"; 190 reg = <0x0 0x118c0000 0x0 0x10000>; 191 clocks = <&clkgen JH7100_CLK_I2C1_CORE>, 192 <&clkgen JH7100_CLK_I2C1_APB>; 193 clock-names = "ref", "pclk"; 194 resets = <&rstgen JH7100_RSTN_I2C1_APB>; 195 interrupts = <97>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 201 gpio: pinctrl@11910000 { 202 compatible = "starfive,jh7100-pinctrl"; 203 reg = <0x0 0x11910000 0x0 0x10000>, 204 <0x0 0x11858000 0x0 0x1000>; 205 reg-names = "gpio", "padctl"; 206 clocks = <&clkgen JH7100_CLK_GPIO_APB>; 207 resets = <&rstgen JH7100_RSTN_GPIO_APB>; 208 interrupts = <32>; 209 gpio-controller; 210 #gpio-cells = <2>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 }; 214 215 uart2: serial@12430000 { 216 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 217 reg = <0x0 0x12430000 0x0 0x10000>; 218 clocks = <&clkgen JH7100_CLK_UART2_CORE>, 219 <&clkgen JH7100_CLK_UART2_APB>; 220 clock-names = "baudclk", "apb_pclk"; 221 resets = <&rstgen JH7100_RSTN_UART2_APB>; 222 interrupts = <72>; 223 reg-io-width = <4>; 224 reg-shift = <2>; 225 status = "disabled"; 226 }; 227 228 uart3: serial@12440000 { 229 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 230 reg = <0x0 0x12440000 0x0 0x10000>; 231 clocks = <&clkgen JH7100_CLK_UART3_CORE>, 232 <&clkgen JH7100_CLK_UART3_APB>; 233 clock-names = "baudclk", "apb_pclk"; 234 resets = <&rstgen JH7100_RSTN_UART3_APB>; 235 interrupts = <73>; 236 reg-io-width = <4>; 237 reg-shift = <2>; 238 status = "disabled"; 239 }; 240 241 i2c2: i2c@12450000 { 242 compatible = "snps,designware-i2c"; 243 reg = <0x0 0x12450000 0x0 0x10000>; 244 clocks = <&clkgen JH7100_CLK_I2C2_CORE>, 245 <&clkgen JH7100_CLK_I2C2_APB>; 246 clock-names = "ref", "pclk"; 247 resets = <&rstgen JH7100_RSTN_I2C2_APB>; 248 interrupts = <74>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@12460000 { 255 compatible = "snps,designware-i2c"; 256 reg = <0x0 0x12460000 0x0 0x10000>; 257 clocks = <&clkgen JH7100_CLK_I2C3_CORE>, 258 <&clkgen JH7100_CLK_I2C3_APB>; 259 clock-names = "ref", "pclk"; 260 resets = <&rstgen JH7100_RSTN_I2C3_APB>; 261 interrupts = <75>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 watchdog@12480000 { 268 compatible = "starfive,jh7100-wdt"; 269 reg = <0x0 0x12480000 0x0 0x10000>; 270 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, 271 <&clkgen JH7100_CLK_WDT_CORE>; 272 clock-names = "apb", "core"; 273 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, 274 <&rstgen JH7100_RSTN_WDT>; 275 }; 276 277 sfctemp: temperature-sensor@124a0000 { 278 compatible = "starfive,jh7100-temp"; 279 reg = <0x0 0x124a0000 0x0 0x10000>; 280 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, 281 <&clkgen JH7100_CLK_TEMP_APB>; 282 clock-names = "sense", "bus"; 283 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, 284 <&rstgen JH7100_RSTN_TEMP_APB>; 285 reset-names = "sense", "bus"; 286 #thermal-sensor-cells = <0>; 287 }; 288 }; 289}; 290