1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive-jh7100.h> 9#include <dt-bindings/reset/starfive-jh7100.h> 10 11/ { 12 compatible = "starfive,jh7100"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 U74_0: cpu@0 { 21 compatible = "sifive,u74-mc", "riscv"; 22 reg = <0>; 23 d-cache-block-size = <64>; 24 d-cache-sets = <64>; 25 d-cache-size = <32768>; 26 d-tlb-sets = <1>; 27 d-tlb-size = <32>; 28 device_type = "cpu"; 29 i-cache-block-size = <64>; 30 i-cache-sets = <64>; 31 i-cache-size = <32768>; 32 i-tlb-sets = <1>; 33 i-tlb-size = <32>; 34 mmu-type = "riscv,sv39"; 35 next-level-cache = <&ccache>; 36 riscv,isa = "rv64imafdc"; 37 riscv,isa-base = "rv64i"; 38 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 39 "zifencei", "zihpm"; 40 tlb-split; 41 42 cpu0_intc: interrupt-controller { 43 compatible = "riscv,cpu-intc"; 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 }; 47 }; 48 49 U74_1: cpu@1 { 50 compatible = "sifive,u74-mc", "riscv"; 51 reg = <1>; 52 d-cache-block-size = <64>; 53 d-cache-sets = <64>; 54 d-cache-size = <32768>; 55 d-tlb-sets = <1>; 56 d-tlb-size = <32>; 57 device_type = "cpu"; 58 i-cache-block-size = <64>; 59 i-cache-sets = <64>; 60 i-cache-size = <32768>; 61 i-tlb-sets = <1>; 62 i-tlb-size = <32>; 63 mmu-type = "riscv,sv39"; 64 next-level-cache = <&ccache>; 65 riscv,isa = "rv64imafdc"; 66 riscv,isa-base = "rv64i"; 67 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 68 "zifencei", "zihpm"; 69 tlb-split; 70 71 cpu1_intc: interrupt-controller { 72 compatible = "riscv,cpu-intc"; 73 interrupt-controller; 74 #interrupt-cells = <1>; 75 }; 76 }; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&U74_0>; 82 }; 83 84 core1 { 85 cpu = <&U74_1>; 86 }; 87 }; 88 }; 89 }; 90 91 thermal-zones { 92 cpu-thermal { 93 polling-delay-passive = <250>; 94 polling-delay = <15000>; 95 96 thermal-sensors = <&sfctemp>; 97 98 trips { 99 cpu-alert0 { 100 /* milliCelsius */ 101 temperature = <75000>; 102 hysteresis = <2000>; 103 type = "passive"; 104 }; 105 106 cpu-crit { 107 /* milliCelsius */ 108 temperature = <90000>; 109 hysteresis = <2000>; 110 type = "critical"; 111 }; 112 }; 113 }; 114 }; 115 116 osc_sys: osc-sys { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-output-names = "osc_sys"; 120 /* This value must be overridden by the board */ 121 clock-frequency = <0>; 122 }; 123 124 osc_aud: osc-aud { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-output-names = "osc_aud"; 128 /* This value must be overridden by the board */ 129 clock-frequency = <0>; 130 }; 131 132 gmac_rmii_ref: gmac-rmii-ref { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-output-names = "gmac_rmii_ref"; 136 /* Should be overridden by the board when needed */ 137 clock-frequency = <0>; 138 }; 139 140 gmac_gr_mii_rxclk: gmac-gr-mii-rxclk { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-output-names = "gmac_gr_mii_rxclk"; 144 /* Should be overridden by the board when needed */ 145 clock-frequency = <0>; 146 }; 147 148 soc { 149 compatible = "simple-bus"; 150 interrupt-parent = <&plic>; 151 #address-cells = <2>; 152 #size-cells = <2>; 153 dma-noncoherent; 154 ranges; 155 156 clint: clint@2000000 { 157 compatible = "starfive,jh7100-clint", "sifive,clint0"; 158 reg = <0x0 0x2000000 0x0 0x10000>; 159 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 160 <&cpu1_intc 3>, <&cpu1_intc 7>; 161 }; 162 163 ccache: cache-controller@2010000 { 164 compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache"; 165 reg = <0x0 0x2010000 0x0 0x1000>; 166 interrupts = <128>, <130>, <131>, <129>; 167 cache-block-size = <64>; 168 cache-level = <2>; 169 cache-sets = <2048>; 170 cache-size = <2097152>; 171 cache-unified; 172 }; 173 174 plic: interrupt-controller@c000000 { 175 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; 176 reg = <0x0 0xc000000 0x0 0x4000000>; 177 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 178 <&cpu1_intc 11>, <&cpu1_intc 9>; 179 interrupt-controller; 180 #address-cells = <0>; 181 #interrupt-cells = <1>; 182 riscv,ndev = <133>; 183 }; 184 185 sdio0: mmc@10000000 { 186 compatible = "snps,dw-mshc"; 187 reg = <0x0 0x10000000 0x0 0x10000>; 188 clocks = <&clkgen JH7100_CLK_SDIO0_AHB>, 189 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>; 190 clock-names = "biu", "ciu"; 191 interrupts = <4>; 192 data-addr = <0>; 193 fifo-depth = <32>; 194 fifo-watermark-aligned; 195 status = "disabled"; 196 }; 197 198 sdio1: mmc@10010000 { 199 compatible = "snps,dw-mshc"; 200 reg = <0x0 0x10010000 0x0 0x10000>; 201 clocks = <&clkgen JH7100_CLK_SDIO1_AHB>, 202 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>; 203 clock-names = "biu", "ciu"; 204 interrupts = <5>; 205 data-addr = <0>; 206 fifo-depth = <32>; 207 fifo-watermark-aligned; 208 status = "disabled"; 209 }; 210 211 gmac: ethernet@10020000 { 212 compatible = "starfive,jh7100-dwmac", "snps,dwmac"; 213 reg = <0x0 0x10020000 0x0 0x10000>; 214 clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, 215 <&clkgen JH7100_CLK_GMAC_AHB>, 216 <&clkgen JH7100_CLK_GMAC_PTP_REF>, 217 <&clkgen JH7100_CLK_GMAC_TX_INV>, 218 <&clkgen JH7100_CLK_GMAC_GTX>; 219 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; 220 resets = <&rstgen JH7100_RSTN_GMAC_AHB>; 221 reset-names = "ahb"; 222 interrupts = <6>, <7>; 223 interrupt-names = "macirq", "eth_wake_irq"; 224 max-frame-size = <9000>; 225 snps,multicast-filter-bins = <32>; 226 snps,perfect-filter-entries = <128>; 227 starfive,syscon = <&sysmain 0x70 0>; 228 rx-fifo-depth = <32768>; 229 tx-fifo-depth = <16384>; 230 snps,axi-config = <&stmmac_axi_setup>; 231 snps,fixed-burst; 232 snps,force_thresh_dma_mode; 233 status = "disabled"; 234 235 stmmac_axi_setup: stmmac-axi-config { 236 snps,wr_osr_lmt = <16>; 237 snps,rd_osr_lmt = <16>; 238 snps,blen = <256 128 64 32 0 0 0>; 239 }; 240 }; 241 242 clkgen: clock-controller@11800000 { 243 compatible = "starfive,jh7100-clkgen"; 244 reg = <0x0 0x11800000 0x0 0x10000>; 245 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; 246 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; 247 #clock-cells = <1>; 248 }; 249 250 rstgen: reset-controller@11840000 { 251 compatible = "starfive,jh7100-reset"; 252 reg = <0x0 0x11840000 0x0 0x10000>; 253 #reset-cells = <1>; 254 }; 255 256 sysmain: syscon@11850000 { 257 compatible = "starfive,jh7100-sysmain", "syscon"; 258 reg = <0x0 0x11850000 0x0 0x10000>; 259 }; 260 261 i2c0: i2c@118b0000 { 262 compatible = "snps,designware-i2c"; 263 reg = <0x0 0x118b0000 0x0 0x10000>; 264 clocks = <&clkgen JH7100_CLK_I2C0_CORE>, 265 <&clkgen JH7100_CLK_I2C0_APB>; 266 clock-names = "ref", "pclk"; 267 resets = <&rstgen JH7100_RSTN_I2C0_APB>; 268 interrupts = <96>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 status = "disabled"; 272 }; 273 274 i2c1: i2c@118c0000 { 275 compatible = "snps,designware-i2c"; 276 reg = <0x0 0x118c0000 0x0 0x10000>; 277 clocks = <&clkgen JH7100_CLK_I2C1_CORE>, 278 <&clkgen JH7100_CLK_I2C1_APB>; 279 clock-names = "ref", "pclk"; 280 resets = <&rstgen JH7100_RSTN_I2C1_APB>; 281 interrupts = <97>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 status = "disabled"; 285 }; 286 287 gpio: pinctrl@11910000 { 288 compatible = "starfive,jh7100-pinctrl"; 289 reg = <0x0 0x11910000 0x0 0x10000>, 290 <0x0 0x11858000 0x0 0x1000>; 291 reg-names = "gpio", "padctl"; 292 clocks = <&clkgen JH7100_CLK_GPIO_APB>; 293 resets = <&rstgen JH7100_RSTN_GPIO_APB>; 294 interrupts = <32>; 295 gpio-controller; 296 #gpio-cells = <2>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 }; 300 301 uart2: serial@12430000 { 302 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 303 reg = <0x0 0x12430000 0x0 0x10000>; 304 clocks = <&clkgen JH7100_CLK_UART2_CORE>, 305 <&clkgen JH7100_CLK_UART2_APB>; 306 clock-names = "baudclk", "apb_pclk"; 307 resets = <&rstgen JH7100_RSTN_UART2_APB>; 308 interrupts = <72>; 309 reg-io-width = <4>; 310 reg-shift = <2>; 311 status = "disabled"; 312 }; 313 314 uart3: serial@12440000 { 315 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 316 reg = <0x0 0x12440000 0x0 0x10000>; 317 clocks = <&clkgen JH7100_CLK_UART3_CORE>, 318 <&clkgen JH7100_CLK_UART3_APB>; 319 clock-names = "baudclk", "apb_pclk"; 320 resets = <&rstgen JH7100_RSTN_UART3_APB>; 321 interrupts = <73>; 322 reg-io-width = <4>; 323 reg-shift = <2>; 324 status = "disabled"; 325 }; 326 327 i2c2: i2c@12450000 { 328 compatible = "snps,designware-i2c"; 329 reg = <0x0 0x12450000 0x0 0x10000>; 330 clocks = <&clkgen JH7100_CLK_I2C2_CORE>, 331 <&clkgen JH7100_CLK_I2C2_APB>; 332 clock-names = "ref", "pclk"; 333 resets = <&rstgen JH7100_RSTN_I2C2_APB>; 334 interrupts = <74>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 }; 339 340 i2c3: i2c@12460000 { 341 compatible = "snps,designware-i2c"; 342 reg = <0x0 0x12460000 0x0 0x10000>; 343 clocks = <&clkgen JH7100_CLK_I2C3_CORE>, 344 <&clkgen JH7100_CLK_I2C3_APB>; 345 clock-names = "ref", "pclk"; 346 resets = <&rstgen JH7100_RSTN_I2C3_APB>; 347 interrupts = <75>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 watchdog@12480000 { 354 compatible = "starfive,jh7100-wdt"; 355 reg = <0x0 0x12480000 0x0 0x10000>; 356 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, 357 <&clkgen JH7100_CLK_WDT_CORE>; 358 clock-names = "apb", "core"; 359 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, 360 <&rstgen JH7100_RSTN_WDT>; 361 }; 362 363 pwm: pwm@12490000 { 364 compatible = "starfive,jh7100-pwm", "opencores,pwm-v1"; 365 reg = <0x0 0x12490000 0x0 0x10000>; 366 clocks = <&clkgen JH7100_CLK_PWM_APB>; 367 resets = <&rstgen JH7100_RSTN_PWM_APB>; 368 #pwm-cells = <3>; 369 status = "disabled"; 370 }; 371 372 sfctemp: temperature-sensor@124a0000 { 373 compatible = "starfive,jh7100-temp"; 374 reg = <0x0 0x124a0000 0x0 0x10000>; 375 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, 376 <&clkgen JH7100_CLK_TEMP_APB>; 377 clock-names = "sense", "bus"; 378 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, 379 <&rstgen JH7100_RSTN_TEMP_APB>; 380 reset-names = "sense", "bus"; 381 #thermal-sensor-cells = <0>; 382 }; 383 }; 384}; 385