1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2021 StarFive Technology Co., Ltd. 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive-jh7100.h> 9#include <dt-bindings/reset/starfive-jh7100.h> 10 11/ { 12 compatible = "starfive,jh7100"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 U74_0: cpu@0 { 21 compatible = "sifive,u74-mc", "riscv"; 22 reg = <0>; 23 d-cache-block-size = <64>; 24 d-cache-sets = <64>; 25 d-cache-size = <32768>; 26 d-tlb-sets = <1>; 27 d-tlb-size = <32>; 28 device_type = "cpu"; 29 i-cache-block-size = <64>; 30 i-cache-sets = <64>; 31 i-cache-size = <32768>; 32 i-tlb-sets = <1>; 33 i-tlb-size = <32>; 34 mmu-type = "riscv,sv39"; 35 riscv,isa = "rv64imafdc"; 36 riscv,isa-base = "rv64i"; 37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 38 "zifencei", "zihpm"; 39 tlb-split; 40 41 cpu0_intc: interrupt-controller { 42 compatible = "riscv,cpu-intc"; 43 interrupt-controller; 44 #interrupt-cells = <1>; 45 }; 46 }; 47 48 U74_1: cpu@1 { 49 compatible = "sifive,u74-mc", "riscv"; 50 reg = <1>; 51 d-cache-block-size = <64>; 52 d-cache-sets = <64>; 53 d-cache-size = <32768>; 54 d-tlb-sets = <1>; 55 d-tlb-size = <32>; 56 device_type = "cpu"; 57 i-cache-block-size = <64>; 58 i-cache-sets = <64>; 59 i-cache-size = <32768>; 60 i-tlb-sets = <1>; 61 i-tlb-size = <32>; 62 mmu-type = "riscv,sv39"; 63 riscv,isa = "rv64imafdc"; 64 riscv,isa-base = "rv64i"; 65 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 66 "zifencei", "zihpm"; 67 tlb-split; 68 69 cpu1_intc: interrupt-controller { 70 compatible = "riscv,cpu-intc"; 71 interrupt-controller; 72 #interrupt-cells = <1>; 73 }; 74 }; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&U74_0>; 80 }; 81 82 core1 { 83 cpu = <&U74_1>; 84 }; 85 }; 86 }; 87 }; 88 89 thermal-zones { 90 cpu-thermal { 91 polling-delay-passive = <250>; 92 polling-delay = <15000>; 93 94 thermal-sensors = <&sfctemp>; 95 96 trips { 97 cpu_alert0 { 98 /* milliCelsius */ 99 temperature = <75000>; 100 hysteresis = <2000>; 101 type = "passive"; 102 }; 103 104 cpu_crit { 105 /* milliCelsius */ 106 temperature = <90000>; 107 hysteresis = <2000>; 108 type = "critical"; 109 }; 110 }; 111 }; 112 }; 113 114 osc_sys: osc_sys { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 /* This value must be overridden by the board */ 118 clock-frequency = <0>; 119 }; 120 121 osc_aud: osc_aud { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 /* This value must be overridden by the board */ 125 clock-frequency = <0>; 126 }; 127 128 gmac_rmii_ref: gmac_rmii_ref { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 /* Should be overridden by the board when needed */ 132 clock-frequency = <0>; 133 }; 134 135 gmac_gr_mii_rxclk: gmac_gr_mii_rxclk { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 /* Should be overridden by the board when needed */ 139 clock-frequency = <0>; 140 }; 141 142 soc { 143 compatible = "simple-bus"; 144 interrupt-parent = <&plic>; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 clint: clint@2000000 { 150 compatible = "starfive,jh7100-clint", "sifive,clint0"; 151 reg = <0x0 0x2000000 0x0 0x10000>; 152 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 153 &cpu1_intc 3 &cpu1_intc 7>; 154 }; 155 156 plic: interrupt-controller@c000000 { 157 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; 158 reg = <0x0 0xc000000 0x0 0x4000000>; 159 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 160 &cpu1_intc 11 &cpu1_intc 9>; 161 interrupt-controller; 162 #address-cells = <0>; 163 #interrupt-cells = <1>; 164 riscv,ndev = <133>; 165 }; 166 167 clkgen: clock-controller@11800000 { 168 compatible = "starfive,jh7100-clkgen"; 169 reg = <0x0 0x11800000 0x0 0x10000>; 170 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>; 171 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk"; 172 #clock-cells = <1>; 173 }; 174 175 rstgen: reset-controller@11840000 { 176 compatible = "starfive,jh7100-reset"; 177 reg = <0x0 0x11840000 0x0 0x10000>; 178 #reset-cells = <1>; 179 }; 180 181 i2c0: i2c@118b0000 { 182 compatible = "snps,designware-i2c"; 183 reg = <0x0 0x118b0000 0x0 0x10000>; 184 clocks = <&clkgen JH7100_CLK_I2C0_CORE>, 185 <&clkgen JH7100_CLK_I2C0_APB>; 186 clock-names = "ref", "pclk"; 187 resets = <&rstgen JH7100_RSTN_I2C0_APB>; 188 interrupts = <96>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 i2c1: i2c@118c0000 { 195 compatible = "snps,designware-i2c"; 196 reg = <0x0 0x118c0000 0x0 0x10000>; 197 clocks = <&clkgen JH7100_CLK_I2C1_CORE>, 198 <&clkgen JH7100_CLK_I2C1_APB>; 199 clock-names = "ref", "pclk"; 200 resets = <&rstgen JH7100_RSTN_I2C1_APB>; 201 interrupts = <97>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 status = "disabled"; 205 }; 206 207 gpio: pinctrl@11910000 { 208 compatible = "starfive,jh7100-pinctrl"; 209 reg = <0x0 0x11910000 0x0 0x10000>, 210 <0x0 0x11858000 0x0 0x1000>; 211 reg-names = "gpio", "padctl"; 212 clocks = <&clkgen JH7100_CLK_GPIO_APB>; 213 resets = <&rstgen JH7100_RSTN_GPIO_APB>; 214 interrupts = <32>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 }; 220 221 uart2: serial@12430000 { 222 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 223 reg = <0x0 0x12430000 0x0 0x10000>; 224 clocks = <&clkgen JH7100_CLK_UART2_CORE>, 225 <&clkgen JH7100_CLK_UART2_APB>; 226 clock-names = "baudclk", "apb_pclk"; 227 resets = <&rstgen JH7100_RSTN_UART2_APB>; 228 interrupts = <72>; 229 reg-io-width = <4>; 230 reg-shift = <2>; 231 status = "disabled"; 232 }; 233 234 uart3: serial@12440000 { 235 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart"; 236 reg = <0x0 0x12440000 0x0 0x10000>; 237 clocks = <&clkgen JH7100_CLK_UART3_CORE>, 238 <&clkgen JH7100_CLK_UART3_APB>; 239 clock-names = "baudclk", "apb_pclk"; 240 resets = <&rstgen JH7100_RSTN_UART3_APB>; 241 interrupts = <73>; 242 reg-io-width = <4>; 243 reg-shift = <2>; 244 status = "disabled"; 245 }; 246 247 i2c2: i2c@12450000 { 248 compatible = "snps,designware-i2c"; 249 reg = <0x0 0x12450000 0x0 0x10000>; 250 clocks = <&clkgen JH7100_CLK_I2C2_CORE>, 251 <&clkgen JH7100_CLK_I2C2_APB>; 252 clock-names = "ref", "pclk"; 253 resets = <&rstgen JH7100_RSTN_I2C2_APB>; 254 interrupts = <74>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 status = "disabled"; 258 }; 259 260 i2c3: i2c@12460000 { 261 compatible = "snps,designware-i2c"; 262 reg = <0x0 0x12460000 0x0 0x10000>; 263 clocks = <&clkgen JH7100_CLK_I2C3_CORE>, 264 <&clkgen JH7100_CLK_I2C3_APB>; 265 clock-names = "ref", "pclk"; 266 resets = <&rstgen JH7100_RSTN_I2C3_APB>; 267 interrupts = <75>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 watchdog@12480000 { 274 compatible = "starfive,jh7100-wdt"; 275 reg = <0x0 0x12480000 0x0 0x10000>; 276 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, 277 <&clkgen JH7100_CLK_WDT_CORE>; 278 clock-names = "apb", "core"; 279 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, 280 <&rstgen JH7100_RSTN_WDT>; 281 }; 282 283 sfctemp: temperature-sensor@124a0000 { 284 compatible = "starfive,jh7100-temp"; 285 reg = <0x0 0x124a0000 0x0 0x10000>; 286 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, 287 <&clkgen JH7100_CLK_TEMP_APB>; 288 clock-names = "sense", "bus"; 289 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, 290 <&rstgen JH7100_RSTN_TEMP_APB>; 291 reset-names = "sense", "bus"; 292 #thermal-sensor-cells = <0>; 293 }; 294 }; 295}; 296