xref: /linux/arch/riscv/boot/dts/spacemit/k1-opp.dtsi (revision 67f8bc848ee31831336bd478e57d2f993551902e)
1*3b9c3455SShuwei Wu// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*3b9c3455SShuwei Wu
3*3b9c3455SShuwei Wu/ {
4*3b9c3455SShuwei Wu	cluster0_opp_table: opp-table-cluster0 {
5*3b9c3455SShuwei Wu		compatible = "operating-points-v2";
6*3b9c3455SShuwei Wu		opp-shared;
7*3b9c3455SShuwei Wu
8*3b9c3455SShuwei Wu		opp-614400000 {
9*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <614400000>;
10*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
11*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
12*3b9c3455SShuwei Wu		};
13*3b9c3455SShuwei Wu
14*3b9c3455SShuwei Wu		opp-819000000 {
15*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <819000000>;
16*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
17*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
18*3b9c3455SShuwei Wu		};
19*3b9c3455SShuwei Wu
20*3b9c3455SShuwei Wu		opp-1000000000 {
21*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1000000000>;
22*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
23*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
24*3b9c3455SShuwei Wu		};
25*3b9c3455SShuwei Wu
26*3b9c3455SShuwei Wu		opp-1228800000 {
27*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1228800000>;
28*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
29*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
30*3b9c3455SShuwei Wu		};
31*3b9c3455SShuwei Wu
32*3b9c3455SShuwei Wu		opp-1600000000 {
33*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1600000000>;
34*3b9c3455SShuwei Wu			opp-microvolt = <1050000 1050000 1050000>;
35*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
36*3b9c3455SShuwei Wu		};
37*3b9c3455SShuwei Wu	};
38*3b9c3455SShuwei Wu
39*3b9c3455SShuwei Wu	cluster1_opp_table: opp-table-cluster1 {
40*3b9c3455SShuwei Wu		compatible = "operating-points-v2";
41*3b9c3455SShuwei Wu		opp-shared;
42*3b9c3455SShuwei Wu
43*3b9c3455SShuwei Wu		opp-614400000 {
44*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <614400000>;
45*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
46*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
47*3b9c3455SShuwei Wu		};
48*3b9c3455SShuwei Wu
49*3b9c3455SShuwei Wu		opp-819000000 {
50*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <819000000>;
51*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
52*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
53*3b9c3455SShuwei Wu		};
54*3b9c3455SShuwei Wu
55*3b9c3455SShuwei Wu		opp-1000000000 {
56*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1000000000>;
57*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
58*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
59*3b9c3455SShuwei Wu		};
60*3b9c3455SShuwei Wu
61*3b9c3455SShuwei Wu		opp-1228800000 {
62*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1228800000>;
63*3b9c3455SShuwei Wu			opp-microvolt = <950000 950000 1050000>;
64*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
65*3b9c3455SShuwei Wu		};
66*3b9c3455SShuwei Wu
67*3b9c3455SShuwei Wu		opp-1600000000 {
68*3b9c3455SShuwei Wu			opp-hz = /bits/ 64 <1600000000>;
69*3b9c3455SShuwei Wu			opp-microvolt = <1050000 1050000 1050000>;
70*3b9c3455SShuwei Wu			clock-latency-ns = <200000>;
71*3b9c3455SShuwei Wu		};
72*3b9c3455SShuwei Wu	};
73*3b9c3455SShuwei Wu};
74*3b9c3455SShuwei Wu
75*3b9c3455SShuwei Wu&cpu_0 {
76*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster0_opp_table>;
77*3b9c3455SShuwei Wu};
78*3b9c3455SShuwei Wu
79*3b9c3455SShuwei Wu&cpu_1 {
80*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster0_opp_table>;
81*3b9c3455SShuwei Wu};
82*3b9c3455SShuwei Wu
83*3b9c3455SShuwei Wu&cpu_2 {
84*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster0_opp_table>;
85*3b9c3455SShuwei Wu};
86*3b9c3455SShuwei Wu
87*3b9c3455SShuwei Wu&cpu_3 {
88*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster0_opp_table>;
89*3b9c3455SShuwei Wu};
90*3b9c3455SShuwei Wu
91*3b9c3455SShuwei Wu&cpu_4 {
92*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster1_opp_table>;
93*3b9c3455SShuwei Wu};
94*3b9c3455SShuwei Wu
95*3b9c3455SShuwei Wu&cpu_5 {
96*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster1_opp_table>;
97*3b9c3455SShuwei Wu};
98*3b9c3455SShuwei Wu
99*3b9c3455SShuwei Wu&cpu_6 {
100*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster1_opp_table>;
101*3b9c3455SShuwei Wu};
102*3b9c3455SShuwei Wu
103*3b9c3455SShuwei Wu&cpu_7 {
104*3b9c3455SShuwei Wu	operating-points-v2 = <&cluster1_opp_table>;
105*3b9c3455SShuwei Wu};
106