1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> 8#include <dt-bindings/clock/sophgo,sg2042-pll.h> 9#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset/sophgo,sg2042-reset.h> 12 13#include "sg2042-cpus.dtsi" 14 15/ { 16 compatible = "sophgo,sg2042"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 dma-noncoherent; 20 21 aliases { 22 serial0 = &uart0; 23 }; 24 25 cgi_main: oscillator0 { 26 compatible = "fixed-clock"; 27 clock-output-names = "cgi_main"; 28 #clock-cells = <0>; 29 }; 30 31 cgi_dpll0: oscillator1 { 32 compatible = "fixed-clock"; 33 clock-output-names = "cgi_dpll0"; 34 #clock-cells = <0>; 35 }; 36 37 cgi_dpll1: oscillator2 { 38 compatible = "fixed-clock"; 39 clock-output-names = "cgi_dpll1"; 40 #clock-cells = <0>; 41 }; 42 43 soc: soc { 44 compatible = "simple-bus"; 45 #address-cells = <2>; 46 #size-cells = <2>; 47 ranges; 48 49 pllclk: clock-controller@70300100c0 { 50 compatible = "sophgo,sg2042-pll"; 51 reg = <0x70 0x300100c0 0x0 0x40>; 52 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; 53 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; 54 #clock-cells = <1>; 55 }; 56 57 rpgate: clock-controller@7030010368 { 58 compatible = "sophgo,sg2042-rpgate"; 59 reg = <0x70 0x30010368 0x0 0x98>; 60 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; 61 clock-names = "rpgate"; 62 #clock-cells = <1>; 63 }; 64 65 clkgen: clock-controller@7030012000 { 66 compatible = "sophgo,sg2042-clkgen"; 67 reg = <0x70 0x30012000 0x0 0x1000>; 68 clocks = <&pllclk MPLL_CLK>, 69 <&pllclk FPLL_CLK>, 70 <&pllclk DPLL0_CLK>, 71 <&pllclk DPLL1_CLK>; 72 clock-names = "mpll", 73 "fpll", 74 "dpll0", 75 "dpll1"; 76 #clock-cells = <1>; 77 }; 78 79 clint_mswi: interrupt-controller@7094000000 { 80 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 81 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 82 interrupts-extended = <&cpu0_intc 3>, 83 <&cpu1_intc 3>, 84 <&cpu2_intc 3>, 85 <&cpu3_intc 3>, 86 <&cpu4_intc 3>, 87 <&cpu5_intc 3>, 88 <&cpu6_intc 3>, 89 <&cpu7_intc 3>, 90 <&cpu8_intc 3>, 91 <&cpu9_intc 3>, 92 <&cpu10_intc 3>, 93 <&cpu11_intc 3>, 94 <&cpu12_intc 3>, 95 <&cpu13_intc 3>, 96 <&cpu14_intc 3>, 97 <&cpu15_intc 3>, 98 <&cpu16_intc 3>, 99 <&cpu17_intc 3>, 100 <&cpu18_intc 3>, 101 <&cpu19_intc 3>, 102 <&cpu20_intc 3>, 103 <&cpu21_intc 3>, 104 <&cpu22_intc 3>, 105 <&cpu23_intc 3>, 106 <&cpu24_intc 3>, 107 <&cpu25_intc 3>, 108 <&cpu26_intc 3>, 109 <&cpu27_intc 3>, 110 <&cpu28_intc 3>, 111 <&cpu29_intc 3>, 112 <&cpu30_intc 3>, 113 <&cpu31_intc 3>, 114 <&cpu32_intc 3>, 115 <&cpu33_intc 3>, 116 <&cpu34_intc 3>, 117 <&cpu35_intc 3>, 118 <&cpu36_intc 3>, 119 <&cpu37_intc 3>, 120 <&cpu38_intc 3>, 121 <&cpu39_intc 3>, 122 <&cpu40_intc 3>, 123 <&cpu41_intc 3>, 124 <&cpu42_intc 3>, 125 <&cpu43_intc 3>, 126 <&cpu44_intc 3>, 127 <&cpu45_intc 3>, 128 <&cpu46_intc 3>, 129 <&cpu47_intc 3>, 130 <&cpu48_intc 3>, 131 <&cpu49_intc 3>, 132 <&cpu50_intc 3>, 133 <&cpu51_intc 3>, 134 <&cpu52_intc 3>, 135 <&cpu53_intc 3>, 136 <&cpu54_intc 3>, 137 <&cpu55_intc 3>, 138 <&cpu56_intc 3>, 139 <&cpu57_intc 3>, 140 <&cpu58_intc 3>, 141 <&cpu59_intc 3>, 142 <&cpu60_intc 3>, 143 <&cpu61_intc 3>, 144 <&cpu62_intc 3>, 145 <&cpu63_intc 3>; 146 }; 147 148 clint_mtimer0: timer@70ac004000 { 149 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 150 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; 151 reg-names = "mtimecmp"; 152 interrupts-extended = <&cpu0_intc 7>, 153 <&cpu1_intc 7>, 154 <&cpu2_intc 7>, 155 <&cpu3_intc 7>; 156 }; 157 158 clint_mtimer1: timer@70ac014000 { 159 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 160 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; 161 reg-names = "mtimecmp"; 162 interrupts-extended = <&cpu4_intc 7>, 163 <&cpu5_intc 7>, 164 <&cpu6_intc 7>, 165 <&cpu7_intc 7>; 166 }; 167 168 clint_mtimer2: timer@70ac024000 { 169 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 170 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; 171 reg-names = "mtimecmp"; 172 interrupts-extended = <&cpu8_intc 7>, 173 <&cpu9_intc 7>, 174 <&cpu10_intc 7>, 175 <&cpu11_intc 7>; 176 }; 177 178 clint_mtimer3: timer@70ac034000 { 179 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 180 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; 181 reg-names = "mtimecmp"; 182 interrupts-extended = <&cpu12_intc 7>, 183 <&cpu13_intc 7>, 184 <&cpu14_intc 7>, 185 <&cpu15_intc 7>; 186 }; 187 188 clint_mtimer4: timer@70ac044000 { 189 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 190 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; 191 reg-names = "mtimecmp"; 192 interrupts-extended = <&cpu16_intc 7>, 193 <&cpu17_intc 7>, 194 <&cpu18_intc 7>, 195 <&cpu19_intc 7>; 196 }; 197 198 clint_mtimer5: timer@70ac054000 { 199 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 200 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; 201 reg-names = "mtimecmp"; 202 interrupts-extended = <&cpu20_intc 7>, 203 <&cpu21_intc 7>, 204 <&cpu22_intc 7>, 205 <&cpu23_intc 7>; 206 }; 207 208 clint_mtimer6: timer@70ac064000 { 209 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 210 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; 211 reg-names = "mtimecmp"; 212 interrupts-extended = <&cpu24_intc 7>, 213 <&cpu25_intc 7>, 214 <&cpu26_intc 7>, 215 <&cpu27_intc 7>; 216 }; 217 218 clint_mtimer7: timer@70ac074000 { 219 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 220 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; 221 reg-names = "mtimecmp"; 222 interrupts-extended = <&cpu28_intc 7>, 223 <&cpu29_intc 7>, 224 <&cpu30_intc 7>, 225 <&cpu31_intc 7>; 226 }; 227 228 clint_mtimer8: timer@70ac084000 { 229 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 230 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; 231 reg-names = "mtimecmp"; 232 interrupts-extended = <&cpu32_intc 7>, 233 <&cpu33_intc 7>, 234 <&cpu34_intc 7>, 235 <&cpu35_intc 7>; 236 }; 237 238 clint_mtimer9: timer@70ac094000 { 239 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 240 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; 241 reg-names = "mtimecmp"; 242 interrupts-extended = <&cpu36_intc 7>, 243 <&cpu37_intc 7>, 244 <&cpu38_intc 7>, 245 <&cpu39_intc 7>; 246 }; 247 248 clint_mtimer10: timer@70ac0a4000 { 249 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 250 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; 251 reg-names = "mtimecmp"; 252 interrupts-extended = <&cpu40_intc 7>, 253 <&cpu41_intc 7>, 254 <&cpu42_intc 7>, 255 <&cpu43_intc 7>; 256 }; 257 258 clint_mtimer11: timer@70ac0b4000 { 259 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 260 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; 261 reg-names = "mtimecmp"; 262 interrupts-extended = <&cpu44_intc 7>, 263 <&cpu45_intc 7>, 264 <&cpu46_intc 7>, 265 <&cpu47_intc 7>; 266 }; 267 268 clint_mtimer12: timer@70ac0c4000 { 269 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 270 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; 271 reg-names = "mtimecmp"; 272 interrupts-extended = <&cpu48_intc 7>, 273 <&cpu49_intc 7>, 274 <&cpu50_intc 7>, 275 <&cpu51_intc 7>; 276 }; 277 278 clint_mtimer13: timer@70ac0d4000 { 279 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 280 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; 281 reg-names = "mtimecmp"; 282 interrupts-extended = <&cpu52_intc 7>, 283 <&cpu53_intc 7>, 284 <&cpu54_intc 7>, 285 <&cpu55_intc 7>; 286 }; 287 288 clint_mtimer14: timer@70ac0e4000 { 289 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 290 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; 291 reg-names = "mtimecmp"; 292 interrupts-extended = <&cpu56_intc 7>, 293 <&cpu57_intc 7>, 294 <&cpu58_intc 7>, 295 <&cpu59_intc 7>; 296 }; 297 298 clint_mtimer15: timer@70ac0f4000 { 299 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 300 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; 301 reg-names = "mtimecmp"; 302 interrupts-extended = <&cpu60_intc 7>, 303 <&cpu61_intc 7>, 304 <&cpu62_intc 7>, 305 <&cpu63_intc 7>; 306 }; 307 308 intc: interrupt-controller@7090000000 { 309 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 310 #address-cells = <0>; 311 #interrupt-cells = <2>; 312 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 313 interrupt-controller; 314 interrupts-extended = 315 <&cpu0_intc 11>, <&cpu0_intc 9>, 316 <&cpu1_intc 11>, <&cpu1_intc 9>, 317 <&cpu2_intc 11>, <&cpu2_intc 9>, 318 <&cpu3_intc 11>, <&cpu3_intc 9>, 319 <&cpu4_intc 11>, <&cpu4_intc 9>, 320 <&cpu5_intc 11>, <&cpu5_intc 9>, 321 <&cpu6_intc 11>, <&cpu6_intc 9>, 322 <&cpu7_intc 11>, <&cpu7_intc 9>, 323 <&cpu8_intc 11>, <&cpu8_intc 9>, 324 <&cpu9_intc 11>, <&cpu9_intc 9>, 325 <&cpu10_intc 11>, <&cpu10_intc 9>, 326 <&cpu11_intc 11>, <&cpu11_intc 9>, 327 <&cpu12_intc 11>, <&cpu12_intc 9>, 328 <&cpu13_intc 11>, <&cpu13_intc 9>, 329 <&cpu14_intc 11>, <&cpu14_intc 9>, 330 <&cpu15_intc 11>, <&cpu15_intc 9>, 331 <&cpu16_intc 11>, <&cpu16_intc 9>, 332 <&cpu17_intc 11>, <&cpu17_intc 9>, 333 <&cpu18_intc 11>, <&cpu18_intc 9>, 334 <&cpu19_intc 11>, <&cpu19_intc 9>, 335 <&cpu20_intc 11>, <&cpu20_intc 9>, 336 <&cpu21_intc 11>, <&cpu21_intc 9>, 337 <&cpu22_intc 11>, <&cpu22_intc 9>, 338 <&cpu23_intc 11>, <&cpu23_intc 9>, 339 <&cpu24_intc 11>, <&cpu24_intc 9>, 340 <&cpu25_intc 11>, <&cpu25_intc 9>, 341 <&cpu26_intc 11>, <&cpu26_intc 9>, 342 <&cpu27_intc 11>, <&cpu27_intc 9>, 343 <&cpu28_intc 11>, <&cpu28_intc 9>, 344 <&cpu29_intc 11>, <&cpu29_intc 9>, 345 <&cpu30_intc 11>, <&cpu30_intc 9>, 346 <&cpu31_intc 11>, <&cpu31_intc 9>, 347 <&cpu32_intc 11>, <&cpu32_intc 9>, 348 <&cpu33_intc 11>, <&cpu33_intc 9>, 349 <&cpu34_intc 11>, <&cpu34_intc 9>, 350 <&cpu35_intc 11>, <&cpu35_intc 9>, 351 <&cpu36_intc 11>, <&cpu36_intc 9>, 352 <&cpu37_intc 11>, <&cpu37_intc 9>, 353 <&cpu38_intc 11>, <&cpu38_intc 9>, 354 <&cpu39_intc 11>, <&cpu39_intc 9>, 355 <&cpu40_intc 11>, <&cpu40_intc 9>, 356 <&cpu41_intc 11>, <&cpu41_intc 9>, 357 <&cpu42_intc 11>, <&cpu42_intc 9>, 358 <&cpu43_intc 11>, <&cpu43_intc 9>, 359 <&cpu44_intc 11>, <&cpu44_intc 9>, 360 <&cpu45_intc 11>, <&cpu45_intc 9>, 361 <&cpu46_intc 11>, <&cpu46_intc 9>, 362 <&cpu47_intc 11>, <&cpu47_intc 9>, 363 <&cpu48_intc 11>, <&cpu48_intc 9>, 364 <&cpu49_intc 11>, <&cpu49_intc 9>, 365 <&cpu50_intc 11>, <&cpu50_intc 9>, 366 <&cpu51_intc 11>, <&cpu51_intc 9>, 367 <&cpu52_intc 11>, <&cpu52_intc 9>, 368 <&cpu53_intc 11>, <&cpu53_intc 9>, 369 <&cpu54_intc 11>, <&cpu54_intc 9>, 370 <&cpu55_intc 11>, <&cpu55_intc 9>, 371 <&cpu56_intc 11>, <&cpu56_intc 9>, 372 <&cpu57_intc 11>, <&cpu57_intc 9>, 373 <&cpu58_intc 11>, <&cpu58_intc 9>, 374 <&cpu59_intc 11>, <&cpu59_intc 9>, 375 <&cpu60_intc 11>, <&cpu60_intc 9>, 376 <&cpu61_intc 11>, <&cpu61_intc 9>, 377 <&cpu62_intc 11>, <&cpu62_intc 9>, 378 <&cpu63_intc 11>, <&cpu63_intc 9>; 379 riscv,ndev = <224>; 380 }; 381 382 rstgen: reset-controller@7030013000 { 383 compatible = "sophgo,sg2042-reset"; 384 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; 385 #reset-cells = <1>; 386 }; 387 388 uart0: serial@7040000000 { 389 compatible = "snps,dw-apb-uart"; 390 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; 391 interrupt-parent = <&intc>; 392 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 393 clock-frequency = <500000000>; 394 clocks = <&clkgen GATE_CLK_UART_500M>, 395 <&clkgen GATE_CLK_APB_UART>; 396 clock-names = "baudclk", "apb_pclk"; 397 reg-shift = <2>; 398 reg-io-width = <4>; 399 resets = <&rstgen RST_UART0>; 400 status = "disabled"; 401 }; 402 }; 403}; 404