1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> 8#include <dt-bindings/clock/sophgo,sg2042-pll.h> 9#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/pinctrl-sg2042.h> 12#include <dt-bindings/reset/sophgo,sg2042-reset.h> 13 14#include "sg2042-cpus.dtsi" 15 16/ { 17 compatible = "sophgo,sg2042"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 dma-noncoherent; 21 22 distance-map { 23 compatible = "numa-distance-map-v1"; 24 distance-matrix = <0 0 10>, 25 <0 1 15>, 26 <0 2 25>, 27 <0 3 30>, 28 <1 0 15>, 29 <1 1 10>, 30 <1 2 30>, 31 <1 3 25>, 32 <2 0 25>, 33 <2 1 30>, 34 <2 2 10>, 35 <2 3 15>, 36 <3 0 30>, 37 <3 1 25>, 38 <3 2 15>, 39 <3 3 10>; 40 }; 41 42 aliases { 43 serial0 = &uart0; 44 }; 45 46 cgi_main: oscillator0 { 47 compatible = "fixed-clock"; 48 clock-output-names = "cgi_main"; 49 #clock-cells = <0>; 50 }; 51 52 cgi_dpll0: oscillator1 { 53 compatible = "fixed-clock"; 54 clock-output-names = "cgi_dpll0"; 55 #clock-cells = <0>; 56 }; 57 58 cgi_dpll1: oscillator2 { 59 compatible = "fixed-clock"; 60 clock-output-names = "cgi_dpll1"; 61 #clock-cells = <0>; 62 }; 63 64 soc: soc { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 interrupt-parent = <&intc>; 69 ranges; 70 71 i2c0: i2c@7030005000 { 72 compatible = "snps,designware-i2c"; 73 reg = <0x70 0x30005000 0x0 0x1000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 clocks = <&clkgen GATE_CLK_APB_I2C>; 77 clock-names = "ref"; 78 clock-frequency = <100000>; 79 interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; 80 resets = <&rstgen RST_I2C0>; 81 status = "disabled"; 82 }; 83 84 i2c1: i2c@7030006000 { 85 compatible = "snps,designware-i2c"; 86 reg = <0x70 0x30006000 0x0 0x1000>; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 clocks = <&clkgen GATE_CLK_APB_I2C>; 90 clock-names = "ref"; 91 clock-frequency = <100000>; 92 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; 93 resets = <&rstgen RST_I2C1>; 94 status = "disabled"; 95 }; 96 97 i2c2: i2c@7030007000 { 98 compatible = "snps,designware-i2c"; 99 reg = <0x70 0x30007000 0x0 0x1000>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 clocks = <&clkgen GATE_CLK_APB_I2C>; 103 clock-names = "ref"; 104 clock-frequency = <100000>; 105 interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; 106 resets = <&rstgen RST_I2C2>; 107 status = "disabled"; 108 }; 109 110 i2c3: i2c@7030008000 { 111 compatible = "snps,designware-i2c"; 112 reg = <0x70 0x30008000 0x0 0x1000>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 clocks = <&clkgen GATE_CLK_APB_I2C>; 116 clock-names = "ref"; 117 clock-frequency = <100000>; 118 interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; 119 resets = <&rstgen RST_I2C3>; 120 status = "disabled"; 121 }; 122 123 gpio0: gpio@7030009000 { 124 compatible = "snps,dw-apb-gpio"; 125 reg = <0x70 0x30009000 0x0 0x400>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&clkgen GATE_CLK_APB_GPIO>, 129 <&clkgen GATE_CLK_GPIO_DB>; 130 clock-names = "bus", "db"; 131 132 port0a: gpio-controller@0 { 133 compatible = "snps,dw-apb-gpio-port"; 134 gpio-controller; 135 #gpio-cells = <2>; 136 ngpios = <32>; 137 reg = <0>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 interrupt-parent = <&intc>; 141 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; 142 }; 143 }; 144 145 gpio1: gpio@703000a000 { 146 compatible = "snps,dw-apb-gpio"; 147 reg = <0x70 0x3000a000 0x0 0x400>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 clocks = <&clkgen GATE_CLK_APB_GPIO>, 151 <&clkgen GATE_CLK_GPIO_DB>; 152 clock-names = "bus", "db"; 153 154 port1a: gpio-controller@0 { 155 compatible = "snps,dw-apb-gpio-port"; 156 gpio-controller; 157 #gpio-cells = <2>; 158 ngpios = <32>; 159 reg = <0>; 160 interrupt-controller; 161 #interrupt-cells = <2>; 162 interrupt-parent = <&intc>; 163 interrupts = <97 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 }; 166 167 gpio2: gpio@703000b000 { 168 compatible = "snps,dw-apb-gpio"; 169 reg = <0x70 0x3000b000 0x0 0x400>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 clocks = <&clkgen GATE_CLK_APB_GPIO>, 173 <&clkgen GATE_CLK_GPIO_DB>; 174 clock-names = "bus", "db"; 175 176 port2a: gpio-controller@0 { 177 compatible = "snps,dw-apb-gpio-port"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 ngpios = <32>; 181 reg = <0>; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 interrupt-parent = <&intc>; 185 interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; 186 }; 187 }; 188 189 pwm: pwm@703000c000 { 190 compatible = "sophgo,sg2042-pwm"; 191 reg = <0x70 0x3000c000 0x0 0x20>; 192 #pwm-cells = <3>; 193 clocks = <&clkgen GATE_CLK_APB_PWM>; 194 clock-names = "apb"; 195 resets = <&rstgen RST_PWM>; 196 }; 197 198 pllclk: clock-controller@70300100c0 { 199 compatible = "sophgo,sg2042-pll"; 200 reg = <0x70 0x300100c0 0x0 0x40>; 201 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; 202 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; 203 #clock-cells = <1>; 204 }; 205 206 msi: msi-controller@7030010304 { 207 compatible = "sophgo,sg2042-msi"; 208 reg = <0x70 0x30010304 0x0 0x4>, 209 <0x70 0x30010300 0x0 0x4>; 210 reg-names = "clr", "doorbell"; 211 msi-controller; 212 #msi-cells = <0>; 213 msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; 214 }; 215 216 rpgate: clock-controller@7030010368 { 217 compatible = "sophgo,sg2042-rpgate"; 218 reg = <0x70 0x30010368 0x0 0x98>; 219 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; 220 clock-names = "rpgate"; 221 #clock-cells = <1>; 222 }; 223 224 pinctrl: pinctrl@7030011000 { 225 compatible = "sophgo,sg2042-pinctrl"; 226 reg = <0x70 0x30011000 0x0 0x1000>; 227 }; 228 229 clkgen: clock-controller@7030012000 { 230 compatible = "sophgo,sg2042-clkgen"; 231 reg = <0x70 0x30012000 0x0 0x1000>; 232 clocks = <&pllclk MPLL_CLK>, 233 <&pllclk FPLL_CLK>, 234 <&pllclk DPLL0_CLK>, 235 <&pllclk DPLL1_CLK>; 236 clock-names = "mpll", 237 "fpll", 238 "dpll0", 239 "dpll1"; 240 #clock-cells = <1>; 241 }; 242 243 clint_mswi: interrupt-controller@7094000000 { 244 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 245 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 246 interrupts-extended = <&cpu0_intc 3>, 247 <&cpu1_intc 3>, 248 <&cpu2_intc 3>, 249 <&cpu3_intc 3>, 250 <&cpu4_intc 3>, 251 <&cpu5_intc 3>, 252 <&cpu6_intc 3>, 253 <&cpu7_intc 3>, 254 <&cpu8_intc 3>, 255 <&cpu9_intc 3>, 256 <&cpu10_intc 3>, 257 <&cpu11_intc 3>, 258 <&cpu12_intc 3>, 259 <&cpu13_intc 3>, 260 <&cpu14_intc 3>, 261 <&cpu15_intc 3>, 262 <&cpu16_intc 3>, 263 <&cpu17_intc 3>, 264 <&cpu18_intc 3>, 265 <&cpu19_intc 3>, 266 <&cpu20_intc 3>, 267 <&cpu21_intc 3>, 268 <&cpu22_intc 3>, 269 <&cpu23_intc 3>, 270 <&cpu24_intc 3>, 271 <&cpu25_intc 3>, 272 <&cpu26_intc 3>, 273 <&cpu27_intc 3>, 274 <&cpu28_intc 3>, 275 <&cpu29_intc 3>, 276 <&cpu30_intc 3>, 277 <&cpu31_intc 3>, 278 <&cpu32_intc 3>, 279 <&cpu33_intc 3>, 280 <&cpu34_intc 3>, 281 <&cpu35_intc 3>, 282 <&cpu36_intc 3>, 283 <&cpu37_intc 3>, 284 <&cpu38_intc 3>, 285 <&cpu39_intc 3>, 286 <&cpu40_intc 3>, 287 <&cpu41_intc 3>, 288 <&cpu42_intc 3>, 289 <&cpu43_intc 3>, 290 <&cpu44_intc 3>, 291 <&cpu45_intc 3>, 292 <&cpu46_intc 3>, 293 <&cpu47_intc 3>, 294 <&cpu48_intc 3>, 295 <&cpu49_intc 3>, 296 <&cpu50_intc 3>, 297 <&cpu51_intc 3>, 298 <&cpu52_intc 3>, 299 <&cpu53_intc 3>, 300 <&cpu54_intc 3>, 301 <&cpu55_intc 3>, 302 <&cpu56_intc 3>, 303 <&cpu57_intc 3>, 304 <&cpu58_intc 3>, 305 <&cpu59_intc 3>, 306 <&cpu60_intc 3>, 307 <&cpu61_intc 3>, 308 <&cpu62_intc 3>, 309 <&cpu63_intc 3>; 310 }; 311 312 clint_mtimer0: timer@70ac004000 { 313 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 314 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; 315 reg-names = "mtimecmp"; 316 interrupts-extended = <&cpu0_intc 7>, 317 <&cpu1_intc 7>, 318 <&cpu2_intc 7>, 319 <&cpu3_intc 7>; 320 }; 321 322 clint_mtimer1: timer@70ac014000 { 323 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 324 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; 325 reg-names = "mtimecmp"; 326 interrupts-extended = <&cpu4_intc 7>, 327 <&cpu5_intc 7>, 328 <&cpu6_intc 7>, 329 <&cpu7_intc 7>; 330 }; 331 332 clint_mtimer2: timer@70ac024000 { 333 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 334 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; 335 reg-names = "mtimecmp"; 336 interrupts-extended = <&cpu8_intc 7>, 337 <&cpu9_intc 7>, 338 <&cpu10_intc 7>, 339 <&cpu11_intc 7>; 340 }; 341 342 clint_mtimer3: timer@70ac034000 { 343 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 344 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; 345 reg-names = "mtimecmp"; 346 interrupts-extended = <&cpu12_intc 7>, 347 <&cpu13_intc 7>, 348 <&cpu14_intc 7>, 349 <&cpu15_intc 7>; 350 }; 351 352 clint_mtimer4: timer@70ac044000 { 353 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 354 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; 355 reg-names = "mtimecmp"; 356 interrupts-extended = <&cpu16_intc 7>, 357 <&cpu17_intc 7>, 358 <&cpu18_intc 7>, 359 <&cpu19_intc 7>; 360 }; 361 362 clint_mtimer5: timer@70ac054000 { 363 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 364 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; 365 reg-names = "mtimecmp"; 366 interrupts-extended = <&cpu20_intc 7>, 367 <&cpu21_intc 7>, 368 <&cpu22_intc 7>, 369 <&cpu23_intc 7>; 370 }; 371 372 clint_mtimer6: timer@70ac064000 { 373 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 374 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; 375 reg-names = "mtimecmp"; 376 interrupts-extended = <&cpu24_intc 7>, 377 <&cpu25_intc 7>, 378 <&cpu26_intc 7>, 379 <&cpu27_intc 7>; 380 }; 381 382 clint_mtimer7: timer@70ac074000 { 383 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 384 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; 385 reg-names = "mtimecmp"; 386 interrupts-extended = <&cpu28_intc 7>, 387 <&cpu29_intc 7>, 388 <&cpu30_intc 7>, 389 <&cpu31_intc 7>; 390 }; 391 392 clint_mtimer8: timer@70ac084000 { 393 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 394 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; 395 reg-names = "mtimecmp"; 396 interrupts-extended = <&cpu32_intc 7>, 397 <&cpu33_intc 7>, 398 <&cpu34_intc 7>, 399 <&cpu35_intc 7>; 400 }; 401 402 clint_mtimer9: timer@70ac094000 { 403 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 404 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; 405 reg-names = "mtimecmp"; 406 interrupts-extended = <&cpu36_intc 7>, 407 <&cpu37_intc 7>, 408 <&cpu38_intc 7>, 409 <&cpu39_intc 7>; 410 }; 411 412 clint_mtimer10: timer@70ac0a4000 { 413 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 414 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; 415 reg-names = "mtimecmp"; 416 interrupts-extended = <&cpu40_intc 7>, 417 <&cpu41_intc 7>, 418 <&cpu42_intc 7>, 419 <&cpu43_intc 7>; 420 }; 421 422 clint_mtimer11: timer@70ac0b4000 { 423 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 424 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; 425 reg-names = "mtimecmp"; 426 interrupts-extended = <&cpu44_intc 7>, 427 <&cpu45_intc 7>, 428 <&cpu46_intc 7>, 429 <&cpu47_intc 7>; 430 }; 431 432 clint_mtimer12: timer@70ac0c4000 { 433 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 434 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; 435 reg-names = "mtimecmp"; 436 interrupts-extended = <&cpu48_intc 7>, 437 <&cpu49_intc 7>, 438 <&cpu50_intc 7>, 439 <&cpu51_intc 7>; 440 }; 441 442 clint_mtimer13: timer@70ac0d4000 { 443 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 444 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; 445 reg-names = "mtimecmp"; 446 interrupts-extended = <&cpu52_intc 7>, 447 <&cpu53_intc 7>, 448 <&cpu54_intc 7>, 449 <&cpu55_intc 7>; 450 }; 451 452 clint_mtimer14: timer@70ac0e4000 { 453 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 454 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; 455 reg-names = "mtimecmp"; 456 interrupts-extended = <&cpu56_intc 7>, 457 <&cpu57_intc 7>, 458 <&cpu58_intc 7>, 459 <&cpu59_intc 7>; 460 }; 461 462 clint_mtimer15: timer@70ac0f4000 { 463 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 464 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; 465 reg-names = "mtimecmp"; 466 interrupts-extended = <&cpu60_intc 7>, 467 <&cpu61_intc 7>, 468 <&cpu62_intc 7>, 469 <&cpu63_intc 7>; 470 }; 471 472 intc: interrupt-controller@7090000000 { 473 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 474 #address-cells = <0>; 475 #interrupt-cells = <2>; 476 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 477 interrupt-controller; 478 interrupts-extended = 479 <&cpu0_intc 11>, <&cpu0_intc 9>, 480 <&cpu1_intc 11>, <&cpu1_intc 9>, 481 <&cpu2_intc 11>, <&cpu2_intc 9>, 482 <&cpu3_intc 11>, <&cpu3_intc 9>, 483 <&cpu4_intc 11>, <&cpu4_intc 9>, 484 <&cpu5_intc 11>, <&cpu5_intc 9>, 485 <&cpu6_intc 11>, <&cpu6_intc 9>, 486 <&cpu7_intc 11>, <&cpu7_intc 9>, 487 <&cpu8_intc 11>, <&cpu8_intc 9>, 488 <&cpu9_intc 11>, <&cpu9_intc 9>, 489 <&cpu10_intc 11>, <&cpu10_intc 9>, 490 <&cpu11_intc 11>, <&cpu11_intc 9>, 491 <&cpu12_intc 11>, <&cpu12_intc 9>, 492 <&cpu13_intc 11>, <&cpu13_intc 9>, 493 <&cpu14_intc 11>, <&cpu14_intc 9>, 494 <&cpu15_intc 11>, <&cpu15_intc 9>, 495 <&cpu16_intc 11>, <&cpu16_intc 9>, 496 <&cpu17_intc 11>, <&cpu17_intc 9>, 497 <&cpu18_intc 11>, <&cpu18_intc 9>, 498 <&cpu19_intc 11>, <&cpu19_intc 9>, 499 <&cpu20_intc 11>, <&cpu20_intc 9>, 500 <&cpu21_intc 11>, <&cpu21_intc 9>, 501 <&cpu22_intc 11>, <&cpu22_intc 9>, 502 <&cpu23_intc 11>, <&cpu23_intc 9>, 503 <&cpu24_intc 11>, <&cpu24_intc 9>, 504 <&cpu25_intc 11>, <&cpu25_intc 9>, 505 <&cpu26_intc 11>, <&cpu26_intc 9>, 506 <&cpu27_intc 11>, <&cpu27_intc 9>, 507 <&cpu28_intc 11>, <&cpu28_intc 9>, 508 <&cpu29_intc 11>, <&cpu29_intc 9>, 509 <&cpu30_intc 11>, <&cpu30_intc 9>, 510 <&cpu31_intc 11>, <&cpu31_intc 9>, 511 <&cpu32_intc 11>, <&cpu32_intc 9>, 512 <&cpu33_intc 11>, <&cpu33_intc 9>, 513 <&cpu34_intc 11>, <&cpu34_intc 9>, 514 <&cpu35_intc 11>, <&cpu35_intc 9>, 515 <&cpu36_intc 11>, <&cpu36_intc 9>, 516 <&cpu37_intc 11>, <&cpu37_intc 9>, 517 <&cpu38_intc 11>, <&cpu38_intc 9>, 518 <&cpu39_intc 11>, <&cpu39_intc 9>, 519 <&cpu40_intc 11>, <&cpu40_intc 9>, 520 <&cpu41_intc 11>, <&cpu41_intc 9>, 521 <&cpu42_intc 11>, <&cpu42_intc 9>, 522 <&cpu43_intc 11>, <&cpu43_intc 9>, 523 <&cpu44_intc 11>, <&cpu44_intc 9>, 524 <&cpu45_intc 11>, <&cpu45_intc 9>, 525 <&cpu46_intc 11>, <&cpu46_intc 9>, 526 <&cpu47_intc 11>, <&cpu47_intc 9>, 527 <&cpu48_intc 11>, <&cpu48_intc 9>, 528 <&cpu49_intc 11>, <&cpu49_intc 9>, 529 <&cpu50_intc 11>, <&cpu50_intc 9>, 530 <&cpu51_intc 11>, <&cpu51_intc 9>, 531 <&cpu52_intc 11>, <&cpu52_intc 9>, 532 <&cpu53_intc 11>, <&cpu53_intc 9>, 533 <&cpu54_intc 11>, <&cpu54_intc 9>, 534 <&cpu55_intc 11>, <&cpu55_intc 9>, 535 <&cpu56_intc 11>, <&cpu56_intc 9>, 536 <&cpu57_intc 11>, <&cpu57_intc 9>, 537 <&cpu58_intc 11>, <&cpu58_intc 9>, 538 <&cpu59_intc 11>, <&cpu59_intc 9>, 539 <&cpu60_intc 11>, <&cpu60_intc 9>, 540 <&cpu61_intc 11>, <&cpu61_intc 9>, 541 <&cpu62_intc 11>, <&cpu62_intc 9>, 542 <&cpu63_intc 11>, <&cpu63_intc 9>; 543 riscv,ndev = <224>; 544 }; 545 546 rstgen: reset-controller@7030013000 { 547 compatible = "sophgo,sg2042-reset"; 548 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; 549 #reset-cells = <1>; 550 }; 551 552 uart0: serial@7040000000 { 553 compatible = "snps,dw-apb-uart"; 554 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; 555 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 556 clock-frequency = <500000000>; 557 clocks = <&clkgen GATE_CLK_UART_500M>, 558 <&clkgen GATE_CLK_APB_UART>; 559 clock-names = "baudclk", "apb_pclk"; 560 reg-shift = <2>; 561 reg-io-width = <4>; 562 resets = <&rstgen RST_UART0>; 563 status = "disabled"; 564 }; 565 566 spi0: spi@7040004000 { 567 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 568 reg = <0x70 0x40004000 0x00 0x1000>; 569 clocks = <&clkgen GATE_CLK_APB_SPI>; 570 interrupt-parent = <&intc>; 571 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 num-cs = <2>; 575 resets = <&rstgen RST_SPI0>; 576 status = "disabled"; 577 }; 578 579 spi1: spi@7040005000 { 580 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 581 reg = <0x70 0x40005000 0x00 0x1000>; 582 clocks = <&clkgen GATE_CLK_APB_SPI>; 583 interrupt-parent = <&intc>; 584 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 num-cs = <2>; 588 resets = <&rstgen RST_SPI1>; 589 status = "disabled"; 590 }; 591 592 gmac0: ethernet@7040026000 { 593 compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a"; 594 reg = <0x70 0x40026000 0x0 0x4000>; 595 clocks = <&clkgen GATE_CLK_AXI_ETH0>, 596 <&clkgen GATE_CLK_PTP_REF_I_ETH0>, 597 <&clkgen GATE_CLK_TX_ETH0>; 598 clock-names = "stmmaceth", "ptp_ref", "tx"; 599 dma-noncoherent; 600 interrupt-parent = <&intc>; 601 interrupts = <132 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "macirq"; 603 resets = <&rstgen RST_ETH0>; 604 reset-names = "stmmaceth"; 605 snps,multicast-filter-bins = <0>; 606 snps,perfect-filter-entries = <1>; 607 snps,aal; 608 snps,tso; 609 snps,txpbl = <32>; 610 snps,rxpbl = <32>; 611 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 612 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 613 snps,axi-config = <&gmac0_stmmac_axi_setup>; 614 status = "disabled"; 615 616 mdio { 617 compatible = "snps,dwmac-mdio"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 }; 621 622 gmac0_mtl_rx_setup: rx-queues-config { 623 snps,rx-queues-to-use = <8>; 624 queue0 {}; 625 queue1 {}; 626 queue2 {}; 627 queue3 {}; 628 queue4 {}; 629 queue5 {}; 630 queue6 {}; 631 queue7 {}; 632 }; 633 634 gmac0_mtl_tx_setup: tx-queues-config { 635 snps,tx-queues-to-use = <8>; 636 queue0 {}; 637 queue1 {}; 638 queue2 {}; 639 queue3 {}; 640 queue4 {}; 641 queue5 {}; 642 queue6 {}; 643 queue7 {}; 644 }; 645 646 gmac0_stmmac_axi_setup: stmmac-axi-config { 647 snps,blen = <16 8 4 0 0 0 0>; 648 snps,wr_osr_lmt = <1>; 649 snps,rd_osr_lmt = <2>; 650 }; 651 }; 652 653 emmc: mmc@704002a000 { 654 compatible = "sophgo,sg2042-dwcmshc"; 655 reg = <0x70 0x4002a000 0x0 0x1000>; 656 interrupt-parent = <&intc>; 657 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&clkgen GATE_CLK_EMMC_100M>, 659 <&clkgen GATE_CLK_AXI_EMMC>, 660 <&clkgen GATE_CLK_100K_EMMC>; 661 clock-names = "core", 662 "bus", 663 "timer"; 664 status = "disabled"; 665 }; 666 667 sd: mmc@704002b000 { 668 compatible = "sophgo,sg2042-dwcmshc"; 669 reg = <0x70 0x4002b000 0x0 0x1000>; 670 interrupt-parent = <&intc>; 671 interrupts = <136 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clkgen GATE_CLK_SD_100M>, 673 <&clkgen GATE_CLK_AXI_SD>, 674 <&clkgen GATE_CLK_100K_SD>; 675 clock-names = "core", 676 "bus", 677 "timer"; 678 status = "disabled"; 679 }; 680 }; 681}; 682