1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/interrupt-controller/irq.h> 8 9#include "sg2042-cpus.dtsi" 10 11/ { 12 compatible = "sophgo,sg2042"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 dma-noncoherent; 16 17 aliases { 18 serial0 = &uart0; 19 }; 20 21 soc: soc { 22 compatible = "simple-bus"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 clint_mswi: interrupt-controller@7094000000 { 28 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 29 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 30 interrupts-extended = <&cpu0_intc 3>, 31 <&cpu1_intc 3>, 32 <&cpu2_intc 3>, 33 <&cpu3_intc 3>, 34 <&cpu4_intc 3>, 35 <&cpu5_intc 3>, 36 <&cpu6_intc 3>, 37 <&cpu7_intc 3>, 38 <&cpu8_intc 3>, 39 <&cpu9_intc 3>, 40 <&cpu10_intc 3>, 41 <&cpu11_intc 3>, 42 <&cpu12_intc 3>, 43 <&cpu13_intc 3>, 44 <&cpu14_intc 3>, 45 <&cpu15_intc 3>, 46 <&cpu16_intc 3>, 47 <&cpu17_intc 3>, 48 <&cpu18_intc 3>, 49 <&cpu19_intc 3>, 50 <&cpu20_intc 3>, 51 <&cpu21_intc 3>, 52 <&cpu22_intc 3>, 53 <&cpu23_intc 3>, 54 <&cpu24_intc 3>, 55 <&cpu25_intc 3>, 56 <&cpu26_intc 3>, 57 <&cpu27_intc 3>, 58 <&cpu28_intc 3>, 59 <&cpu29_intc 3>, 60 <&cpu30_intc 3>, 61 <&cpu31_intc 3>, 62 <&cpu32_intc 3>, 63 <&cpu33_intc 3>, 64 <&cpu34_intc 3>, 65 <&cpu35_intc 3>, 66 <&cpu36_intc 3>, 67 <&cpu37_intc 3>, 68 <&cpu38_intc 3>, 69 <&cpu39_intc 3>, 70 <&cpu40_intc 3>, 71 <&cpu41_intc 3>, 72 <&cpu42_intc 3>, 73 <&cpu43_intc 3>, 74 <&cpu44_intc 3>, 75 <&cpu45_intc 3>, 76 <&cpu46_intc 3>, 77 <&cpu47_intc 3>, 78 <&cpu48_intc 3>, 79 <&cpu49_intc 3>, 80 <&cpu50_intc 3>, 81 <&cpu51_intc 3>, 82 <&cpu52_intc 3>, 83 <&cpu53_intc 3>, 84 <&cpu54_intc 3>, 85 <&cpu55_intc 3>, 86 <&cpu56_intc 3>, 87 <&cpu57_intc 3>, 88 <&cpu58_intc 3>, 89 <&cpu59_intc 3>, 90 <&cpu60_intc 3>, 91 <&cpu61_intc 3>, 92 <&cpu62_intc 3>, 93 <&cpu63_intc 3>; 94 }; 95 96 clint_mtimer0: timer@70ac000000 { 97 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 98 reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>; 99 interrupts-extended = <&cpu0_intc 7>, 100 <&cpu1_intc 7>, 101 <&cpu2_intc 7>, 102 <&cpu3_intc 7>; 103 }; 104 105 clint_mtimer1: timer@70ac010000 { 106 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 107 reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>; 108 interrupts-extended = <&cpu4_intc 7>, 109 <&cpu5_intc 7>, 110 <&cpu6_intc 7>, 111 <&cpu7_intc 7>; 112 }; 113 114 clint_mtimer2: timer@70ac020000 { 115 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 116 reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>; 117 interrupts-extended = <&cpu8_intc 7>, 118 <&cpu9_intc 7>, 119 <&cpu10_intc 7>, 120 <&cpu11_intc 7>; 121 }; 122 123 clint_mtimer3: timer@70ac030000 { 124 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 125 reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>; 126 interrupts-extended = <&cpu12_intc 7>, 127 <&cpu13_intc 7>, 128 <&cpu14_intc 7>, 129 <&cpu15_intc 7>; 130 }; 131 132 clint_mtimer4: timer@70ac040000 { 133 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 134 reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>; 135 interrupts-extended = <&cpu16_intc 7>, 136 <&cpu17_intc 7>, 137 <&cpu18_intc 7>, 138 <&cpu19_intc 7>; 139 }; 140 141 clint_mtimer5: timer@70ac050000 { 142 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 143 reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>; 144 interrupts-extended = <&cpu20_intc 7>, 145 <&cpu21_intc 7>, 146 <&cpu22_intc 7>, 147 <&cpu23_intc 7>; 148 }; 149 150 clint_mtimer6: timer@70ac060000 { 151 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 152 reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>; 153 interrupts-extended = <&cpu24_intc 7>, 154 <&cpu25_intc 7>, 155 <&cpu26_intc 7>, 156 <&cpu27_intc 7>; 157 }; 158 159 clint_mtimer7: timer@70ac070000 { 160 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 161 reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>; 162 interrupts-extended = <&cpu28_intc 7>, 163 <&cpu29_intc 7>, 164 <&cpu30_intc 7>, 165 <&cpu31_intc 7>; 166 }; 167 168 clint_mtimer8: timer@70ac080000 { 169 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 170 reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>; 171 interrupts-extended = <&cpu32_intc 7>, 172 <&cpu33_intc 7>, 173 <&cpu34_intc 7>, 174 <&cpu35_intc 7>; 175 }; 176 177 clint_mtimer9: timer@70ac090000 { 178 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 179 reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>; 180 interrupts-extended = <&cpu36_intc 7>, 181 <&cpu37_intc 7>, 182 <&cpu38_intc 7>, 183 <&cpu39_intc 7>; 184 }; 185 186 clint_mtimer10: timer@70ac0a0000 { 187 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 188 reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; 189 interrupts-extended = <&cpu40_intc 7>, 190 <&cpu41_intc 7>, 191 <&cpu42_intc 7>, 192 <&cpu43_intc 7>; 193 }; 194 195 clint_mtimer11: timer@70ac0b0000 { 196 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 197 reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; 198 interrupts-extended = <&cpu44_intc 7>, 199 <&cpu45_intc 7>, 200 <&cpu46_intc 7>, 201 <&cpu47_intc 7>; 202 }; 203 204 clint_mtimer12: timer@70ac0c0000 { 205 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 206 reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; 207 interrupts-extended = <&cpu48_intc 7>, 208 <&cpu49_intc 7>, 209 <&cpu50_intc 7>, 210 <&cpu51_intc 7>; 211 }; 212 213 clint_mtimer13: timer@70ac0d0000 { 214 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 215 reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; 216 interrupts-extended = <&cpu52_intc 7>, 217 <&cpu53_intc 7>, 218 <&cpu54_intc 7>, 219 <&cpu55_intc 7>; 220 }; 221 222 clint_mtimer14: timer@70ac0e0000 { 223 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 224 reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; 225 interrupts-extended = <&cpu56_intc 7>, 226 <&cpu57_intc 7>, 227 <&cpu58_intc 7>, 228 <&cpu59_intc 7>; 229 }; 230 231 clint_mtimer15: timer@70ac0f0000 { 232 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 233 reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; 234 interrupts-extended = <&cpu60_intc 7>, 235 <&cpu61_intc 7>, 236 <&cpu62_intc 7>, 237 <&cpu63_intc 7>; 238 }; 239 240 intc: interrupt-controller@7090000000 { 241 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 242 #address-cells = <0>; 243 #interrupt-cells = <2>; 244 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 245 interrupt-controller; 246 interrupts-extended = 247 <&cpu0_intc 11>, <&cpu0_intc 9>, 248 <&cpu1_intc 11>, <&cpu1_intc 9>, 249 <&cpu2_intc 11>, <&cpu2_intc 9>, 250 <&cpu3_intc 11>, <&cpu3_intc 9>, 251 <&cpu4_intc 11>, <&cpu4_intc 9>, 252 <&cpu5_intc 11>, <&cpu5_intc 9>, 253 <&cpu6_intc 11>, <&cpu6_intc 9>, 254 <&cpu7_intc 11>, <&cpu7_intc 9>, 255 <&cpu8_intc 11>, <&cpu8_intc 9>, 256 <&cpu9_intc 11>, <&cpu9_intc 9>, 257 <&cpu10_intc 11>, <&cpu10_intc 9>, 258 <&cpu11_intc 11>, <&cpu11_intc 9>, 259 <&cpu12_intc 11>, <&cpu12_intc 9>, 260 <&cpu13_intc 11>, <&cpu13_intc 9>, 261 <&cpu14_intc 11>, <&cpu14_intc 9>, 262 <&cpu15_intc 11>, <&cpu15_intc 9>, 263 <&cpu16_intc 11>, <&cpu16_intc 9>, 264 <&cpu17_intc 11>, <&cpu17_intc 9>, 265 <&cpu18_intc 11>, <&cpu18_intc 9>, 266 <&cpu19_intc 11>, <&cpu19_intc 9>, 267 <&cpu20_intc 11>, <&cpu20_intc 9>, 268 <&cpu21_intc 11>, <&cpu21_intc 9>, 269 <&cpu22_intc 11>, <&cpu22_intc 9>, 270 <&cpu23_intc 11>, <&cpu23_intc 9>, 271 <&cpu24_intc 11>, <&cpu24_intc 9>, 272 <&cpu25_intc 11>, <&cpu25_intc 9>, 273 <&cpu26_intc 11>, <&cpu26_intc 9>, 274 <&cpu27_intc 11>, <&cpu27_intc 9>, 275 <&cpu28_intc 11>, <&cpu28_intc 9>, 276 <&cpu29_intc 11>, <&cpu29_intc 9>, 277 <&cpu30_intc 11>, <&cpu30_intc 9>, 278 <&cpu31_intc 11>, <&cpu31_intc 9>, 279 <&cpu32_intc 11>, <&cpu32_intc 9>, 280 <&cpu33_intc 11>, <&cpu33_intc 9>, 281 <&cpu34_intc 11>, <&cpu34_intc 9>, 282 <&cpu35_intc 11>, <&cpu35_intc 9>, 283 <&cpu36_intc 11>, <&cpu36_intc 9>, 284 <&cpu37_intc 11>, <&cpu37_intc 9>, 285 <&cpu38_intc 11>, <&cpu38_intc 9>, 286 <&cpu39_intc 11>, <&cpu39_intc 9>, 287 <&cpu40_intc 11>, <&cpu40_intc 9>, 288 <&cpu41_intc 11>, <&cpu41_intc 9>, 289 <&cpu42_intc 11>, <&cpu42_intc 9>, 290 <&cpu43_intc 11>, <&cpu43_intc 9>, 291 <&cpu44_intc 11>, <&cpu44_intc 9>, 292 <&cpu45_intc 11>, <&cpu45_intc 9>, 293 <&cpu46_intc 11>, <&cpu46_intc 9>, 294 <&cpu47_intc 11>, <&cpu47_intc 9>, 295 <&cpu48_intc 11>, <&cpu48_intc 9>, 296 <&cpu49_intc 11>, <&cpu49_intc 9>, 297 <&cpu50_intc 11>, <&cpu50_intc 9>, 298 <&cpu51_intc 11>, <&cpu51_intc 9>, 299 <&cpu52_intc 11>, <&cpu52_intc 9>, 300 <&cpu53_intc 11>, <&cpu53_intc 9>, 301 <&cpu54_intc 11>, <&cpu54_intc 9>, 302 <&cpu55_intc 11>, <&cpu55_intc 9>, 303 <&cpu56_intc 11>, <&cpu56_intc 9>, 304 <&cpu57_intc 11>, <&cpu57_intc 9>, 305 <&cpu58_intc 11>, <&cpu58_intc 9>, 306 <&cpu59_intc 11>, <&cpu59_intc 9>, 307 <&cpu60_intc 11>, <&cpu60_intc 9>, 308 <&cpu61_intc 11>, <&cpu61_intc 9>, 309 <&cpu62_intc 11>, <&cpu62_intc 9>, 310 <&cpu63_intc 11>, <&cpu63_intc 9>; 311 riscv,ndev = <224>; 312 }; 313 314 uart0: serial@7040000000 { 315 compatible = "snps,dw-apb-uart"; 316 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; 317 interrupt-parent = <&intc>; 318 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 319 clock-frequency = <500000000>; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 status = "disabled"; 323 }; 324 }; 325}; 326