xref: /linux/arch/riscv/boot/dts/sophgo/sg2042.dtsi (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
4 */
5
6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
8
9#include <dt-bindings/reset/sophgo,sg2042-reset.h>
10
11#include "sg2042-cpus.dtsi"
12
13/ {
14	compatible = "sophgo,sg2042";
15	#address-cells = <2>;
16	#size-cells = <2>;
17	dma-noncoherent;
18
19	aliases {
20		serial0 = &uart0;
21	};
22
23	soc: soc {
24		compatible = "simple-bus";
25		#address-cells = <2>;
26		#size-cells = <2>;
27		ranges;
28
29		clint_mswi: interrupt-controller@7094000000 {
30			compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
31			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
32			interrupts-extended = <&cpu0_intc 3>,
33					      <&cpu1_intc 3>,
34					      <&cpu2_intc 3>,
35					      <&cpu3_intc 3>,
36					      <&cpu4_intc 3>,
37					      <&cpu5_intc 3>,
38					      <&cpu6_intc 3>,
39					      <&cpu7_intc 3>,
40					      <&cpu8_intc 3>,
41					      <&cpu9_intc 3>,
42					      <&cpu10_intc 3>,
43					      <&cpu11_intc 3>,
44					      <&cpu12_intc 3>,
45					      <&cpu13_intc 3>,
46					      <&cpu14_intc 3>,
47					      <&cpu15_intc 3>,
48					      <&cpu16_intc 3>,
49					      <&cpu17_intc 3>,
50					      <&cpu18_intc 3>,
51					      <&cpu19_intc 3>,
52					      <&cpu20_intc 3>,
53					      <&cpu21_intc 3>,
54					      <&cpu22_intc 3>,
55					      <&cpu23_intc 3>,
56					      <&cpu24_intc 3>,
57					      <&cpu25_intc 3>,
58					      <&cpu26_intc 3>,
59					      <&cpu27_intc 3>,
60					      <&cpu28_intc 3>,
61					      <&cpu29_intc 3>,
62					      <&cpu30_intc 3>,
63					      <&cpu31_intc 3>,
64					      <&cpu32_intc 3>,
65					      <&cpu33_intc 3>,
66					      <&cpu34_intc 3>,
67					      <&cpu35_intc 3>,
68					      <&cpu36_intc 3>,
69					      <&cpu37_intc 3>,
70					      <&cpu38_intc 3>,
71					      <&cpu39_intc 3>,
72					      <&cpu40_intc 3>,
73					      <&cpu41_intc 3>,
74					      <&cpu42_intc 3>,
75					      <&cpu43_intc 3>,
76					      <&cpu44_intc 3>,
77					      <&cpu45_intc 3>,
78					      <&cpu46_intc 3>,
79					      <&cpu47_intc 3>,
80					      <&cpu48_intc 3>,
81					      <&cpu49_intc 3>,
82					      <&cpu50_intc 3>,
83					      <&cpu51_intc 3>,
84					      <&cpu52_intc 3>,
85					      <&cpu53_intc 3>,
86					      <&cpu54_intc 3>,
87					      <&cpu55_intc 3>,
88					      <&cpu56_intc 3>,
89					      <&cpu57_intc 3>,
90					      <&cpu58_intc 3>,
91					      <&cpu59_intc 3>,
92					      <&cpu60_intc 3>,
93					      <&cpu61_intc 3>,
94					      <&cpu62_intc 3>,
95					      <&cpu63_intc 3>;
96		};
97
98		clint_mtimer0: timer@70ac004000 {
99			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
100			reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
101			reg-names = "mtimecmp";
102			interrupts-extended = <&cpu0_intc 7>,
103					      <&cpu1_intc 7>,
104					      <&cpu2_intc 7>,
105					      <&cpu3_intc 7>;
106		};
107
108		clint_mtimer1: timer@70ac014000 {
109			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
110			reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
111			reg-names = "mtimecmp";
112			interrupts-extended = <&cpu4_intc 7>,
113					      <&cpu5_intc 7>,
114					      <&cpu6_intc 7>,
115					      <&cpu7_intc 7>;
116		};
117
118		clint_mtimer2: timer@70ac024000 {
119			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
120			reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
121			reg-names = "mtimecmp";
122			interrupts-extended = <&cpu8_intc 7>,
123					      <&cpu9_intc 7>,
124					      <&cpu10_intc 7>,
125					      <&cpu11_intc 7>;
126		};
127
128		clint_mtimer3: timer@70ac034000 {
129			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
130			reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
131			reg-names = "mtimecmp";
132			interrupts-extended = <&cpu12_intc 7>,
133					      <&cpu13_intc 7>,
134					      <&cpu14_intc 7>,
135					      <&cpu15_intc 7>;
136		};
137
138		clint_mtimer4: timer@70ac044000 {
139			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
140			reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
141			reg-names = "mtimecmp";
142			interrupts-extended = <&cpu16_intc 7>,
143					      <&cpu17_intc 7>,
144					      <&cpu18_intc 7>,
145					      <&cpu19_intc 7>;
146		};
147
148		clint_mtimer5: timer@70ac054000 {
149			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
150			reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
151			reg-names = "mtimecmp";
152			interrupts-extended = <&cpu20_intc 7>,
153					      <&cpu21_intc 7>,
154					      <&cpu22_intc 7>,
155					      <&cpu23_intc 7>;
156		};
157
158		clint_mtimer6: timer@70ac064000 {
159			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
160			reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
161			reg-names = "mtimecmp";
162			interrupts-extended = <&cpu24_intc 7>,
163					      <&cpu25_intc 7>,
164					      <&cpu26_intc 7>,
165					      <&cpu27_intc 7>;
166		};
167
168		clint_mtimer7: timer@70ac074000 {
169			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
170			reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
171			reg-names = "mtimecmp";
172			interrupts-extended = <&cpu28_intc 7>,
173					      <&cpu29_intc 7>,
174					      <&cpu30_intc 7>,
175					      <&cpu31_intc 7>;
176		};
177
178		clint_mtimer8: timer@70ac084000 {
179			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
180			reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
181			reg-names = "mtimecmp";
182			interrupts-extended = <&cpu32_intc 7>,
183					      <&cpu33_intc 7>,
184					      <&cpu34_intc 7>,
185					      <&cpu35_intc 7>;
186		};
187
188		clint_mtimer9: timer@70ac094000 {
189			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
190			reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
191			reg-names = "mtimecmp";
192			interrupts-extended = <&cpu36_intc 7>,
193					      <&cpu37_intc 7>,
194					      <&cpu38_intc 7>,
195					      <&cpu39_intc 7>;
196		};
197
198		clint_mtimer10: timer@70ac0a4000 {
199			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
200			reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
201			reg-names = "mtimecmp";
202			interrupts-extended = <&cpu40_intc 7>,
203					      <&cpu41_intc 7>,
204					      <&cpu42_intc 7>,
205					      <&cpu43_intc 7>;
206		};
207
208		clint_mtimer11: timer@70ac0b4000 {
209			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
210			reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
211			reg-names = "mtimecmp";
212			interrupts-extended = <&cpu44_intc 7>,
213					      <&cpu45_intc 7>,
214					      <&cpu46_intc 7>,
215					      <&cpu47_intc 7>;
216		};
217
218		clint_mtimer12: timer@70ac0c4000 {
219			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
220			reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
221			reg-names = "mtimecmp";
222			interrupts-extended = <&cpu48_intc 7>,
223					      <&cpu49_intc 7>,
224					      <&cpu50_intc 7>,
225					      <&cpu51_intc 7>;
226		};
227
228		clint_mtimer13: timer@70ac0d4000 {
229			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
230			reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
231			reg-names = "mtimecmp";
232			interrupts-extended = <&cpu52_intc 7>,
233					      <&cpu53_intc 7>,
234					      <&cpu54_intc 7>,
235					      <&cpu55_intc 7>;
236		};
237
238		clint_mtimer14: timer@70ac0e4000 {
239			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
240			reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
241			reg-names = "mtimecmp";
242			interrupts-extended = <&cpu56_intc 7>,
243					      <&cpu57_intc 7>,
244					      <&cpu58_intc 7>,
245					      <&cpu59_intc 7>;
246		};
247
248		clint_mtimer15: timer@70ac0f4000 {
249			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
250			reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
251			reg-names = "mtimecmp";
252			interrupts-extended = <&cpu60_intc 7>,
253					      <&cpu61_intc 7>,
254					      <&cpu62_intc 7>,
255					      <&cpu63_intc 7>;
256		};
257
258		intc: interrupt-controller@7090000000 {
259			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
260			#address-cells = <0>;
261			#interrupt-cells = <2>;
262			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
263			interrupt-controller;
264			interrupts-extended =
265				<&cpu0_intc 11>,  <&cpu0_intc 9>,
266				<&cpu1_intc 11>,  <&cpu1_intc 9>,
267				<&cpu2_intc 11>,  <&cpu2_intc 9>,
268				<&cpu3_intc 11>,  <&cpu3_intc 9>,
269				<&cpu4_intc 11>,  <&cpu4_intc 9>,
270				<&cpu5_intc 11>,  <&cpu5_intc 9>,
271				<&cpu6_intc 11>,  <&cpu6_intc 9>,
272				<&cpu7_intc 11>,  <&cpu7_intc 9>,
273				<&cpu8_intc 11>,  <&cpu8_intc 9>,
274				<&cpu9_intc 11>,  <&cpu9_intc 9>,
275				<&cpu10_intc 11>, <&cpu10_intc 9>,
276				<&cpu11_intc 11>, <&cpu11_intc 9>,
277				<&cpu12_intc 11>, <&cpu12_intc 9>,
278				<&cpu13_intc 11>, <&cpu13_intc 9>,
279				<&cpu14_intc 11>, <&cpu14_intc 9>,
280				<&cpu15_intc 11>, <&cpu15_intc 9>,
281				<&cpu16_intc 11>, <&cpu16_intc 9>,
282				<&cpu17_intc 11>, <&cpu17_intc 9>,
283				<&cpu18_intc 11>, <&cpu18_intc 9>,
284				<&cpu19_intc 11>, <&cpu19_intc 9>,
285				<&cpu20_intc 11>, <&cpu20_intc 9>,
286				<&cpu21_intc 11>, <&cpu21_intc 9>,
287				<&cpu22_intc 11>, <&cpu22_intc 9>,
288				<&cpu23_intc 11>, <&cpu23_intc 9>,
289				<&cpu24_intc 11>, <&cpu24_intc 9>,
290				<&cpu25_intc 11>, <&cpu25_intc 9>,
291				<&cpu26_intc 11>, <&cpu26_intc 9>,
292				<&cpu27_intc 11>, <&cpu27_intc 9>,
293				<&cpu28_intc 11>, <&cpu28_intc 9>,
294				<&cpu29_intc 11>, <&cpu29_intc 9>,
295				<&cpu30_intc 11>, <&cpu30_intc 9>,
296				<&cpu31_intc 11>, <&cpu31_intc 9>,
297				<&cpu32_intc 11>, <&cpu32_intc 9>,
298				<&cpu33_intc 11>, <&cpu33_intc 9>,
299				<&cpu34_intc 11>, <&cpu34_intc 9>,
300				<&cpu35_intc 11>, <&cpu35_intc 9>,
301				<&cpu36_intc 11>, <&cpu36_intc 9>,
302				<&cpu37_intc 11>, <&cpu37_intc 9>,
303				<&cpu38_intc 11>, <&cpu38_intc 9>,
304				<&cpu39_intc 11>, <&cpu39_intc 9>,
305				<&cpu40_intc 11>, <&cpu40_intc 9>,
306				<&cpu41_intc 11>, <&cpu41_intc 9>,
307				<&cpu42_intc 11>, <&cpu42_intc 9>,
308				<&cpu43_intc 11>, <&cpu43_intc 9>,
309				<&cpu44_intc 11>, <&cpu44_intc 9>,
310				<&cpu45_intc 11>, <&cpu45_intc 9>,
311				<&cpu46_intc 11>, <&cpu46_intc 9>,
312				<&cpu47_intc 11>, <&cpu47_intc 9>,
313				<&cpu48_intc 11>, <&cpu48_intc 9>,
314				<&cpu49_intc 11>, <&cpu49_intc 9>,
315				<&cpu50_intc 11>, <&cpu50_intc 9>,
316				<&cpu51_intc 11>, <&cpu51_intc 9>,
317				<&cpu52_intc 11>, <&cpu52_intc 9>,
318				<&cpu53_intc 11>, <&cpu53_intc 9>,
319				<&cpu54_intc 11>, <&cpu54_intc 9>,
320				<&cpu55_intc 11>, <&cpu55_intc 9>,
321				<&cpu56_intc 11>, <&cpu56_intc 9>,
322				<&cpu57_intc 11>, <&cpu57_intc 9>,
323				<&cpu58_intc 11>, <&cpu58_intc 9>,
324				<&cpu59_intc 11>, <&cpu59_intc 9>,
325				<&cpu60_intc 11>, <&cpu60_intc 9>,
326				<&cpu61_intc 11>, <&cpu61_intc 9>,
327				<&cpu62_intc 11>, <&cpu62_intc 9>,
328				<&cpu63_intc 11>, <&cpu63_intc 9>;
329			riscv,ndev = <224>;
330		};
331
332		rstgen: reset-controller@7030013000 {
333			compatible = "sophgo,sg2042-reset";
334			reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
335			#reset-cells = <1>;
336		};
337
338		uart0: serial@7040000000 {
339			compatible = "snps,dw-apb-uart";
340			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
341			interrupt-parent = <&intc>;
342			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
343			clock-frequency = <500000000>;
344			reg-shift = <2>;
345			reg-io-width = <4>;
346			resets = <&rstgen RST_UART0>;
347			status = "disabled";
348		};
349	};
350};
351