1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/ { 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 timebase-frequency = <50000000>; 11 12 cpu-map { 13 socket0 { 14 cluster0 { 15 core0 { 16 cpu = <&cpu0>; 17 }; 18 core1 { 19 cpu = <&cpu1>; 20 }; 21 core2 { 22 cpu = <&cpu2>; 23 }; 24 core3 { 25 cpu = <&cpu3>; 26 }; 27 }; 28 29 cluster1 { 30 core0 { 31 cpu = <&cpu4>; 32 }; 33 core1 { 34 cpu = <&cpu5>; 35 }; 36 core2 { 37 cpu = <&cpu6>; 38 }; 39 core3 { 40 cpu = <&cpu7>; 41 }; 42 }; 43 44 cluster2 { 45 core0 { 46 cpu = <&cpu16>; 47 }; 48 core1 { 49 cpu = <&cpu17>; 50 }; 51 core2 { 52 cpu = <&cpu18>; 53 }; 54 core3 { 55 cpu = <&cpu19>; 56 }; 57 }; 58 59 cluster3 { 60 core0 { 61 cpu = <&cpu20>; 62 }; 63 core1 { 64 cpu = <&cpu21>; 65 }; 66 core2 { 67 cpu = <&cpu22>; 68 }; 69 core3 { 70 cpu = <&cpu23>; 71 }; 72 }; 73 74 cluster4 { 75 core0 { 76 cpu = <&cpu8>; 77 }; 78 core1 { 79 cpu = <&cpu9>; 80 }; 81 core2 { 82 cpu = <&cpu10>; 83 }; 84 core3 { 85 cpu = <&cpu11>; 86 }; 87 }; 88 89 cluster5 { 90 core0 { 91 cpu = <&cpu12>; 92 }; 93 core1 { 94 cpu = <&cpu13>; 95 }; 96 core2 { 97 cpu = <&cpu14>; 98 }; 99 core3 { 100 cpu = <&cpu15>; 101 }; 102 }; 103 104 cluster6 { 105 core0 { 106 cpu = <&cpu24>; 107 }; 108 core1 { 109 cpu = <&cpu25>; 110 }; 111 core2 { 112 cpu = <&cpu26>; 113 }; 114 core3 { 115 cpu = <&cpu27>; 116 }; 117 }; 118 119 cluster7 { 120 core0 { 121 cpu = <&cpu28>; 122 }; 123 core1 { 124 cpu = <&cpu29>; 125 }; 126 core2 { 127 cpu = <&cpu30>; 128 }; 129 core3 { 130 cpu = <&cpu31>; 131 }; 132 }; 133 134 cluster8 { 135 core0 { 136 cpu = <&cpu32>; 137 }; 138 core1 { 139 cpu = <&cpu33>; 140 }; 141 core2 { 142 cpu = <&cpu34>; 143 }; 144 core3 { 145 cpu = <&cpu35>; 146 }; 147 }; 148 149 cluster9 { 150 core0 { 151 cpu = <&cpu36>; 152 }; 153 core1 { 154 cpu = <&cpu37>; 155 }; 156 core2 { 157 cpu = <&cpu38>; 158 }; 159 core3 { 160 cpu = <&cpu39>; 161 }; 162 }; 163 164 cluster10 { 165 core0 { 166 cpu = <&cpu48>; 167 }; 168 core1 { 169 cpu = <&cpu49>; 170 }; 171 core2 { 172 cpu = <&cpu50>; 173 }; 174 core3 { 175 cpu = <&cpu51>; 176 }; 177 }; 178 179 cluster11 { 180 core0 { 181 cpu = <&cpu52>; 182 }; 183 core1 { 184 cpu = <&cpu53>; 185 }; 186 core2 { 187 cpu = <&cpu54>; 188 }; 189 core3 { 190 cpu = <&cpu55>; 191 }; 192 }; 193 194 cluster12 { 195 core0 { 196 cpu = <&cpu40>; 197 }; 198 core1 { 199 cpu = <&cpu41>; 200 }; 201 core2 { 202 cpu = <&cpu42>; 203 }; 204 core3 { 205 cpu = <&cpu43>; 206 }; 207 }; 208 209 cluster13 { 210 core0 { 211 cpu = <&cpu44>; 212 }; 213 core1 { 214 cpu = <&cpu45>; 215 }; 216 core2 { 217 cpu = <&cpu46>; 218 }; 219 core3 { 220 cpu = <&cpu47>; 221 }; 222 }; 223 224 cluster14 { 225 core0 { 226 cpu = <&cpu56>; 227 }; 228 core1 { 229 cpu = <&cpu57>; 230 }; 231 core2 { 232 cpu = <&cpu58>; 233 }; 234 core3 { 235 cpu = <&cpu59>; 236 }; 237 }; 238 239 cluster15 { 240 core0 { 241 cpu = <&cpu60>; 242 }; 243 core1 { 244 cpu = <&cpu61>; 245 }; 246 core2 { 247 cpu = <&cpu62>; 248 }; 249 core3 { 250 cpu = <&cpu63>; 251 }; 252 }; 253 }; 254 }; 255 256 cpu0: cpu@0 { 257 compatible = "thead,c920", "riscv"; 258 device_type = "cpu"; 259 riscv,isa = "rv64imafdc"; 260 riscv,isa-base = "rv64i"; 261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 262 "ziccrse", "zicntr", "zicsr", 263 "zifencei", "zihpm", "zfh", 264 "xtheadvector"; 265 thead,vlenb = <16>; 266 reg = <0>; 267 i-cache-block-size = <64>; 268 i-cache-size = <65536>; 269 i-cache-sets = <512>; 270 d-cache-block-size = <64>; 271 d-cache-size = <65536>; 272 d-cache-sets = <512>; 273 next-level-cache = <&l2_cache0>; 274 mmu-type = "riscv,sv39"; 275 276 cpu0_intc: interrupt-controller { 277 compatible = "riscv,cpu-intc"; 278 interrupt-controller; 279 #interrupt-cells = <1>; 280 }; 281 }; 282 283 cpu1: cpu@1 { 284 compatible = "thead,c920", "riscv"; 285 device_type = "cpu"; 286 riscv,isa = "rv64imafdc"; 287 riscv,isa-base = "rv64i"; 288 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 289 "ziccrse", "zicntr", "zicsr", 290 "zifencei", "zihpm", "zfh", 291 "xtheadvector"; 292 thead,vlenb = <16>; 293 reg = <1>; 294 i-cache-block-size = <64>; 295 i-cache-size = <65536>; 296 i-cache-sets = <512>; 297 d-cache-block-size = <64>; 298 d-cache-size = <65536>; 299 d-cache-sets = <512>; 300 next-level-cache = <&l2_cache0>; 301 mmu-type = "riscv,sv39"; 302 303 cpu1_intc: interrupt-controller { 304 compatible = "riscv,cpu-intc"; 305 interrupt-controller; 306 #interrupt-cells = <1>; 307 }; 308 }; 309 310 cpu2: cpu@2 { 311 compatible = "thead,c920", "riscv"; 312 device_type = "cpu"; 313 riscv,isa = "rv64imafdc"; 314 riscv,isa-base = "rv64i"; 315 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 316 "ziccrse", "zicntr", "zicsr", 317 "zifencei", "zihpm", "zfh", 318 "xtheadvector"; 319 thead,vlenb = <16>; 320 reg = <2>; 321 i-cache-block-size = <64>; 322 i-cache-size = <65536>; 323 i-cache-sets = <512>; 324 d-cache-block-size = <64>; 325 d-cache-size = <65536>; 326 d-cache-sets = <512>; 327 next-level-cache = <&l2_cache0>; 328 mmu-type = "riscv,sv39"; 329 330 cpu2_intc: interrupt-controller { 331 compatible = "riscv,cpu-intc"; 332 interrupt-controller; 333 #interrupt-cells = <1>; 334 }; 335 }; 336 337 cpu3: cpu@3 { 338 compatible = "thead,c920", "riscv"; 339 device_type = "cpu"; 340 riscv,isa = "rv64imafdc"; 341 riscv,isa-base = "rv64i"; 342 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 343 "ziccrse", "zicntr", "zicsr", 344 "zifencei", "zihpm", "zfh", 345 "xtheadvector"; 346 thead,vlenb = <16>; 347 reg = <3>; 348 i-cache-block-size = <64>; 349 i-cache-size = <65536>; 350 i-cache-sets = <512>; 351 d-cache-block-size = <64>; 352 d-cache-size = <65536>; 353 d-cache-sets = <512>; 354 next-level-cache = <&l2_cache0>; 355 mmu-type = "riscv,sv39"; 356 357 cpu3_intc: interrupt-controller { 358 compatible = "riscv,cpu-intc"; 359 interrupt-controller; 360 #interrupt-cells = <1>; 361 }; 362 }; 363 364 cpu4: cpu@4 { 365 compatible = "thead,c920", "riscv"; 366 device_type = "cpu"; 367 riscv,isa = "rv64imafdc"; 368 riscv,isa-base = "rv64i"; 369 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 370 "ziccrse", "zicntr", "zicsr", 371 "zifencei", "zihpm", "zfh", 372 "xtheadvector"; 373 thead,vlenb = <16>; 374 reg = <4>; 375 i-cache-block-size = <64>; 376 i-cache-size = <65536>; 377 i-cache-sets = <512>; 378 d-cache-block-size = <64>; 379 d-cache-size = <65536>; 380 d-cache-sets = <512>; 381 next-level-cache = <&l2_cache1>; 382 mmu-type = "riscv,sv39"; 383 384 cpu4_intc: interrupt-controller { 385 compatible = "riscv,cpu-intc"; 386 interrupt-controller; 387 #interrupt-cells = <1>; 388 }; 389 }; 390 391 cpu5: cpu@5 { 392 compatible = "thead,c920", "riscv"; 393 device_type = "cpu"; 394 riscv,isa = "rv64imafdc"; 395 riscv,isa-base = "rv64i"; 396 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 397 "ziccrse", "zicntr", "zicsr", 398 "zifencei", "zihpm", "zfh", 399 "xtheadvector"; 400 thead,vlenb = <16>; 401 reg = <5>; 402 i-cache-block-size = <64>; 403 i-cache-size = <65536>; 404 i-cache-sets = <512>; 405 d-cache-block-size = <64>; 406 d-cache-size = <65536>; 407 d-cache-sets = <512>; 408 next-level-cache = <&l2_cache1>; 409 mmu-type = "riscv,sv39"; 410 411 cpu5_intc: interrupt-controller { 412 compatible = "riscv,cpu-intc"; 413 interrupt-controller; 414 #interrupt-cells = <1>; 415 }; 416 }; 417 418 cpu6: cpu@6 { 419 compatible = "thead,c920", "riscv"; 420 device_type = "cpu"; 421 riscv,isa = "rv64imafdc"; 422 riscv,isa-base = "rv64i"; 423 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 424 "ziccrse", "zicntr", "zicsr", 425 "zifencei", "zihpm", "zfh", 426 "xtheadvector"; 427 thead,vlenb = <16>; 428 reg = <6>; 429 i-cache-block-size = <64>; 430 i-cache-size = <65536>; 431 i-cache-sets = <512>; 432 d-cache-block-size = <64>; 433 d-cache-size = <65536>; 434 d-cache-sets = <512>; 435 next-level-cache = <&l2_cache1>; 436 mmu-type = "riscv,sv39"; 437 438 cpu6_intc: interrupt-controller { 439 compatible = "riscv,cpu-intc"; 440 interrupt-controller; 441 #interrupt-cells = <1>; 442 }; 443 }; 444 445 cpu7: cpu@7 { 446 compatible = "thead,c920", "riscv"; 447 device_type = "cpu"; 448 riscv,isa = "rv64imafdc"; 449 riscv,isa-base = "rv64i"; 450 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 451 "ziccrse", "zicntr", "zicsr", 452 "zifencei", "zihpm", "zfh", 453 "xtheadvector"; 454 thead,vlenb = <16>; 455 reg = <7>; 456 i-cache-block-size = <64>; 457 i-cache-size = <65536>; 458 i-cache-sets = <512>; 459 d-cache-block-size = <64>; 460 d-cache-size = <65536>; 461 d-cache-sets = <512>; 462 next-level-cache = <&l2_cache1>; 463 mmu-type = "riscv,sv39"; 464 465 cpu7_intc: interrupt-controller { 466 compatible = "riscv,cpu-intc"; 467 interrupt-controller; 468 #interrupt-cells = <1>; 469 }; 470 }; 471 472 cpu8: cpu@8 { 473 compatible = "thead,c920", "riscv"; 474 device_type = "cpu"; 475 riscv,isa = "rv64imafdc"; 476 riscv,isa-base = "rv64i"; 477 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 478 "ziccrse", "zicntr", "zicsr", 479 "zifencei", "zihpm", "zfh", 480 "xtheadvector"; 481 thead,vlenb = <16>; 482 reg = <8>; 483 i-cache-block-size = <64>; 484 i-cache-size = <65536>; 485 i-cache-sets = <512>; 486 d-cache-block-size = <64>; 487 d-cache-size = <65536>; 488 d-cache-sets = <512>; 489 next-level-cache = <&l2_cache4>; 490 mmu-type = "riscv,sv39"; 491 492 cpu8_intc: interrupt-controller { 493 compatible = "riscv,cpu-intc"; 494 interrupt-controller; 495 #interrupt-cells = <1>; 496 }; 497 }; 498 499 cpu9: cpu@9 { 500 compatible = "thead,c920", "riscv"; 501 device_type = "cpu"; 502 riscv,isa = "rv64imafdc"; 503 riscv,isa-base = "rv64i"; 504 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 505 "ziccrse", "zicntr", "zicsr", 506 "zifencei", "zihpm", "zfh", 507 "xtheadvector"; 508 thead,vlenb = <16>; 509 reg = <9>; 510 i-cache-block-size = <64>; 511 i-cache-size = <65536>; 512 i-cache-sets = <512>; 513 d-cache-block-size = <64>; 514 d-cache-size = <65536>; 515 d-cache-sets = <512>; 516 next-level-cache = <&l2_cache4>; 517 mmu-type = "riscv,sv39"; 518 519 cpu9_intc: interrupt-controller { 520 compatible = "riscv,cpu-intc"; 521 interrupt-controller; 522 #interrupt-cells = <1>; 523 }; 524 }; 525 526 cpu10: cpu@10 { 527 compatible = "thead,c920", "riscv"; 528 device_type = "cpu"; 529 riscv,isa = "rv64imafdc"; 530 riscv,isa-base = "rv64i"; 531 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 532 "ziccrse", "zicntr", "zicsr", 533 "zifencei", "zihpm", "zfh", 534 "xtheadvector"; 535 thead,vlenb = <16>; 536 reg = <10>; 537 i-cache-block-size = <64>; 538 i-cache-size = <65536>; 539 i-cache-sets = <512>; 540 d-cache-block-size = <64>; 541 d-cache-size = <65536>; 542 d-cache-sets = <512>; 543 next-level-cache = <&l2_cache4>; 544 mmu-type = "riscv,sv39"; 545 546 cpu10_intc: interrupt-controller { 547 compatible = "riscv,cpu-intc"; 548 interrupt-controller; 549 #interrupt-cells = <1>; 550 }; 551 }; 552 553 cpu11: cpu@11 { 554 compatible = "thead,c920", "riscv"; 555 device_type = "cpu"; 556 riscv,isa = "rv64imafdc"; 557 riscv,isa-base = "rv64i"; 558 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 559 "ziccrse", "zicntr", "zicsr", 560 "zifencei", "zihpm", "zfh", 561 "xtheadvector"; 562 thead,vlenb = <16>; 563 reg = <11>; 564 i-cache-block-size = <64>; 565 i-cache-size = <65536>; 566 i-cache-sets = <512>; 567 d-cache-block-size = <64>; 568 d-cache-size = <65536>; 569 d-cache-sets = <512>; 570 next-level-cache = <&l2_cache4>; 571 mmu-type = "riscv,sv39"; 572 573 cpu11_intc: interrupt-controller { 574 compatible = "riscv,cpu-intc"; 575 interrupt-controller; 576 #interrupt-cells = <1>; 577 }; 578 }; 579 580 cpu12: cpu@12 { 581 compatible = "thead,c920", "riscv"; 582 device_type = "cpu"; 583 riscv,isa = "rv64imafdc"; 584 riscv,isa-base = "rv64i"; 585 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 586 "ziccrse", "zicntr", "zicsr", 587 "zifencei", "zihpm", "zfh", 588 "xtheadvector"; 589 thead,vlenb = <16>; 590 reg = <12>; 591 i-cache-block-size = <64>; 592 i-cache-size = <65536>; 593 i-cache-sets = <512>; 594 d-cache-block-size = <64>; 595 d-cache-size = <65536>; 596 d-cache-sets = <512>; 597 next-level-cache = <&l2_cache5>; 598 mmu-type = "riscv,sv39"; 599 600 cpu12_intc: interrupt-controller { 601 compatible = "riscv,cpu-intc"; 602 interrupt-controller; 603 #interrupt-cells = <1>; 604 }; 605 }; 606 607 cpu13: cpu@13 { 608 compatible = "thead,c920", "riscv"; 609 device_type = "cpu"; 610 riscv,isa = "rv64imafdc"; 611 riscv,isa-base = "rv64i"; 612 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 613 "ziccrse", "zicntr", "zicsr", 614 "zifencei", "zihpm", "zfh", 615 "xtheadvector"; 616 thead,vlenb = <16>; 617 reg = <13>; 618 i-cache-block-size = <64>; 619 i-cache-size = <65536>; 620 i-cache-sets = <512>; 621 d-cache-block-size = <64>; 622 d-cache-size = <65536>; 623 d-cache-sets = <512>; 624 next-level-cache = <&l2_cache5>; 625 mmu-type = "riscv,sv39"; 626 627 cpu13_intc: interrupt-controller { 628 compatible = "riscv,cpu-intc"; 629 interrupt-controller; 630 #interrupt-cells = <1>; 631 }; 632 }; 633 634 cpu14: cpu@14 { 635 compatible = "thead,c920", "riscv"; 636 device_type = "cpu"; 637 riscv,isa = "rv64imafdc"; 638 riscv,isa-base = "rv64i"; 639 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 640 "ziccrse", "zicntr", "zicsr", 641 "zifencei", "zihpm", "zfh", 642 "xtheadvector"; 643 thead,vlenb = <16>; 644 reg = <14>; 645 i-cache-block-size = <64>; 646 i-cache-size = <65536>; 647 i-cache-sets = <512>; 648 d-cache-block-size = <64>; 649 d-cache-size = <65536>; 650 d-cache-sets = <512>; 651 next-level-cache = <&l2_cache5>; 652 mmu-type = "riscv,sv39"; 653 654 cpu14_intc: interrupt-controller { 655 compatible = "riscv,cpu-intc"; 656 interrupt-controller; 657 #interrupt-cells = <1>; 658 }; 659 }; 660 661 cpu15: cpu@15 { 662 compatible = "thead,c920", "riscv"; 663 device_type = "cpu"; 664 riscv,isa = "rv64imafdc"; 665 riscv,isa-base = "rv64i"; 666 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 667 "ziccrse", "zicntr", "zicsr", 668 "zifencei", "zihpm", "zfh", 669 "xtheadvector"; 670 thead,vlenb = <16>; 671 reg = <15>; 672 i-cache-block-size = <64>; 673 i-cache-size = <65536>; 674 i-cache-sets = <512>; 675 d-cache-block-size = <64>; 676 d-cache-size = <65536>; 677 d-cache-sets = <512>; 678 next-level-cache = <&l2_cache5>; 679 mmu-type = "riscv,sv39"; 680 681 cpu15_intc: interrupt-controller { 682 compatible = "riscv,cpu-intc"; 683 interrupt-controller; 684 #interrupt-cells = <1>; 685 }; 686 }; 687 688 cpu16: cpu@16 { 689 compatible = "thead,c920", "riscv"; 690 device_type = "cpu"; 691 riscv,isa = "rv64imafdc"; 692 riscv,isa-base = "rv64i"; 693 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 694 "ziccrse", "zicntr", "zicsr", 695 "zifencei", "zihpm", "zfh", 696 "xtheadvector"; 697 thead,vlenb = <16>; 698 reg = <16>; 699 i-cache-block-size = <64>; 700 i-cache-size = <65536>; 701 i-cache-sets = <512>; 702 d-cache-block-size = <64>; 703 d-cache-size = <65536>; 704 d-cache-sets = <512>; 705 next-level-cache = <&l2_cache2>; 706 mmu-type = "riscv,sv39"; 707 708 cpu16_intc: interrupt-controller { 709 compatible = "riscv,cpu-intc"; 710 interrupt-controller; 711 #interrupt-cells = <1>; 712 }; 713 }; 714 715 cpu17: cpu@17 { 716 compatible = "thead,c920", "riscv"; 717 device_type = "cpu"; 718 riscv,isa = "rv64imafdc"; 719 riscv,isa-base = "rv64i"; 720 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 721 "ziccrse", "zicntr", "zicsr", 722 "zifencei", "zihpm", "zfh", 723 "xtheadvector"; 724 thead,vlenb = <16>; 725 reg = <17>; 726 i-cache-block-size = <64>; 727 i-cache-size = <65536>; 728 i-cache-sets = <512>; 729 d-cache-block-size = <64>; 730 d-cache-size = <65536>; 731 d-cache-sets = <512>; 732 next-level-cache = <&l2_cache2>; 733 mmu-type = "riscv,sv39"; 734 735 cpu17_intc: interrupt-controller { 736 compatible = "riscv,cpu-intc"; 737 interrupt-controller; 738 #interrupt-cells = <1>; 739 }; 740 }; 741 742 cpu18: cpu@18 { 743 compatible = "thead,c920", "riscv"; 744 device_type = "cpu"; 745 riscv,isa = "rv64imafdc"; 746 riscv,isa-base = "rv64i"; 747 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 748 "ziccrse", "zicntr", "zicsr", 749 "zifencei", "zihpm", "zfh", 750 "xtheadvector"; 751 thead,vlenb = <16>; 752 reg = <18>; 753 i-cache-block-size = <64>; 754 i-cache-size = <65536>; 755 i-cache-sets = <512>; 756 d-cache-block-size = <64>; 757 d-cache-size = <65536>; 758 d-cache-sets = <512>; 759 next-level-cache = <&l2_cache2>; 760 mmu-type = "riscv,sv39"; 761 762 cpu18_intc: interrupt-controller { 763 compatible = "riscv,cpu-intc"; 764 interrupt-controller; 765 #interrupt-cells = <1>; 766 }; 767 }; 768 769 cpu19: cpu@19 { 770 compatible = "thead,c920", "riscv"; 771 device_type = "cpu"; 772 riscv,isa = "rv64imafdc"; 773 riscv,isa-base = "rv64i"; 774 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 775 "ziccrse", "zicntr", "zicsr", 776 "zifencei", "zihpm", "zfh", 777 "xtheadvector"; 778 thead,vlenb = <16>; 779 reg = <19>; 780 i-cache-block-size = <64>; 781 i-cache-size = <65536>; 782 i-cache-sets = <512>; 783 d-cache-block-size = <64>; 784 d-cache-size = <65536>; 785 d-cache-sets = <512>; 786 next-level-cache = <&l2_cache2>; 787 mmu-type = "riscv,sv39"; 788 789 cpu19_intc: interrupt-controller { 790 compatible = "riscv,cpu-intc"; 791 interrupt-controller; 792 #interrupt-cells = <1>; 793 }; 794 }; 795 796 cpu20: cpu@20 { 797 compatible = "thead,c920", "riscv"; 798 device_type = "cpu"; 799 riscv,isa = "rv64imafdc"; 800 riscv,isa-base = "rv64i"; 801 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 802 "ziccrse", "zicntr", "zicsr", 803 "zifencei", "zihpm", "zfh", 804 "xtheadvector"; 805 thead,vlenb = <16>; 806 reg = <20>; 807 i-cache-block-size = <64>; 808 i-cache-size = <65536>; 809 i-cache-sets = <512>; 810 d-cache-block-size = <64>; 811 d-cache-size = <65536>; 812 d-cache-sets = <512>; 813 next-level-cache = <&l2_cache3>; 814 mmu-type = "riscv,sv39"; 815 816 cpu20_intc: interrupt-controller { 817 compatible = "riscv,cpu-intc"; 818 interrupt-controller; 819 #interrupt-cells = <1>; 820 }; 821 }; 822 823 cpu21: cpu@21 { 824 compatible = "thead,c920", "riscv"; 825 device_type = "cpu"; 826 riscv,isa = "rv64imafdc"; 827 riscv,isa-base = "rv64i"; 828 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 829 "ziccrse", "zicntr", "zicsr", 830 "zifencei", "zihpm", "zfh", 831 "xtheadvector"; 832 thead,vlenb = <16>; 833 reg = <21>; 834 i-cache-block-size = <64>; 835 i-cache-size = <65536>; 836 i-cache-sets = <512>; 837 d-cache-block-size = <64>; 838 d-cache-size = <65536>; 839 d-cache-sets = <512>; 840 next-level-cache = <&l2_cache3>; 841 mmu-type = "riscv,sv39"; 842 843 cpu21_intc: interrupt-controller { 844 compatible = "riscv,cpu-intc"; 845 interrupt-controller; 846 #interrupt-cells = <1>; 847 }; 848 }; 849 850 cpu22: cpu@22 { 851 compatible = "thead,c920", "riscv"; 852 device_type = "cpu"; 853 riscv,isa = "rv64imafdc"; 854 riscv,isa-base = "rv64i"; 855 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 856 "ziccrse", "zicntr", "zicsr", 857 "zifencei", "zihpm", "zfh", 858 "xtheadvector"; 859 thead,vlenb = <16>; 860 reg = <22>; 861 i-cache-block-size = <64>; 862 i-cache-size = <65536>; 863 i-cache-sets = <512>; 864 d-cache-block-size = <64>; 865 d-cache-size = <65536>; 866 d-cache-sets = <512>; 867 next-level-cache = <&l2_cache3>; 868 mmu-type = "riscv,sv39"; 869 870 cpu22_intc: interrupt-controller { 871 compatible = "riscv,cpu-intc"; 872 interrupt-controller; 873 #interrupt-cells = <1>; 874 }; 875 }; 876 877 cpu23: cpu@23 { 878 compatible = "thead,c920", "riscv"; 879 device_type = "cpu"; 880 riscv,isa = "rv64imafdc"; 881 riscv,isa-base = "rv64i"; 882 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 883 "ziccrse", "zicntr", "zicsr", 884 "zifencei", "zihpm", "zfh", 885 "xtheadvector"; 886 thead,vlenb = <16>; 887 reg = <23>; 888 i-cache-block-size = <64>; 889 i-cache-size = <65536>; 890 i-cache-sets = <512>; 891 d-cache-block-size = <64>; 892 d-cache-size = <65536>; 893 d-cache-sets = <512>; 894 next-level-cache = <&l2_cache3>; 895 mmu-type = "riscv,sv39"; 896 897 cpu23_intc: interrupt-controller { 898 compatible = "riscv,cpu-intc"; 899 interrupt-controller; 900 #interrupt-cells = <1>; 901 }; 902 }; 903 904 cpu24: cpu@24 { 905 compatible = "thead,c920", "riscv"; 906 device_type = "cpu"; 907 riscv,isa = "rv64imafdc"; 908 riscv,isa-base = "rv64i"; 909 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 910 "ziccrse", "zicntr", "zicsr", 911 "zifencei", "zihpm", "zfh", 912 "xtheadvector"; 913 thead,vlenb = <16>; 914 reg = <24>; 915 i-cache-block-size = <64>; 916 i-cache-size = <65536>; 917 i-cache-sets = <512>; 918 d-cache-block-size = <64>; 919 d-cache-size = <65536>; 920 d-cache-sets = <512>; 921 next-level-cache = <&l2_cache6>; 922 mmu-type = "riscv,sv39"; 923 924 cpu24_intc: interrupt-controller { 925 compatible = "riscv,cpu-intc"; 926 interrupt-controller; 927 #interrupt-cells = <1>; 928 }; 929 }; 930 931 cpu25: cpu@25 { 932 compatible = "thead,c920", "riscv"; 933 device_type = "cpu"; 934 riscv,isa = "rv64imafdc"; 935 riscv,isa-base = "rv64i"; 936 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 937 "ziccrse", "zicntr", "zicsr", 938 "zifencei", "zihpm", "zfh", 939 "xtheadvector"; 940 thead,vlenb = <16>; 941 reg = <25>; 942 i-cache-block-size = <64>; 943 i-cache-size = <65536>; 944 i-cache-sets = <512>; 945 d-cache-block-size = <64>; 946 d-cache-size = <65536>; 947 d-cache-sets = <512>; 948 next-level-cache = <&l2_cache6>; 949 mmu-type = "riscv,sv39"; 950 951 cpu25_intc: interrupt-controller { 952 compatible = "riscv,cpu-intc"; 953 interrupt-controller; 954 #interrupt-cells = <1>; 955 }; 956 }; 957 958 cpu26: cpu@26 { 959 compatible = "thead,c920", "riscv"; 960 device_type = "cpu"; 961 riscv,isa = "rv64imafdc"; 962 riscv,isa-base = "rv64i"; 963 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 964 "ziccrse", "zicntr", "zicsr", 965 "zifencei", "zihpm", "zfh", 966 "xtheadvector"; 967 thead,vlenb = <16>; 968 reg = <26>; 969 i-cache-block-size = <64>; 970 i-cache-size = <65536>; 971 i-cache-sets = <512>; 972 d-cache-block-size = <64>; 973 d-cache-size = <65536>; 974 d-cache-sets = <512>; 975 next-level-cache = <&l2_cache6>; 976 mmu-type = "riscv,sv39"; 977 978 cpu26_intc: interrupt-controller { 979 compatible = "riscv,cpu-intc"; 980 interrupt-controller; 981 #interrupt-cells = <1>; 982 }; 983 }; 984 985 cpu27: cpu@27 { 986 compatible = "thead,c920", "riscv"; 987 device_type = "cpu"; 988 riscv,isa = "rv64imafdc"; 989 riscv,isa-base = "rv64i"; 990 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 991 "ziccrse", "zicntr", "zicsr", 992 "zifencei", "zihpm", "zfh", 993 "xtheadvector"; 994 thead,vlenb = <16>; 995 reg = <27>; 996 i-cache-block-size = <64>; 997 i-cache-size = <65536>; 998 i-cache-sets = <512>; 999 d-cache-block-size = <64>; 1000 d-cache-size = <65536>; 1001 d-cache-sets = <512>; 1002 next-level-cache = <&l2_cache6>; 1003 mmu-type = "riscv,sv39"; 1004 1005 cpu27_intc: interrupt-controller { 1006 compatible = "riscv,cpu-intc"; 1007 interrupt-controller; 1008 #interrupt-cells = <1>; 1009 }; 1010 }; 1011 1012 cpu28: cpu@28 { 1013 compatible = "thead,c920", "riscv"; 1014 device_type = "cpu"; 1015 riscv,isa = "rv64imafdc"; 1016 riscv,isa-base = "rv64i"; 1017 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1018 "ziccrse", "zicntr", "zicsr", 1019 "zifencei", "zihpm", "zfh", 1020 "xtheadvector"; 1021 thead,vlenb = <16>; 1022 reg = <28>; 1023 i-cache-block-size = <64>; 1024 i-cache-size = <65536>; 1025 i-cache-sets = <512>; 1026 d-cache-block-size = <64>; 1027 d-cache-size = <65536>; 1028 d-cache-sets = <512>; 1029 next-level-cache = <&l2_cache7>; 1030 mmu-type = "riscv,sv39"; 1031 1032 cpu28_intc: interrupt-controller { 1033 compatible = "riscv,cpu-intc"; 1034 interrupt-controller; 1035 #interrupt-cells = <1>; 1036 }; 1037 }; 1038 1039 cpu29: cpu@29 { 1040 compatible = "thead,c920", "riscv"; 1041 device_type = "cpu"; 1042 riscv,isa = "rv64imafdc"; 1043 riscv,isa-base = "rv64i"; 1044 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1045 "ziccrse", "zicntr", "zicsr", 1046 "zifencei", "zihpm", "zfh", 1047 "xtheadvector"; 1048 thead,vlenb = <16>; 1049 reg = <29>; 1050 i-cache-block-size = <64>; 1051 i-cache-size = <65536>; 1052 i-cache-sets = <512>; 1053 d-cache-block-size = <64>; 1054 d-cache-size = <65536>; 1055 d-cache-sets = <512>; 1056 next-level-cache = <&l2_cache7>; 1057 mmu-type = "riscv,sv39"; 1058 1059 cpu29_intc: interrupt-controller { 1060 compatible = "riscv,cpu-intc"; 1061 interrupt-controller; 1062 #interrupt-cells = <1>; 1063 }; 1064 }; 1065 1066 cpu30: cpu@30 { 1067 compatible = "thead,c920", "riscv"; 1068 device_type = "cpu"; 1069 riscv,isa = "rv64imafdc"; 1070 riscv,isa-base = "rv64i"; 1071 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1072 "ziccrse", "zicntr", "zicsr", 1073 "zifencei", "zihpm", "zfh", 1074 "xtheadvector"; 1075 thead,vlenb = <16>; 1076 reg = <30>; 1077 i-cache-block-size = <64>; 1078 i-cache-size = <65536>; 1079 i-cache-sets = <512>; 1080 d-cache-block-size = <64>; 1081 d-cache-size = <65536>; 1082 d-cache-sets = <512>; 1083 next-level-cache = <&l2_cache7>; 1084 mmu-type = "riscv,sv39"; 1085 1086 cpu30_intc: interrupt-controller { 1087 compatible = "riscv,cpu-intc"; 1088 interrupt-controller; 1089 #interrupt-cells = <1>; 1090 }; 1091 }; 1092 1093 cpu31: cpu@31 { 1094 compatible = "thead,c920", "riscv"; 1095 device_type = "cpu"; 1096 riscv,isa = "rv64imafdc"; 1097 riscv,isa-base = "rv64i"; 1098 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1099 "ziccrse", "zicntr", "zicsr", 1100 "zifencei", "zihpm", "zfh", 1101 "xtheadvector"; 1102 thead,vlenb = <16>; 1103 reg = <31>; 1104 i-cache-block-size = <64>; 1105 i-cache-size = <65536>; 1106 i-cache-sets = <512>; 1107 d-cache-block-size = <64>; 1108 d-cache-size = <65536>; 1109 d-cache-sets = <512>; 1110 next-level-cache = <&l2_cache7>; 1111 mmu-type = "riscv,sv39"; 1112 1113 cpu31_intc: interrupt-controller { 1114 compatible = "riscv,cpu-intc"; 1115 interrupt-controller; 1116 #interrupt-cells = <1>; 1117 }; 1118 }; 1119 1120 cpu32: cpu@32 { 1121 compatible = "thead,c920", "riscv"; 1122 device_type = "cpu"; 1123 riscv,isa = "rv64imafdc"; 1124 riscv,isa-base = "rv64i"; 1125 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1126 "ziccrse", "zicntr", "zicsr", 1127 "zifencei", "zihpm", "zfh", 1128 "xtheadvector"; 1129 thead,vlenb = <16>; 1130 reg = <32>; 1131 i-cache-block-size = <64>; 1132 i-cache-size = <65536>; 1133 i-cache-sets = <512>; 1134 d-cache-block-size = <64>; 1135 d-cache-size = <65536>; 1136 d-cache-sets = <512>; 1137 next-level-cache = <&l2_cache8>; 1138 mmu-type = "riscv,sv39"; 1139 1140 cpu32_intc: interrupt-controller { 1141 compatible = "riscv,cpu-intc"; 1142 interrupt-controller; 1143 #interrupt-cells = <1>; 1144 }; 1145 }; 1146 1147 cpu33: cpu@33 { 1148 compatible = "thead,c920", "riscv"; 1149 device_type = "cpu"; 1150 riscv,isa = "rv64imafdc"; 1151 riscv,isa-base = "rv64i"; 1152 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1153 "ziccrse", "zicntr", "zicsr", 1154 "zifencei", "zihpm", "zfh", 1155 "xtheadvector"; 1156 thead,vlenb = <16>; 1157 reg = <33>; 1158 i-cache-block-size = <64>; 1159 i-cache-size = <65536>; 1160 i-cache-sets = <512>; 1161 d-cache-block-size = <64>; 1162 d-cache-size = <65536>; 1163 d-cache-sets = <512>; 1164 next-level-cache = <&l2_cache8>; 1165 mmu-type = "riscv,sv39"; 1166 1167 cpu33_intc: interrupt-controller { 1168 compatible = "riscv,cpu-intc"; 1169 interrupt-controller; 1170 #interrupt-cells = <1>; 1171 }; 1172 }; 1173 1174 cpu34: cpu@34 { 1175 compatible = "thead,c920", "riscv"; 1176 device_type = "cpu"; 1177 riscv,isa = "rv64imafdc"; 1178 riscv,isa-base = "rv64i"; 1179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1180 "ziccrse", "zicntr", "zicsr", 1181 "zifencei", "zihpm", "zfh", 1182 "xtheadvector"; 1183 thead,vlenb = <16>; 1184 reg = <34>; 1185 i-cache-block-size = <64>; 1186 i-cache-size = <65536>; 1187 i-cache-sets = <512>; 1188 d-cache-block-size = <64>; 1189 d-cache-size = <65536>; 1190 d-cache-sets = <512>; 1191 next-level-cache = <&l2_cache8>; 1192 mmu-type = "riscv,sv39"; 1193 1194 cpu34_intc: interrupt-controller { 1195 compatible = "riscv,cpu-intc"; 1196 interrupt-controller; 1197 #interrupt-cells = <1>; 1198 }; 1199 }; 1200 1201 cpu35: cpu@35 { 1202 compatible = "thead,c920", "riscv"; 1203 device_type = "cpu"; 1204 riscv,isa = "rv64imafdc"; 1205 riscv,isa-base = "rv64i"; 1206 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1207 "ziccrse", "zicntr", "zicsr", 1208 "zifencei", "zihpm", "zfh", 1209 "xtheadvector"; 1210 thead,vlenb = <16>; 1211 reg = <35>; 1212 i-cache-block-size = <64>; 1213 i-cache-size = <65536>; 1214 i-cache-sets = <512>; 1215 d-cache-block-size = <64>; 1216 d-cache-size = <65536>; 1217 d-cache-sets = <512>; 1218 next-level-cache = <&l2_cache8>; 1219 mmu-type = "riscv,sv39"; 1220 1221 cpu35_intc: interrupt-controller { 1222 compatible = "riscv,cpu-intc"; 1223 interrupt-controller; 1224 #interrupt-cells = <1>; 1225 }; 1226 }; 1227 1228 cpu36: cpu@36 { 1229 compatible = "thead,c920", "riscv"; 1230 device_type = "cpu"; 1231 riscv,isa = "rv64imafdc"; 1232 riscv,isa-base = "rv64i"; 1233 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1234 "ziccrse", "zicntr", "zicsr", 1235 "zifencei", "zihpm", "zfh", 1236 "xtheadvector"; 1237 thead,vlenb = <16>; 1238 reg = <36>; 1239 i-cache-block-size = <64>; 1240 i-cache-size = <65536>; 1241 i-cache-sets = <512>; 1242 d-cache-block-size = <64>; 1243 d-cache-size = <65536>; 1244 d-cache-sets = <512>; 1245 next-level-cache = <&l2_cache9>; 1246 mmu-type = "riscv,sv39"; 1247 1248 cpu36_intc: interrupt-controller { 1249 compatible = "riscv,cpu-intc"; 1250 interrupt-controller; 1251 #interrupt-cells = <1>; 1252 }; 1253 }; 1254 1255 cpu37: cpu@37 { 1256 compatible = "thead,c920", "riscv"; 1257 device_type = "cpu"; 1258 riscv,isa = "rv64imafdc"; 1259 riscv,isa-base = "rv64i"; 1260 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1261 "ziccrse", "zicntr", "zicsr", 1262 "zifencei", "zihpm", "zfh", 1263 "xtheadvector"; 1264 thead,vlenb = <16>; 1265 reg = <37>; 1266 i-cache-block-size = <64>; 1267 i-cache-size = <65536>; 1268 i-cache-sets = <512>; 1269 d-cache-block-size = <64>; 1270 d-cache-size = <65536>; 1271 d-cache-sets = <512>; 1272 next-level-cache = <&l2_cache9>; 1273 mmu-type = "riscv,sv39"; 1274 1275 cpu37_intc: interrupt-controller { 1276 compatible = "riscv,cpu-intc"; 1277 interrupt-controller; 1278 #interrupt-cells = <1>; 1279 }; 1280 }; 1281 1282 cpu38: cpu@38 { 1283 compatible = "thead,c920", "riscv"; 1284 device_type = "cpu"; 1285 riscv,isa = "rv64imafdc"; 1286 riscv,isa-base = "rv64i"; 1287 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1288 "ziccrse", "zicntr", "zicsr", 1289 "zifencei", "zihpm", "zfh", 1290 "xtheadvector"; 1291 thead,vlenb = <16>; 1292 reg = <38>; 1293 i-cache-block-size = <64>; 1294 i-cache-size = <65536>; 1295 i-cache-sets = <512>; 1296 d-cache-block-size = <64>; 1297 d-cache-size = <65536>; 1298 d-cache-sets = <512>; 1299 next-level-cache = <&l2_cache9>; 1300 mmu-type = "riscv,sv39"; 1301 1302 cpu38_intc: interrupt-controller { 1303 compatible = "riscv,cpu-intc"; 1304 interrupt-controller; 1305 #interrupt-cells = <1>; 1306 }; 1307 }; 1308 1309 cpu39: cpu@39 { 1310 compatible = "thead,c920", "riscv"; 1311 device_type = "cpu"; 1312 riscv,isa = "rv64imafdc"; 1313 riscv,isa-base = "rv64i"; 1314 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1315 "ziccrse", "zicntr", "zicsr", 1316 "zifencei", "zihpm", "zfh", 1317 "xtheadvector"; 1318 thead,vlenb = <16>; 1319 reg = <39>; 1320 i-cache-block-size = <64>; 1321 i-cache-size = <65536>; 1322 i-cache-sets = <512>; 1323 d-cache-block-size = <64>; 1324 d-cache-size = <65536>; 1325 d-cache-sets = <512>; 1326 next-level-cache = <&l2_cache9>; 1327 mmu-type = "riscv,sv39"; 1328 1329 cpu39_intc: interrupt-controller { 1330 compatible = "riscv,cpu-intc"; 1331 interrupt-controller; 1332 #interrupt-cells = <1>; 1333 }; 1334 }; 1335 1336 cpu40: cpu@40 { 1337 compatible = "thead,c920", "riscv"; 1338 device_type = "cpu"; 1339 riscv,isa = "rv64imafdc"; 1340 riscv,isa-base = "rv64i"; 1341 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1342 "ziccrse", "zicntr", "zicsr", 1343 "zifencei", "zihpm", "zfh", 1344 "xtheadvector"; 1345 thead,vlenb = <16>; 1346 reg = <40>; 1347 i-cache-block-size = <64>; 1348 i-cache-size = <65536>; 1349 i-cache-sets = <512>; 1350 d-cache-block-size = <64>; 1351 d-cache-size = <65536>; 1352 d-cache-sets = <512>; 1353 next-level-cache = <&l2_cache12>; 1354 mmu-type = "riscv,sv39"; 1355 1356 cpu40_intc: interrupt-controller { 1357 compatible = "riscv,cpu-intc"; 1358 interrupt-controller; 1359 #interrupt-cells = <1>; 1360 }; 1361 }; 1362 1363 cpu41: cpu@41 { 1364 compatible = "thead,c920", "riscv"; 1365 device_type = "cpu"; 1366 riscv,isa = "rv64imafdc"; 1367 riscv,isa-base = "rv64i"; 1368 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1369 "ziccrse", "zicntr", "zicsr", 1370 "zifencei", "zihpm", "zfh", 1371 "xtheadvector"; 1372 thead,vlenb = <16>; 1373 reg = <41>; 1374 i-cache-block-size = <64>; 1375 i-cache-size = <65536>; 1376 i-cache-sets = <512>; 1377 d-cache-block-size = <64>; 1378 d-cache-size = <65536>; 1379 d-cache-sets = <512>; 1380 next-level-cache = <&l2_cache12>; 1381 mmu-type = "riscv,sv39"; 1382 1383 cpu41_intc: interrupt-controller { 1384 compatible = "riscv,cpu-intc"; 1385 interrupt-controller; 1386 #interrupt-cells = <1>; 1387 }; 1388 }; 1389 1390 cpu42: cpu@42 { 1391 compatible = "thead,c920", "riscv"; 1392 device_type = "cpu"; 1393 riscv,isa = "rv64imafdc"; 1394 riscv,isa-base = "rv64i"; 1395 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1396 "ziccrse", "zicntr", "zicsr", 1397 "zifencei", "zihpm", "zfh", 1398 "xtheadvector"; 1399 thead,vlenb = <16>; 1400 reg = <42>; 1401 i-cache-block-size = <64>; 1402 i-cache-size = <65536>; 1403 i-cache-sets = <512>; 1404 d-cache-block-size = <64>; 1405 d-cache-size = <65536>; 1406 d-cache-sets = <512>; 1407 next-level-cache = <&l2_cache12>; 1408 mmu-type = "riscv,sv39"; 1409 1410 cpu42_intc: interrupt-controller { 1411 compatible = "riscv,cpu-intc"; 1412 interrupt-controller; 1413 #interrupt-cells = <1>; 1414 }; 1415 }; 1416 1417 cpu43: cpu@43 { 1418 compatible = "thead,c920", "riscv"; 1419 device_type = "cpu"; 1420 riscv,isa = "rv64imafdc"; 1421 riscv,isa-base = "rv64i"; 1422 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1423 "ziccrse", "zicntr", "zicsr", 1424 "zifencei", "zihpm", "zfh", 1425 "xtheadvector"; 1426 thead,vlenb = <16>; 1427 reg = <43>; 1428 i-cache-block-size = <64>; 1429 i-cache-size = <65536>; 1430 i-cache-sets = <512>; 1431 d-cache-block-size = <64>; 1432 d-cache-size = <65536>; 1433 d-cache-sets = <512>; 1434 next-level-cache = <&l2_cache12>; 1435 mmu-type = "riscv,sv39"; 1436 1437 cpu43_intc: interrupt-controller { 1438 compatible = "riscv,cpu-intc"; 1439 interrupt-controller; 1440 #interrupt-cells = <1>; 1441 }; 1442 }; 1443 1444 cpu44: cpu@44 { 1445 compatible = "thead,c920", "riscv"; 1446 device_type = "cpu"; 1447 riscv,isa = "rv64imafdc"; 1448 riscv,isa-base = "rv64i"; 1449 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1450 "ziccrse", "zicntr", "zicsr", 1451 "zifencei", "zihpm", "zfh", 1452 "xtheadvector"; 1453 thead,vlenb = <16>; 1454 reg = <44>; 1455 i-cache-block-size = <64>; 1456 i-cache-size = <65536>; 1457 i-cache-sets = <512>; 1458 d-cache-block-size = <64>; 1459 d-cache-size = <65536>; 1460 d-cache-sets = <512>; 1461 next-level-cache = <&l2_cache13>; 1462 mmu-type = "riscv,sv39"; 1463 1464 cpu44_intc: interrupt-controller { 1465 compatible = "riscv,cpu-intc"; 1466 interrupt-controller; 1467 #interrupt-cells = <1>; 1468 }; 1469 }; 1470 1471 cpu45: cpu@45 { 1472 compatible = "thead,c920", "riscv"; 1473 device_type = "cpu"; 1474 riscv,isa = "rv64imafdc"; 1475 riscv,isa-base = "rv64i"; 1476 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1477 "ziccrse", "zicntr", "zicsr", 1478 "zifencei", "zihpm", "zfh", 1479 "xtheadvector"; 1480 thead,vlenb = <16>; 1481 reg = <45>; 1482 i-cache-block-size = <64>; 1483 i-cache-size = <65536>; 1484 i-cache-sets = <512>; 1485 d-cache-block-size = <64>; 1486 d-cache-size = <65536>; 1487 d-cache-sets = <512>; 1488 next-level-cache = <&l2_cache13>; 1489 mmu-type = "riscv,sv39"; 1490 1491 cpu45_intc: interrupt-controller { 1492 compatible = "riscv,cpu-intc"; 1493 interrupt-controller; 1494 #interrupt-cells = <1>; 1495 }; 1496 }; 1497 1498 cpu46: cpu@46 { 1499 compatible = "thead,c920", "riscv"; 1500 device_type = "cpu"; 1501 riscv,isa = "rv64imafdc"; 1502 riscv,isa-base = "rv64i"; 1503 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1504 "ziccrse", "zicntr", "zicsr", 1505 "zifencei", "zihpm", "zfh", 1506 "xtheadvector"; 1507 thead,vlenb = <16>; 1508 reg = <46>; 1509 i-cache-block-size = <64>; 1510 i-cache-size = <65536>; 1511 i-cache-sets = <512>; 1512 d-cache-block-size = <64>; 1513 d-cache-size = <65536>; 1514 d-cache-sets = <512>; 1515 next-level-cache = <&l2_cache13>; 1516 mmu-type = "riscv,sv39"; 1517 1518 cpu46_intc: interrupt-controller { 1519 compatible = "riscv,cpu-intc"; 1520 interrupt-controller; 1521 #interrupt-cells = <1>; 1522 }; 1523 }; 1524 1525 cpu47: cpu@47 { 1526 compatible = "thead,c920", "riscv"; 1527 device_type = "cpu"; 1528 riscv,isa = "rv64imafdc"; 1529 riscv,isa-base = "rv64i"; 1530 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1531 "ziccrse", "zicntr", "zicsr", 1532 "zifencei", "zihpm", "zfh", 1533 "xtheadvector"; 1534 thead,vlenb = <16>; 1535 reg = <47>; 1536 i-cache-block-size = <64>; 1537 i-cache-size = <65536>; 1538 i-cache-sets = <512>; 1539 d-cache-block-size = <64>; 1540 d-cache-size = <65536>; 1541 d-cache-sets = <512>; 1542 next-level-cache = <&l2_cache13>; 1543 mmu-type = "riscv,sv39"; 1544 1545 cpu47_intc: interrupt-controller { 1546 compatible = "riscv,cpu-intc"; 1547 interrupt-controller; 1548 #interrupt-cells = <1>; 1549 }; 1550 }; 1551 1552 cpu48: cpu@48 { 1553 compatible = "thead,c920", "riscv"; 1554 device_type = "cpu"; 1555 riscv,isa = "rv64imafdc"; 1556 riscv,isa-base = "rv64i"; 1557 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1558 "ziccrse", "zicntr", "zicsr", 1559 "zifencei", "zihpm", "zfh", 1560 "xtheadvector"; 1561 thead,vlenb = <16>; 1562 reg = <48>; 1563 i-cache-block-size = <64>; 1564 i-cache-size = <65536>; 1565 i-cache-sets = <512>; 1566 d-cache-block-size = <64>; 1567 d-cache-size = <65536>; 1568 d-cache-sets = <512>; 1569 next-level-cache = <&l2_cache10>; 1570 mmu-type = "riscv,sv39"; 1571 1572 cpu48_intc: interrupt-controller { 1573 compatible = "riscv,cpu-intc"; 1574 interrupt-controller; 1575 #interrupt-cells = <1>; 1576 }; 1577 }; 1578 1579 cpu49: cpu@49 { 1580 compatible = "thead,c920", "riscv"; 1581 device_type = "cpu"; 1582 riscv,isa = "rv64imafdc"; 1583 riscv,isa-base = "rv64i"; 1584 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1585 "ziccrse", "zicntr", "zicsr", 1586 "zifencei", "zihpm", "zfh", 1587 "xtheadvector"; 1588 thead,vlenb = <16>; 1589 reg = <49>; 1590 i-cache-block-size = <64>; 1591 i-cache-size = <65536>; 1592 i-cache-sets = <512>; 1593 d-cache-block-size = <64>; 1594 d-cache-size = <65536>; 1595 d-cache-sets = <512>; 1596 next-level-cache = <&l2_cache10>; 1597 mmu-type = "riscv,sv39"; 1598 1599 cpu49_intc: interrupt-controller { 1600 compatible = "riscv,cpu-intc"; 1601 interrupt-controller; 1602 #interrupt-cells = <1>; 1603 }; 1604 }; 1605 1606 cpu50: cpu@50 { 1607 compatible = "thead,c920", "riscv"; 1608 device_type = "cpu"; 1609 riscv,isa = "rv64imafdc"; 1610 riscv,isa-base = "rv64i"; 1611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1612 "ziccrse", "zicntr", "zicsr", 1613 "zifencei", "zihpm", "zfh", 1614 "xtheadvector"; 1615 thead,vlenb = <16>; 1616 reg = <50>; 1617 i-cache-block-size = <64>; 1618 i-cache-size = <65536>; 1619 i-cache-sets = <512>; 1620 d-cache-block-size = <64>; 1621 d-cache-size = <65536>; 1622 d-cache-sets = <512>; 1623 next-level-cache = <&l2_cache10>; 1624 mmu-type = "riscv,sv39"; 1625 1626 cpu50_intc: interrupt-controller { 1627 compatible = "riscv,cpu-intc"; 1628 interrupt-controller; 1629 #interrupt-cells = <1>; 1630 }; 1631 }; 1632 1633 cpu51: cpu@51 { 1634 compatible = "thead,c920", "riscv"; 1635 device_type = "cpu"; 1636 riscv,isa = "rv64imafdc"; 1637 riscv,isa-base = "rv64i"; 1638 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1639 "ziccrse", "zicntr", "zicsr", 1640 "zifencei", "zihpm", "zfh", 1641 "xtheadvector"; 1642 thead,vlenb = <16>; 1643 reg = <51>; 1644 i-cache-block-size = <64>; 1645 i-cache-size = <65536>; 1646 i-cache-sets = <512>; 1647 d-cache-block-size = <64>; 1648 d-cache-size = <65536>; 1649 d-cache-sets = <512>; 1650 next-level-cache = <&l2_cache10>; 1651 mmu-type = "riscv,sv39"; 1652 1653 cpu51_intc: interrupt-controller { 1654 compatible = "riscv,cpu-intc"; 1655 interrupt-controller; 1656 #interrupt-cells = <1>; 1657 }; 1658 }; 1659 1660 cpu52: cpu@52 { 1661 compatible = "thead,c920", "riscv"; 1662 device_type = "cpu"; 1663 riscv,isa = "rv64imafdc"; 1664 riscv,isa-base = "rv64i"; 1665 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1666 "ziccrse", "zicntr", "zicsr", 1667 "zifencei", "zihpm", "zfh", 1668 "xtheadvector"; 1669 thead,vlenb = <16>; 1670 reg = <52>; 1671 i-cache-block-size = <64>; 1672 i-cache-size = <65536>; 1673 i-cache-sets = <512>; 1674 d-cache-block-size = <64>; 1675 d-cache-size = <65536>; 1676 d-cache-sets = <512>; 1677 next-level-cache = <&l2_cache11>; 1678 mmu-type = "riscv,sv39"; 1679 1680 cpu52_intc: interrupt-controller { 1681 compatible = "riscv,cpu-intc"; 1682 interrupt-controller; 1683 #interrupt-cells = <1>; 1684 }; 1685 }; 1686 1687 cpu53: cpu@53 { 1688 compatible = "thead,c920", "riscv"; 1689 device_type = "cpu"; 1690 riscv,isa = "rv64imafdc"; 1691 riscv,isa-base = "rv64i"; 1692 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1693 "ziccrse", "zicntr", "zicsr", 1694 "zifencei", "zihpm", "zfh", 1695 "xtheadvector"; 1696 thead,vlenb = <16>; 1697 reg = <53>; 1698 i-cache-block-size = <64>; 1699 i-cache-size = <65536>; 1700 i-cache-sets = <512>; 1701 d-cache-block-size = <64>; 1702 d-cache-size = <65536>; 1703 d-cache-sets = <512>; 1704 next-level-cache = <&l2_cache11>; 1705 mmu-type = "riscv,sv39"; 1706 1707 cpu53_intc: interrupt-controller { 1708 compatible = "riscv,cpu-intc"; 1709 interrupt-controller; 1710 #interrupt-cells = <1>; 1711 }; 1712 }; 1713 1714 cpu54: cpu@54 { 1715 compatible = "thead,c920", "riscv"; 1716 device_type = "cpu"; 1717 riscv,isa = "rv64imafdc"; 1718 riscv,isa-base = "rv64i"; 1719 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1720 "ziccrse", "zicntr", "zicsr", 1721 "zifencei", "zihpm", "zfh", 1722 "xtheadvector"; 1723 thead,vlenb = <16>; 1724 reg = <54>; 1725 i-cache-block-size = <64>; 1726 i-cache-size = <65536>; 1727 i-cache-sets = <512>; 1728 d-cache-block-size = <64>; 1729 d-cache-size = <65536>; 1730 d-cache-sets = <512>; 1731 next-level-cache = <&l2_cache11>; 1732 mmu-type = "riscv,sv39"; 1733 1734 cpu54_intc: interrupt-controller { 1735 compatible = "riscv,cpu-intc"; 1736 interrupt-controller; 1737 #interrupt-cells = <1>; 1738 }; 1739 }; 1740 1741 cpu55: cpu@55 { 1742 compatible = "thead,c920", "riscv"; 1743 device_type = "cpu"; 1744 riscv,isa = "rv64imafdc"; 1745 riscv,isa-base = "rv64i"; 1746 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1747 "ziccrse", "zicntr", "zicsr", 1748 "zifencei", "zihpm", "zfh", 1749 "xtheadvector"; 1750 thead,vlenb = <16>; 1751 reg = <55>; 1752 i-cache-block-size = <64>; 1753 i-cache-size = <65536>; 1754 i-cache-sets = <512>; 1755 d-cache-block-size = <64>; 1756 d-cache-size = <65536>; 1757 d-cache-sets = <512>; 1758 next-level-cache = <&l2_cache11>; 1759 mmu-type = "riscv,sv39"; 1760 1761 cpu55_intc: interrupt-controller { 1762 compatible = "riscv,cpu-intc"; 1763 interrupt-controller; 1764 #interrupt-cells = <1>; 1765 }; 1766 }; 1767 1768 cpu56: cpu@56 { 1769 compatible = "thead,c920", "riscv"; 1770 device_type = "cpu"; 1771 riscv,isa = "rv64imafdc"; 1772 riscv,isa-base = "rv64i"; 1773 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1774 "ziccrse", "zicntr", "zicsr", 1775 "zifencei", "zihpm", "zfh", 1776 "xtheadvector"; 1777 thead,vlenb = <16>; 1778 reg = <56>; 1779 i-cache-block-size = <64>; 1780 i-cache-size = <65536>; 1781 i-cache-sets = <512>; 1782 d-cache-block-size = <64>; 1783 d-cache-size = <65536>; 1784 d-cache-sets = <512>; 1785 next-level-cache = <&l2_cache14>; 1786 mmu-type = "riscv,sv39"; 1787 1788 cpu56_intc: interrupt-controller { 1789 compatible = "riscv,cpu-intc"; 1790 interrupt-controller; 1791 #interrupt-cells = <1>; 1792 }; 1793 }; 1794 1795 cpu57: cpu@57 { 1796 compatible = "thead,c920", "riscv"; 1797 device_type = "cpu"; 1798 riscv,isa = "rv64imafdc"; 1799 riscv,isa-base = "rv64i"; 1800 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1801 "ziccrse", "zicntr", "zicsr", 1802 "zifencei", "zihpm", "zfh", 1803 "xtheadvector"; 1804 thead,vlenb = <16>; 1805 reg = <57>; 1806 i-cache-block-size = <64>; 1807 i-cache-size = <65536>; 1808 i-cache-sets = <512>; 1809 d-cache-block-size = <64>; 1810 d-cache-size = <65536>; 1811 d-cache-sets = <512>; 1812 next-level-cache = <&l2_cache14>; 1813 mmu-type = "riscv,sv39"; 1814 1815 cpu57_intc: interrupt-controller { 1816 compatible = "riscv,cpu-intc"; 1817 interrupt-controller; 1818 #interrupt-cells = <1>; 1819 }; 1820 }; 1821 1822 cpu58: cpu@58 { 1823 compatible = "thead,c920", "riscv"; 1824 device_type = "cpu"; 1825 riscv,isa = "rv64imafdc"; 1826 riscv,isa-base = "rv64i"; 1827 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1828 "ziccrse", "zicntr", "zicsr", 1829 "zifencei", "zihpm", "zfh", 1830 "xtheadvector"; 1831 thead,vlenb = <16>; 1832 reg = <58>; 1833 i-cache-block-size = <64>; 1834 i-cache-size = <65536>; 1835 i-cache-sets = <512>; 1836 d-cache-block-size = <64>; 1837 d-cache-size = <65536>; 1838 d-cache-sets = <512>; 1839 next-level-cache = <&l2_cache14>; 1840 mmu-type = "riscv,sv39"; 1841 1842 cpu58_intc: interrupt-controller { 1843 compatible = "riscv,cpu-intc"; 1844 interrupt-controller; 1845 #interrupt-cells = <1>; 1846 }; 1847 }; 1848 1849 cpu59: cpu@59 { 1850 compatible = "thead,c920", "riscv"; 1851 device_type = "cpu"; 1852 riscv,isa = "rv64imafdc"; 1853 riscv,isa-base = "rv64i"; 1854 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1855 "ziccrse", "zicntr", "zicsr", 1856 "zifencei", "zihpm", "zfh", 1857 "xtheadvector"; 1858 thead,vlenb = <16>; 1859 reg = <59>; 1860 i-cache-block-size = <64>; 1861 i-cache-size = <65536>; 1862 i-cache-sets = <512>; 1863 d-cache-block-size = <64>; 1864 d-cache-size = <65536>; 1865 d-cache-sets = <512>; 1866 next-level-cache = <&l2_cache14>; 1867 mmu-type = "riscv,sv39"; 1868 1869 cpu59_intc: interrupt-controller { 1870 compatible = "riscv,cpu-intc"; 1871 interrupt-controller; 1872 #interrupt-cells = <1>; 1873 }; 1874 }; 1875 1876 cpu60: cpu@60 { 1877 compatible = "thead,c920", "riscv"; 1878 device_type = "cpu"; 1879 riscv,isa = "rv64imafdc"; 1880 riscv,isa-base = "rv64i"; 1881 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1882 "ziccrse", "zicntr", "zicsr", 1883 "zifencei", "zihpm", "zfh", 1884 "xtheadvector"; 1885 thead,vlenb = <16>; 1886 reg = <60>; 1887 i-cache-block-size = <64>; 1888 i-cache-size = <65536>; 1889 i-cache-sets = <512>; 1890 d-cache-block-size = <64>; 1891 d-cache-size = <65536>; 1892 d-cache-sets = <512>; 1893 next-level-cache = <&l2_cache15>; 1894 mmu-type = "riscv,sv39"; 1895 1896 cpu60_intc: interrupt-controller { 1897 compatible = "riscv,cpu-intc"; 1898 interrupt-controller; 1899 #interrupt-cells = <1>; 1900 }; 1901 }; 1902 1903 cpu61: cpu@61 { 1904 compatible = "thead,c920", "riscv"; 1905 device_type = "cpu"; 1906 riscv,isa = "rv64imafdc"; 1907 riscv,isa-base = "rv64i"; 1908 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1909 "ziccrse", "zicntr", "zicsr", 1910 "zifencei", "zihpm", "zfh", 1911 "xtheadvector"; 1912 thead,vlenb = <16>; 1913 reg = <61>; 1914 i-cache-block-size = <64>; 1915 i-cache-size = <65536>; 1916 i-cache-sets = <512>; 1917 d-cache-block-size = <64>; 1918 d-cache-size = <65536>; 1919 d-cache-sets = <512>; 1920 next-level-cache = <&l2_cache15>; 1921 mmu-type = "riscv,sv39"; 1922 1923 cpu61_intc: interrupt-controller { 1924 compatible = "riscv,cpu-intc"; 1925 interrupt-controller; 1926 #interrupt-cells = <1>; 1927 }; 1928 }; 1929 1930 cpu62: cpu@62 { 1931 compatible = "thead,c920", "riscv"; 1932 device_type = "cpu"; 1933 riscv,isa = "rv64imafdc"; 1934 riscv,isa-base = "rv64i"; 1935 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1936 "ziccrse", "zicntr", "zicsr", 1937 "zifencei", "zihpm", "zfh", 1938 "xtheadvector"; 1939 thead,vlenb = <16>; 1940 reg = <62>; 1941 i-cache-block-size = <64>; 1942 i-cache-size = <65536>; 1943 i-cache-sets = <512>; 1944 d-cache-block-size = <64>; 1945 d-cache-size = <65536>; 1946 d-cache-sets = <512>; 1947 next-level-cache = <&l2_cache15>; 1948 mmu-type = "riscv,sv39"; 1949 1950 cpu62_intc: interrupt-controller { 1951 compatible = "riscv,cpu-intc"; 1952 interrupt-controller; 1953 #interrupt-cells = <1>; 1954 }; 1955 }; 1956 1957 cpu63: cpu@63 { 1958 compatible = "thead,c920", "riscv"; 1959 device_type = "cpu"; 1960 riscv,isa = "rv64imafdc"; 1961 riscv,isa-base = "rv64i"; 1962 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1963 "ziccrse", "zicntr", "zicsr", 1964 "zifencei", "zihpm", "zfh", 1965 "xtheadvector"; 1966 thead,vlenb = <16>; 1967 reg = <63>; 1968 i-cache-block-size = <64>; 1969 i-cache-size = <65536>; 1970 i-cache-sets = <512>; 1971 d-cache-block-size = <64>; 1972 d-cache-size = <65536>; 1973 d-cache-sets = <512>; 1974 next-level-cache = <&l2_cache15>; 1975 mmu-type = "riscv,sv39"; 1976 1977 cpu63_intc: interrupt-controller { 1978 compatible = "riscv,cpu-intc"; 1979 interrupt-controller; 1980 #interrupt-cells = <1>; 1981 }; 1982 }; 1983 1984 l2_cache0: cache-controller-0 { 1985 compatible = "cache"; 1986 cache-block-size = <64>; 1987 cache-level = <2>; 1988 cache-size = <1048576>; 1989 cache-sets = <1024>; 1990 cache-unified; 1991 }; 1992 1993 l2_cache1: cache-controller-1 { 1994 compatible = "cache"; 1995 cache-block-size = <64>; 1996 cache-level = <2>; 1997 cache-size = <1048576>; 1998 cache-sets = <1024>; 1999 cache-unified; 2000 }; 2001 2002 l2_cache2: cache-controller-2 { 2003 compatible = "cache"; 2004 cache-block-size = <64>; 2005 cache-level = <2>; 2006 cache-size = <1048576>; 2007 cache-sets = <1024>; 2008 cache-unified; 2009 }; 2010 2011 l2_cache3: cache-controller-3 { 2012 compatible = "cache"; 2013 cache-block-size = <64>; 2014 cache-level = <2>; 2015 cache-size = <1048576>; 2016 cache-sets = <1024>; 2017 cache-unified; 2018 }; 2019 2020 l2_cache4: cache-controller-4 { 2021 compatible = "cache"; 2022 cache-block-size = <64>; 2023 cache-level = <2>; 2024 cache-size = <1048576>; 2025 cache-sets = <1024>; 2026 cache-unified; 2027 }; 2028 2029 l2_cache5: cache-controller-5 { 2030 compatible = "cache"; 2031 cache-block-size = <64>; 2032 cache-level = <2>; 2033 cache-size = <1048576>; 2034 cache-sets = <1024>; 2035 cache-unified; 2036 }; 2037 2038 l2_cache6: cache-controller-6 { 2039 compatible = "cache"; 2040 cache-block-size = <64>; 2041 cache-level = <2>; 2042 cache-size = <1048576>; 2043 cache-sets = <1024>; 2044 cache-unified; 2045 }; 2046 2047 l2_cache7: cache-controller-7 { 2048 compatible = "cache"; 2049 cache-block-size = <64>; 2050 cache-level = <2>; 2051 cache-size = <1048576>; 2052 cache-sets = <1024>; 2053 cache-unified; 2054 }; 2055 2056 l2_cache8: cache-controller-8 { 2057 compatible = "cache"; 2058 cache-block-size = <64>; 2059 cache-level = <2>; 2060 cache-size = <1048576>; 2061 cache-sets = <1024>; 2062 cache-unified; 2063 }; 2064 2065 l2_cache9: cache-controller-9 { 2066 compatible = "cache"; 2067 cache-block-size = <64>; 2068 cache-level = <2>; 2069 cache-size = <1048576>; 2070 cache-sets = <1024>; 2071 cache-unified; 2072 }; 2073 2074 l2_cache10: cache-controller-10 { 2075 compatible = "cache"; 2076 cache-block-size = <64>; 2077 cache-level = <2>; 2078 cache-size = <1048576>; 2079 cache-sets = <1024>; 2080 cache-unified; 2081 }; 2082 2083 l2_cache11: cache-controller-11 { 2084 compatible = "cache"; 2085 cache-block-size = <64>; 2086 cache-level = <2>; 2087 cache-size = <1048576>; 2088 cache-sets = <1024>; 2089 cache-unified; 2090 }; 2091 2092 l2_cache12: cache-controller-12 { 2093 compatible = "cache"; 2094 cache-block-size = <64>; 2095 cache-level = <2>; 2096 cache-size = <1048576>; 2097 cache-sets = <1024>; 2098 cache-unified; 2099 }; 2100 2101 l2_cache13: cache-controller-13 { 2102 compatible = "cache"; 2103 cache-block-size = <64>; 2104 cache-level = <2>; 2105 cache-size = <1048576>; 2106 cache-sets = <1024>; 2107 cache-unified; 2108 }; 2109 2110 l2_cache14: cache-controller-14 { 2111 compatible = "cache"; 2112 cache-block-size = <64>; 2113 cache-level = <2>; 2114 cache-size = <1048576>; 2115 cache-sets = <1024>; 2116 cache-unified; 2117 }; 2118 2119 l2_cache15: cache-controller-15 { 2120 compatible = "cache"; 2121 cache-block-size = <64>; 2122 cache-level = <2>; 2123 cache-size = <1048576>; 2124 cache-sets = <1024>; 2125 cache-unified; 2126 }; 2127 }; 2128}; 2129