1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/ { 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 timebase-frequency = <50000000>; 11 12 cpu-map { 13 socket0 { 14 cluster0 { 15 core0 { 16 cpu = <&cpu0>; 17 }; 18 core1 { 19 cpu = <&cpu1>; 20 }; 21 core2 { 22 cpu = <&cpu2>; 23 }; 24 core3 { 25 cpu = <&cpu3>; 26 }; 27 }; 28 29 cluster1 { 30 core0 { 31 cpu = <&cpu4>; 32 }; 33 core1 { 34 cpu = <&cpu5>; 35 }; 36 core2 { 37 cpu = <&cpu6>; 38 }; 39 core3 { 40 cpu = <&cpu7>; 41 }; 42 }; 43 44 cluster2 { 45 core0 { 46 cpu = <&cpu16>; 47 }; 48 core1 { 49 cpu = <&cpu17>; 50 }; 51 core2 { 52 cpu = <&cpu18>; 53 }; 54 core3 { 55 cpu = <&cpu19>; 56 }; 57 }; 58 59 cluster3 { 60 core0 { 61 cpu = <&cpu20>; 62 }; 63 core1 { 64 cpu = <&cpu21>; 65 }; 66 core2 { 67 cpu = <&cpu22>; 68 }; 69 core3 { 70 cpu = <&cpu23>; 71 }; 72 }; 73 74 cluster4 { 75 core0 { 76 cpu = <&cpu8>; 77 }; 78 core1 { 79 cpu = <&cpu9>; 80 }; 81 core2 { 82 cpu = <&cpu10>; 83 }; 84 core3 { 85 cpu = <&cpu11>; 86 }; 87 }; 88 89 cluster5 { 90 core0 { 91 cpu = <&cpu12>; 92 }; 93 core1 { 94 cpu = <&cpu13>; 95 }; 96 core2 { 97 cpu = <&cpu14>; 98 }; 99 core3 { 100 cpu = <&cpu15>; 101 }; 102 }; 103 104 cluster6 { 105 core0 { 106 cpu = <&cpu24>; 107 }; 108 core1 { 109 cpu = <&cpu25>; 110 }; 111 core2 { 112 cpu = <&cpu26>; 113 }; 114 core3 { 115 cpu = <&cpu27>; 116 }; 117 }; 118 119 cluster7 { 120 core0 { 121 cpu = <&cpu28>; 122 }; 123 core1 { 124 cpu = <&cpu29>; 125 }; 126 core2 { 127 cpu = <&cpu30>; 128 }; 129 core3 { 130 cpu = <&cpu31>; 131 }; 132 }; 133 134 cluster8 { 135 core0 { 136 cpu = <&cpu32>; 137 }; 138 core1 { 139 cpu = <&cpu33>; 140 }; 141 core2 { 142 cpu = <&cpu34>; 143 }; 144 core3 { 145 cpu = <&cpu35>; 146 }; 147 }; 148 149 cluster9 { 150 core0 { 151 cpu = <&cpu36>; 152 }; 153 core1 { 154 cpu = <&cpu37>; 155 }; 156 core2 { 157 cpu = <&cpu38>; 158 }; 159 core3 { 160 cpu = <&cpu39>; 161 }; 162 }; 163 164 cluster10 { 165 core0 { 166 cpu = <&cpu48>; 167 }; 168 core1 { 169 cpu = <&cpu49>; 170 }; 171 core2 { 172 cpu = <&cpu50>; 173 }; 174 core3 { 175 cpu = <&cpu51>; 176 }; 177 }; 178 179 cluster11 { 180 core0 { 181 cpu = <&cpu52>; 182 }; 183 core1 { 184 cpu = <&cpu53>; 185 }; 186 core2 { 187 cpu = <&cpu54>; 188 }; 189 core3 { 190 cpu = <&cpu55>; 191 }; 192 }; 193 194 cluster12 { 195 core0 { 196 cpu = <&cpu40>; 197 }; 198 core1 { 199 cpu = <&cpu41>; 200 }; 201 core2 { 202 cpu = <&cpu42>; 203 }; 204 core3 { 205 cpu = <&cpu43>; 206 }; 207 }; 208 209 cluster13 { 210 core0 { 211 cpu = <&cpu44>; 212 }; 213 core1 { 214 cpu = <&cpu45>; 215 }; 216 core2 { 217 cpu = <&cpu46>; 218 }; 219 core3 { 220 cpu = <&cpu47>; 221 }; 222 }; 223 224 cluster14 { 225 core0 { 226 cpu = <&cpu56>; 227 }; 228 core1 { 229 cpu = <&cpu57>; 230 }; 231 core2 { 232 cpu = <&cpu58>; 233 }; 234 core3 { 235 cpu = <&cpu59>; 236 }; 237 }; 238 239 cluster15 { 240 core0 { 241 cpu = <&cpu60>; 242 }; 243 core1 { 244 cpu = <&cpu61>; 245 }; 246 core2 { 247 cpu = <&cpu62>; 248 }; 249 core3 { 250 cpu = <&cpu63>; 251 }; 252 }; 253 }; 254 }; 255 256 cpu0: cpu@0 { 257 compatible = "thead,c920", "riscv"; 258 device_type = "cpu"; 259 riscv,isa = "rv64imafdc"; 260 riscv,isa-base = "rv64i"; 261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 262 "zicntr", "zicsr", "zifencei", 263 "zihpm"; 264 reg = <0>; 265 i-cache-block-size = <64>; 266 i-cache-size = <65536>; 267 i-cache-sets = <512>; 268 d-cache-block-size = <64>; 269 d-cache-size = <65536>; 270 d-cache-sets = <512>; 271 next-level-cache = <&l2_cache0>; 272 mmu-type = "riscv,sv39"; 273 274 cpu0_intc: interrupt-controller { 275 compatible = "riscv,cpu-intc"; 276 interrupt-controller; 277 #interrupt-cells = <1>; 278 }; 279 }; 280 281 cpu1: cpu@1 { 282 compatible = "thead,c920", "riscv"; 283 device_type = "cpu"; 284 riscv,isa = "rv64imafdc"; 285 riscv,isa-base = "rv64i"; 286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 287 "zicntr", "zicsr", "zifencei", 288 "zihpm"; 289 reg = <1>; 290 i-cache-block-size = <64>; 291 i-cache-size = <65536>; 292 i-cache-sets = <512>; 293 d-cache-block-size = <64>; 294 d-cache-size = <65536>; 295 d-cache-sets = <512>; 296 next-level-cache = <&l2_cache0>; 297 mmu-type = "riscv,sv39"; 298 299 cpu1_intc: interrupt-controller { 300 compatible = "riscv,cpu-intc"; 301 interrupt-controller; 302 #interrupt-cells = <1>; 303 }; 304 }; 305 306 cpu2: cpu@2 { 307 compatible = "thead,c920", "riscv"; 308 device_type = "cpu"; 309 riscv,isa = "rv64imafdc"; 310 riscv,isa-base = "rv64i"; 311 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 312 "zicntr", "zicsr", "zifencei", 313 "zihpm"; 314 reg = <2>; 315 i-cache-block-size = <64>; 316 i-cache-size = <65536>; 317 i-cache-sets = <512>; 318 d-cache-block-size = <64>; 319 d-cache-size = <65536>; 320 d-cache-sets = <512>; 321 next-level-cache = <&l2_cache0>; 322 mmu-type = "riscv,sv39"; 323 324 cpu2_intc: interrupt-controller { 325 compatible = "riscv,cpu-intc"; 326 interrupt-controller; 327 #interrupt-cells = <1>; 328 }; 329 }; 330 331 cpu3: cpu@3 { 332 compatible = "thead,c920", "riscv"; 333 device_type = "cpu"; 334 riscv,isa = "rv64imafdc"; 335 riscv,isa-base = "rv64i"; 336 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 337 "zicntr", "zicsr", "zifencei", 338 "zihpm"; 339 reg = <3>; 340 i-cache-block-size = <64>; 341 i-cache-size = <65536>; 342 i-cache-sets = <512>; 343 d-cache-block-size = <64>; 344 d-cache-size = <65536>; 345 d-cache-sets = <512>; 346 next-level-cache = <&l2_cache0>; 347 mmu-type = "riscv,sv39"; 348 349 cpu3_intc: interrupt-controller { 350 compatible = "riscv,cpu-intc"; 351 interrupt-controller; 352 #interrupt-cells = <1>; 353 }; 354 }; 355 356 cpu4: cpu@4 { 357 compatible = "thead,c920", "riscv"; 358 device_type = "cpu"; 359 riscv,isa = "rv64imafdc"; 360 riscv,isa-base = "rv64i"; 361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 362 "zicntr", "zicsr", "zifencei", 363 "zihpm"; 364 reg = <4>; 365 i-cache-block-size = <64>; 366 i-cache-size = <65536>; 367 i-cache-sets = <512>; 368 d-cache-block-size = <64>; 369 d-cache-size = <65536>; 370 d-cache-sets = <512>; 371 next-level-cache = <&l2_cache1>; 372 mmu-type = "riscv,sv39"; 373 374 cpu4_intc: interrupt-controller { 375 compatible = "riscv,cpu-intc"; 376 interrupt-controller; 377 #interrupt-cells = <1>; 378 }; 379 }; 380 381 cpu5: cpu@5 { 382 compatible = "thead,c920", "riscv"; 383 device_type = "cpu"; 384 riscv,isa = "rv64imafdc"; 385 riscv,isa-base = "rv64i"; 386 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 387 "zicntr", "zicsr", "zifencei", 388 "zihpm"; 389 reg = <5>; 390 i-cache-block-size = <64>; 391 i-cache-size = <65536>; 392 i-cache-sets = <512>; 393 d-cache-block-size = <64>; 394 d-cache-size = <65536>; 395 d-cache-sets = <512>; 396 next-level-cache = <&l2_cache1>; 397 mmu-type = "riscv,sv39"; 398 399 cpu5_intc: interrupt-controller { 400 compatible = "riscv,cpu-intc"; 401 interrupt-controller; 402 #interrupt-cells = <1>; 403 }; 404 }; 405 406 cpu6: cpu@6 { 407 compatible = "thead,c920", "riscv"; 408 device_type = "cpu"; 409 riscv,isa = "rv64imafdc"; 410 riscv,isa-base = "rv64i"; 411 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 412 "zicntr", "zicsr", "zifencei", 413 "zihpm"; 414 reg = <6>; 415 i-cache-block-size = <64>; 416 i-cache-size = <65536>; 417 i-cache-sets = <512>; 418 d-cache-block-size = <64>; 419 d-cache-size = <65536>; 420 d-cache-sets = <512>; 421 next-level-cache = <&l2_cache1>; 422 mmu-type = "riscv,sv39"; 423 424 cpu6_intc: interrupt-controller { 425 compatible = "riscv,cpu-intc"; 426 interrupt-controller; 427 #interrupt-cells = <1>; 428 }; 429 }; 430 431 cpu7: cpu@7 { 432 compatible = "thead,c920", "riscv"; 433 device_type = "cpu"; 434 riscv,isa = "rv64imafdc"; 435 riscv,isa-base = "rv64i"; 436 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 437 "zicntr", "zicsr", "zifencei", 438 "zihpm"; 439 reg = <7>; 440 i-cache-block-size = <64>; 441 i-cache-size = <65536>; 442 i-cache-sets = <512>; 443 d-cache-block-size = <64>; 444 d-cache-size = <65536>; 445 d-cache-sets = <512>; 446 next-level-cache = <&l2_cache1>; 447 mmu-type = "riscv,sv39"; 448 449 cpu7_intc: interrupt-controller { 450 compatible = "riscv,cpu-intc"; 451 interrupt-controller; 452 #interrupt-cells = <1>; 453 }; 454 }; 455 456 cpu8: cpu@8 { 457 compatible = "thead,c920", "riscv"; 458 device_type = "cpu"; 459 riscv,isa = "rv64imafdc"; 460 riscv,isa-base = "rv64i"; 461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 462 "zicntr", "zicsr", "zifencei", 463 "zihpm"; 464 reg = <8>; 465 i-cache-block-size = <64>; 466 i-cache-size = <65536>; 467 i-cache-sets = <512>; 468 d-cache-block-size = <64>; 469 d-cache-size = <65536>; 470 d-cache-sets = <512>; 471 next-level-cache = <&l2_cache4>; 472 mmu-type = "riscv,sv39"; 473 474 cpu8_intc: interrupt-controller { 475 compatible = "riscv,cpu-intc"; 476 interrupt-controller; 477 #interrupt-cells = <1>; 478 }; 479 }; 480 481 cpu9: cpu@9 { 482 compatible = "thead,c920", "riscv"; 483 device_type = "cpu"; 484 riscv,isa = "rv64imafdc"; 485 riscv,isa-base = "rv64i"; 486 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 487 "zicntr", "zicsr", "zifencei", 488 "zihpm"; 489 reg = <9>; 490 i-cache-block-size = <64>; 491 i-cache-size = <65536>; 492 i-cache-sets = <512>; 493 d-cache-block-size = <64>; 494 d-cache-size = <65536>; 495 d-cache-sets = <512>; 496 next-level-cache = <&l2_cache4>; 497 mmu-type = "riscv,sv39"; 498 499 cpu9_intc: interrupt-controller { 500 compatible = "riscv,cpu-intc"; 501 interrupt-controller; 502 #interrupt-cells = <1>; 503 }; 504 }; 505 506 cpu10: cpu@10 { 507 compatible = "thead,c920", "riscv"; 508 device_type = "cpu"; 509 riscv,isa = "rv64imafdc"; 510 riscv,isa-base = "rv64i"; 511 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 512 "zicntr", "zicsr", "zifencei", 513 "zihpm"; 514 reg = <10>; 515 i-cache-block-size = <64>; 516 i-cache-size = <65536>; 517 i-cache-sets = <512>; 518 d-cache-block-size = <64>; 519 d-cache-size = <65536>; 520 d-cache-sets = <512>; 521 next-level-cache = <&l2_cache4>; 522 mmu-type = "riscv,sv39"; 523 524 cpu10_intc: interrupt-controller { 525 compatible = "riscv,cpu-intc"; 526 interrupt-controller; 527 #interrupt-cells = <1>; 528 }; 529 }; 530 531 cpu11: cpu@11 { 532 compatible = "thead,c920", "riscv"; 533 device_type = "cpu"; 534 riscv,isa = "rv64imafdc"; 535 riscv,isa-base = "rv64i"; 536 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 537 "zicntr", "zicsr", "zifencei", 538 "zihpm"; 539 reg = <11>; 540 i-cache-block-size = <64>; 541 i-cache-size = <65536>; 542 i-cache-sets = <512>; 543 d-cache-block-size = <64>; 544 d-cache-size = <65536>; 545 d-cache-sets = <512>; 546 next-level-cache = <&l2_cache4>; 547 mmu-type = "riscv,sv39"; 548 549 cpu11_intc: interrupt-controller { 550 compatible = "riscv,cpu-intc"; 551 interrupt-controller; 552 #interrupt-cells = <1>; 553 }; 554 }; 555 556 cpu12: cpu@12 { 557 compatible = "thead,c920", "riscv"; 558 device_type = "cpu"; 559 riscv,isa = "rv64imafdc"; 560 riscv,isa-base = "rv64i"; 561 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 562 "zicntr", "zicsr", "zifencei", 563 "zihpm"; 564 reg = <12>; 565 i-cache-block-size = <64>; 566 i-cache-size = <65536>; 567 i-cache-sets = <512>; 568 d-cache-block-size = <64>; 569 d-cache-size = <65536>; 570 d-cache-sets = <512>; 571 next-level-cache = <&l2_cache5>; 572 mmu-type = "riscv,sv39"; 573 574 cpu12_intc: interrupt-controller { 575 compatible = "riscv,cpu-intc"; 576 interrupt-controller; 577 #interrupt-cells = <1>; 578 }; 579 }; 580 581 cpu13: cpu@13 { 582 compatible = "thead,c920", "riscv"; 583 device_type = "cpu"; 584 riscv,isa = "rv64imafdc"; 585 riscv,isa-base = "rv64i"; 586 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 587 "zicntr", "zicsr", "zifencei", 588 "zihpm"; 589 reg = <13>; 590 i-cache-block-size = <64>; 591 i-cache-size = <65536>; 592 i-cache-sets = <512>; 593 d-cache-block-size = <64>; 594 d-cache-size = <65536>; 595 d-cache-sets = <512>; 596 next-level-cache = <&l2_cache5>; 597 mmu-type = "riscv,sv39"; 598 599 cpu13_intc: interrupt-controller { 600 compatible = "riscv,cpu-intc"; 601 interrupt-controller; 602 #interrupt-cells = <1>; 603 }; 604 }; 605 606 cpu14: cpu@14 { 607 compatible = "thead,c920", "riscv"; 608 device_type = "cpu"; 609 riscv,isa = "rv64imafdc"; 610 riscv,isa-base = "rv64i"; 611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 612 "zicntr", "zicsr", "zifencei", 613 "zihpm"; 614 reg = <14>; 615 i-cache-block-size = <64>; 616 i-cache-size = <65536>; 617 i-cache-sets = <512>; 618 d-cache-block-size = <64>; 619 d-cache-size = <65536>; 620 d-cache-sets = <512>; 621 next-level-cache = <&l2_cache5>; 622 mmu-type = "riscv,sv39"; 623 624 cpu14_intc: interrupt-controller { 625 compatible = "riscv,cpu-intc"; 626 interrupt-controller; 627 #interrupt-cells = <1>; 628 }; 629 }; 630 631 cpu15: cpu@15 { 632 compatible = "thead,c920", "riscv"; 633 device_type = "cpu"; 634 riscv,isa = "rv64imafdc"; 635 riscv,isa-base = "rv64i"; 636 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 637 "zicntr", "zicsr", "zifencei", 638 "zihpm"; 639 reg = <15>; 640 i-cache-block-size = <64>; 641 i-cache-size = <65536>; 642 i-cache-sets = <512>; 643 d-cache-block-size = <64>; 644 d-cache-size = <65536>; 645 d-cache-sets = <512>; 646 next-level-cache = <&l2_cache5>; 647 mmu-type = "riscv,sv39"; 648 649 cpu15_intc: interrupt-controller { 650 compatible = "riscv,cpu-intc"; 651 interrupt-controller; 652 #interrupt-cells = <1>; 653 }; 654 }; 655 656 cpu16: cpu@16 { 657 compatible = "thead,c920", "riscv"; 658 device_type = "cpu"; 659 riscv,isa = "rv64imafdc"; 660 riscv,isa-base = "rv64i"; 661 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 662 "zicntr", "zicsr", "zifencei", 663 "zihpm"; 664 reg = <16>; 665 i-cache-block-size = <64>; 666 i-cache-size = <65536>; 667 i-cache-sets = <512>; 668 d-cache-block-size = <64>; 669 d-cache-size = <65536>; 670 d-cache-sets = <512>; 671 next-level-cache = <&l2_cache2>; 672 mmu-type = "riscv,sv39"; 673 674 cpu16_intc: interrupt-controller { 675 compatible = "riscv,cpu-intc"; 676 interrupt-controller; 677 #interrupt-cells = <1>; 678 }; 679 }; 680 681 cpu17: cpu@17 { 682 compatible = "thead,c920", "riscv"; 683 device_type = "cpu"; 684 riscv,isa = "rv64imafdc"; 685 riscv,isa-base = "rv64i"; 686 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 687 "zicntr", "zicsr", "zifencei", 688 "zihpm"; 689 reg = <17>; 690 i-cache-block-size = <64>; 691 i-cache-size = <65536>; 692 i-cache-sets = <512>; 693 d-cache-block-size = <64>; 694 d-cache-size = <65536>; 695 d-cache-sets = <512>; 696 next-level-cache = <&l2_cache2>; 697 mmu-type = "riscv,sv39"; 698 699 cpu17_intc: interrupt-controller { 700 compatible = "riscv,cpu-intc"; 701 interrupt-controller; 702 #interrupt-cells = <1>; 703 }; 704 }; 705 706 cpu18: cpu@18 { 707 compatible = "thead,c920", "riscv"; 708 device_type = "cpu"; 709 riscv,isa = "rv64imafdc"; 710 riscv,isa-base = "rv64i"; 711 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 712 "zicntr", "zicsr", "zifencei", 713 "zihpm"; 714 reg = <18>; 715 i-cache-block-size = <64>; 716 i-cache-size = <65536>; 717 i-cache-sets = <512>; 718 d-cache-block-size = <64>; 719 d-cache-size = <65536>; 720 d-cache-sets = <512>; 721 next-level-cache = <&l2_cache2>; 722 mmu-type = "riscv,sv39"; 723 724 cpu18_intc: interrupt-controller { 725 compatible = "riscv,cpu-intc"; 726 interrupt-controller; 727 #interrupt-cells = <1>; 728 }; 729 }; 730 731 cpu19: cpu@19 { 732 compatible = "thead,c920", "riscv"; 733 device_type = "cpu"; 734 riscv,isa = "rv64imafdc"; 735 riscv,isa-base = "rv64i"; 736 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 737 "zicntr", "zicsr", "zifencei", 738 "zihpm"; 739 reg = <19>; 740 i-cache-block-size = <64>; 741 i-cache-size = <65536>; 742 i-cache-sets = <512>; 743 d-cache-block-size = <64>; 744 d-cache-size = <65536>; 745 d-cache-sets = <512>; 746 next-level-cache = <&l2_cache2>; 747 mmu-type = "riscv,sv39"; 748 749 cpu19_intc: interrupt-controller { 750 compatible = "riscv,cpu-intc"; 751 interrupt-controller; 752 #interrupt-cells = <1>; 753 }; 754 }; 755 756 cpu20: cpu@20 { 757 compatible = "thead,c920", "riscv"; 758 device_type = "cpu"; 759 riscv,isa = "rv64imafdc"; 760 riscv,isa-base = "rv64i"; 761 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 762 "zicntr", "zicsr", "zifencei", 763 "zihpm"; 764 reg = <20>; 765 i-cache-block-size = <64>; 766 i-cache-size = <65536>; 767 i-cache-sets = <512>; 768 d-cache-block-size = <64>; 769 d-cache-size = <65536>; 770 d-cache-sets = <512>; 771 next-level-cache = <&l2_cache3>; 772 mmu-type = "riscv,sv39"; 773 774 cpu20_intc: interrupt-controller { 775 compatible = "riscv,cpu-intc"; 776 interrupt-controller; 777 #interrupt-cells = <1>; 778 }; 779 }; 780 781 cpu21: cpu@21 { 782 compatible = "thead,c920", "riscv"; 783 device_type = "cpu"; 784 riscv,isa = "rv64imafdc"; 785 riscv,isa-base = "rv64i"; 786 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 787 "zicntr", "zicsr", "zifencei", 788 "zihpm"; 789 reg = <21>; 790 i-cache-block-size = <64>; 791 i-cache-size = <65536>; 792 i-cache-sets = <512>; 793 d-cache-block-size = <64>; 794 d-cache-size = <65536>; 795 d-cache-sets = <512>; 796 next-level-cache = <&l2_cache3>; 797 mmu-type = "riscv,sv39"; 798 799 cpu21_intc: interrupt-controller { 800 compatible = "riscv,cpu-intc"; 801 interrupt-controller; 802 #interrupt-cells = <1>; 803 }; 804 }; 805 806 cpu22: cpu@22 { 807 compatible = "thead,c920", "riscv"; 808 device_type = "cpu"; 809 riscv,isa = "rv64imafdc"; 810 riscv,isa-base = "rv64i"; 811 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 812 "zicntr", "zicsr", "zifencei", 813 "zihpm"; 814 reg = <22>; 815 i-cache-block-size = <64>; 816 i-cache-size = <65536>; 817 i-cache-sets = <512>; 818 d-cache-block-size = <64>; 819 d-cache-size = <65536>; 820 d-cache-sets = <512>; 821 next-level-cache = <&l2_cache3>; 822 mmu-type = "riscv,sv39"; 823 824 cpu22_intc: interrupt-controller { 825 compatible = "riscv,cpu-intc"; 826 interrupt-controller; 827 #interrupt-cells = <1>; 828 }; 829 }; 830 831 cpu23: cpu@23 { 832 compatible = "thead,c920", "riscv"; 833 device_type = "cpu"; 834 riscv,isa = "rv64imafdc"; 835 riscv,isa-base = "rv64i"; 836 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 837 "zicntr", "zicsr", "zifencei", 838 "zihpm"; 839 reg = <23>; 840 i-cache-block-size = <64>; 841 i-cache-size = <65536>; 842 i-cache-sets = <512>; 843 d-cache-block-size = <64>; 844 d-cache-size = <65536>; 845 d-cache-sets = <512>; 846 next-level-cache = <&l2_cache3>; 847 mmu-type = "riscv,sv39"; 848 849 cpu23_intc: interrupt-controller { 850 compatible = "riscv,cpu-intc"; 851 interrupt-controller; 852 #interrupt-cells = <1>; 853 }; 854 }; 855 856 cpu24: cpu@24 { 857 compatible = "thead,c920", "riscv"; 858 device_type = "cpu"; 859 riscv,isa = "rv64imafdc"; 860 riscv,isa-base = "rv64i"; 861 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 862 "zicntr", "zicsr", "zifencei", 863 "zihpm"; 864 reg = <24>; 865 i-cache-block-size = <64>; 866 i-cache-size = <65536>; 867 i-cache-sets = <512>; 868 d-cache-block-size = <64>; 869 d-cache-size = <65536>; 870 d-cache-sets = <512>; 871 next-level-cache = <&l2_cache6>; 872 mmu-type = "riscv,sv39"; 873 874 cpu24_intc: interrupt-controller { 875 compatible = "riscv,cpu-intc"; 876 interrupt-controller; 877 #interrupt-cells = <1>; 878 }; 879 }; 880 881 cpu25: cpu@25 { 882 compatible = "thead,c920", "riscv"; 883 device_type = "cpu"; 884 riscv,isa = "rv64imafdc"; 885 riscv,isa-base = "rv64i"; 886 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 887 "zicntr", "zicsr", "zifencei", 888 "zihpm"; 889 reg = <25>; 890 i-cache-block-size = <64>; 891 i-cache-size = <65536>; 892 i-cache-sets = <512>; 893 d-cache-block-size = <64>; 894 d-cache-size = <65536>; 895 d-cache-sets = <512>; 896 next-level-cache = <&l2_cache6>; 897 mmu-type = "riscv,sv39"; 898 899 cpu25_intc: interrupt-controller { 900 compatible = "riscv,cpu-intc"; 901 interrupt-controller; 902 #interrupt-cells = <1>; 903 }; 904 }; 905 906 cpu26: cpu@26 { 907 compatible = "thead,c920", "riscv"; 908 device_type = "cpu"; 909 riscv,isa = "rv64imafdc"; 910 riscv,isa-base = "rv64i"; 911 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 912 "zicntr", "zicsr", "zifencei", 913 "zihpm"; 914 reg = <26>; 915 i-cache-block-size = <64>; 916 i-cache-size = <65536>; 917 i-cache-sets = <512>; 918 d-cache-block-size = <64>; 919 d-cache-size = <65536>; 920 d-cache-sets = <512>; 921 next-level-cache = <&l2_cache6>; 922 mmu-type = "riscv,sv39"; 923 924 cpu26_intc: interrupt-controller { 925 compatible = "riscv,cpu-intc"; 926 interrupt-controller; 927 #interrupt-cells = <1>; 928 }; 929 }; 930 931 cpu27: cpu@27 { 932 compatible = "thead,c920", "riscv"; 933 device_type = "cpu"; 934 riscv,isa = "rv64imafdc"; 935 riscv,isa-base = "rv64i"; 936 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 937 "zicntr", "zicsr", "zifencei", 938 "zihpm"; 939 reg = <27>; 940 i-cache-block-size = <64>; 941 i-cache-size = <65536>; 942 i-cache-sets = <512>; 943 d-cache-block-size = <64>; 944 d-cache-size = <65536>; 945 d-cache-sets = <512>; 946 next-level-cache = <&l2_cache6>; 947 mmu-type = "riscv,sv39"; 948 949 cpu27_intc: interrupt-controller { 950 compatible = "riscv,cpu-intc"; 951 interrupt-controller; 952 #interrupt-cells = <1>; 953 }; 954 }; 955 956 cpu28: cpu@28 { 957 compatible = "thead,c920", "riscv"; 958 device_type = "cpu"; 959 riscv,isa = "rv64imafdc"; 960 riscv,isa-base = "rv64i"; 961 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 962 "zicntr", "zicsr", "zifencei", 963 "zihpm"; 964 reg = <28>; 965 i-cache-block-size = <64>; 966 i-cache-size = <65536>; 967 i-cache-sets = <512>; 968 d-cache-block-size = <64>; 969 d-cache-size = <65536>; 970 d-cache-sets = <512>; 971 next-level-cache = <&l2_cache7>; 972 mmu-type = "riscv,sv39"; 973 974 cpu28_intc: interrupt-controller { 975 compatible = "riscv,cpu-intc"; 976 interrupt-controller; 977 #interrupt-cells = <1>; 978 }; 979 }; 980 981 cpu29: cpu@29 { 982 compatible = "thead,c920", "riscv"; 983 device_type = "cpu"; 984 riscv,isa = "rv64imafdc"; 985 riscv,isa-base = "rv64i"; 986 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 987 "zicntr", "zicsr", "zifencei", 988 "zihpm"; 989 reg = <29>; 990 i-cache-block-size = <64>; 991 i-cache-size = <65536>; 992 i-cache-sets = <512>; 993 d-cache-block-size = <64>; 994 d-cache-size = <65536>; 995 d-cache-sets = <512>; 996 next-level-cache = <&l2_cache7>; 997 mmu-type = "riscv,sv39"; 998 999 cpu29_intc: interrupt-controller { 1000 compatible = "riscv,cpu-intc"; 1001 interrupt-controller; 1002 #interrupt-cells = <1>; 1003 }; 1004 }; 1005 1006 cpu30: cpu@30 { 1007 compatible = "thead,c920", "riscv"; 1008 device_type = "cpu"; 1009 riscv,isa = "rv64imafdc"; 1010 riscv,isa-base = "rv64i"; 1011 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1012 "zicntr", "zicsr", "zifencei", 1013 "zihpm"; 1014 reg = <30>; 1015 i-cache-block-size = <64>; 1016 i-cache-size = <65536>; 1017 i-cache-sets = <512>; 1018 d-cache-block-size = <64>; 1019 d-cache-size = <65536>; 1020 d-cache-sets = <512>; 1021 next-level-cache = <&l2_cache7>; 1022 mmu-type = "riscv,sv39"; 1023 1024 cpu30_intc: interrupt-controller { 1025 compatible = "riscv,cpu-intc"; 1026 interrupt-controller; 1027 #interrupt-cells = <1>; 1028 }; 1029 }; 1030 1031 cpu31: cpu@31 { 1032 compatible = "thead,c920", "riscv"; 1033 device_type = "cpu"; 1034 riscv,isa = "rv64imafdc"; 1035 riscv,isa-base = "rv64i"; 1036 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1037 "zicntr", "zicsr", "zifencei", 1038 "zihpm"; 1039 reg = <31>; 1040 i-cache-block-size = <64>; 1041 i-cache-size = <65536>; 1042 i-cache-sets = <512>; 1043 d-cache-block-size = <64>; 1044 d-cache-size = <65536>; 1045 d-cache-sets = <512>; 1046 next-level-cache = <&l2_cache7>; 1047 mmu-type = "riscv,sv39"; 1048 1049 cpu31_intc: interrupt-controller { 1050 compatible = "riscv,cpu-intc"; 1051 interrupt-controller; 1052 #interrupt-cells = <1>; 1053 }; 1054 }; 1055 1056 cpu32: cpu@32 { 1057 compatible = "thead,c920", "riscv"; 1058 device_type = "cpu"; 1059 riscv,isa = "rv64imafdc"; 1060 riscv,isa-base = "rv64i"; 1061 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1062 "zicntr", "zicsr", "zifencei", 1063 "zihpm"; 1064 reg = <32>; 1065 i-cache-block-size = <64>; 1066 i-cache-size = <65536>; 1067 i-cache-sets = <512>; 1068 d-cache-block-size = <64>; 1069 d-cache-size = <65536>; 1070 d-cache-sets = <512>; 1071 next-level-cache = <&l2_cache8>; 1072 mmu-type = "riscv,sv39"; 1073 1074 cpu32_intc: interrupt-controller { 1075 compatible = "riscv,cpu-intc"; 1076 interrupt-controller; 1077 #interrupt-cells = <1>; 1078 }; 1079 }; 1080 1081 cpu33: cpu@33 { 1082 compatible = "thead,c920", "riscv"; 1083 device_type = "cpu"; 1084 riscv,isa = "rv64imafdc"; 1085 riscv,isa-base = "rv64i"; 1086 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1087 "zicntr", "zicsr", "zifencei", 1088 "zihpm"; 1089 reg = <33>; 1090 i-cache-block-size = <64>; 1091 i-cache-size = <65536>; 1092 i-cache-sets = <512>; 1093 d-cache-block-size = <64>; 1094 d-cache-size = <65536>; 1095 d-cache-sets = <512>; 1096 next-level-cache = <&l2_cache8>; 1097 mmu-type = "riscv,sv39"; 1098 1099 cpu33_intc: interrupt-controller { 1100 compatible = "riscv,cpu-intc"; 1101 interrupt-controller; 1102 #interrupt-cells = <1>; 1103 }; 1104 }; 1105 1106 cpu34: cpu@34 { 1107 compatible = "thead,c920", "riscv"; 1108 device_type = "cpu"; 1109 riscv,isa = "rv64imafdc"; 1110 riscv,isa-base = "rv64i"; 1111 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1112 "zicntr", "zicsr", "zifencei", 1113 "zihpm"; 1114 reg = <34>; 1115 i-cache-block-size = <64>; 1116 i-cache-size = <65536>; 1117 i-cache-sets = <512>; 1118 d-cache-block-size = <64>; 1119 d-cache-size = <65536>; 1120 d-cache-sets = <512>; 1121 next-level-cache = <&l2_cache8>; 1122 mmu-type = "riscv,sv39"; 1123 1124 cpu34_intc: interrupt-controller { 1125 compatible = "riscv,cpu-intc"; 1126 interrupt-controller; 1127 #interrupt-cells = <1>; 1128 }; 1129 }; 1130 1131 cpu35: cpu@35 { 1132 compatible = "thead,c920", "riscv"; 1133 device_type = "cpu"; 1134 riscv,isa = "rv64imafdc"; 1135 riscv,isa-base = "rv64i"; 1136 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1137 "zicntr", "zicsr", "zifencei", 1138 "zihpm"; 1139 reg = <35>; 1140 i-cache-block-size = <64>; 1141 i-cache-size = <65536>; 1142 i-cache-sets = <512>; 1143 d-cache-block-size = <64>; 1144 d-cache-size = <65536>; 1145 d-cache-sets = <512>; 1146 next-level-cache = <&l2_cache8>; 1147 mmu-type = "riscv,sv39"; 1148 1149 cpu35_intc: interrupt-controller { 1150 compatible = "riscv,cpu-intc"; 1151 interrupt-controller; 1152 #interrupt-cells = <1>; 1153 }; 1154 }; 1155 1156 cpu36: cpu@36 { 1157 compatible = "thead,c920", "riscv"; 1158 device_type = "cpu"; 1159 riscv,isa = "rv64imafdc"; 1160 riscv,isa-base = "rv64i"; 1161 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1162 "zicntr", "zicsr", "zifencei", 1163 "zihpm"; 1164 reg = <36>; 1165 i-cache-block-size = <64>; 1166 i-cache-size = <65536>; 1167 i-cache-sets = <512>; 1168 d-cache-block-size = <64>; 1169 d-cache-size = <65536>; 1170 d-cache-sets = <512>; 1171 next-level-cache = <&l2_cache9>; 1172 mmu-type = "riscv,sv39"; 1173 1174 cpu36_intc: interrupt-controller { 1175 compatible = "riscv,cpu-intc"; 1176 interrupt-controller; 1177 #interrupt-cells = <1>; 1178 }; 1179 }; 1180 1181 cpu37: cpu@37 { 1182 compatible = "thead,c920", "riscv"; 1183 device_type = "cpu"; 1184 riscv,isa = "rv64imafdc"; 1185 riscv,isa-base = "rv64i"; 1186 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1187 "zicntr", "zicsr", "zifencei", 1188 "zihpm"; 1189 reg = <37>; 1190 i-cache-block-size = <64>; 1191 i-cache-size = <65536>; 1192 i-cache-sets = <512>; 1193 d-cache-block-size = <64>; 1194 d-cache-size = <65536>; 1195 d-cache-sets = <512>; 1196 next-level-cache = <&l2_cache9>; 1197 mmu-type = "riscv,sv39"; 1198 1199 cpu37_intc: interrupt-controller { 1200 compatible = "riscv,cpu-intc"; 1201 interrupt-controller; 1202 #interrupt-cells = <1>; 1203 }; 1204 }; 1205 1206 cpu38: cpu@38 { 1207 compatible = "thead,c920", "riscv"; 1208 device_type = "cpu"; 1209 riscv,isa = "rv64imafdc"; 1210 riscv,isa-base = "rv64i"; 1211 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1212 "zicntr", "zicsr", "zifencei", 1213 "zihpm"; 1214 reg = <38>; 1215 i-cache-block-size = <64>; 1216 i-cache-size = <65536>; 1217 i-cache-sets = <512>; 1218 d-cache-block-size = <64>; 1219 d-cache-size = <65536>; 1220 d-cache-sets = <512>; 1221 next-level-cache = <&l2_cache9>; 1222 mmu-type = "riscv,sv39"; 1223 1224 cpu38_intc: interrupt-controller { 1225 compatible = "riscv,cpu-intc"; 1226 interrupt-controller; 1227 #interrupt-cells = <1>; 1228 }; 1229 }; 1230 1231 cpu39: cpu@39 { 1232 compatible = "thead,c920", "riscv"; 1233 device_type = "cpu"; 1234 riscv,isa = "rv64imafdc"; 1235 riscv,isa-base = "rv64i"; 1236 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1237 "zicntr", "zicsr", "zifencei", 1238 "zihpm"; 1239 reg = <39>; 1240 i-cache-block-size = <64>; 1241 i-cache-size = <65536>; 1242 i-cache-sets = <512>; 1243 d-cache-block-size = <64>; 1244 d-cache-size = <65536>; 1245 d-cache-sets = <512>; 1246 next-level-cache = <&l2_cache9>; 1247 mmu-type = "riscv,sv39"; 1248 1249 cpu39_intc: interrupt-controller { 1250 compatible = "riscv,cpu-intc"; 1251 interrupt-controller; 1252 #interrupt-cells = <1>; 1253 }; 1254 }; 1255 1256 cpu40: cpu@40 { 1257 compatible = "thead,c920", "riscv"; 1258 device_type = "cpu"; 1259 riscv,isa = "rv64imafdc"; 1260 riscv,isa-base = "rv64i"; 1261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1262 "zicntr", "zicsr", "zifencei", 1263 "zihpm"; 1264 reg = <40>; 1265 i-cache-block-size = <64>; 1266 i-cache-size = <65536>; 1267 i-cache-sets = <512>; 1268 d-cache-block-size = <64>; 1269 d-cache-size = <65536>; 1270 d-cache-sets = <512>; 1271 next-level-cache = <&l2_cache12>; 1272 mmu-type = "riscv,sv39"; 1273 1274 cpu40_intc: interrupt-controller { 1275 compatible = "riscv,cpu-intc"; 1276 interrupt-controller; 1277 #interrupt-cells = <1>; 1278 }; 1279 }; 1280 1281 cpu41: cpu@41 { 1282 compatible = "thead,c920", "riscv"; 1283 device_type = "cpu"; 1284 riscv,isa = "rv64imafdc"; 1285 riscv,isa-base = "rv64i"; 1286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1287 "zicntr", "zicsr", "zifencei", 1288 "zihpm"; 1289 reg = <41>; 1290 i-cache-block-size = <64>; 1291 i-cache-size = <65536>; 1292 i-cache-sets = <512>; 1293 d-cache-block-size = <64>; 1294 d-cache-size = <65536>; 1295 d-cache-sets = <512>; 1296 next-level-cache = <&l2_cache12>; 1297 mmu-type = "riscv,sv39"; 1298 1299 cpu41_intc: interrupt-controller { 1300 compatible = "riscv,cpu-intc"; 1301 interrupt-controller; 1302 #interrupt-cells = <1>; 1303 }; 1304 }; 1305 1306 cpu42: cpu@42 { 1307 compatible = "thead,c920", "riscv"; 1308 device_type = "cpu"; 1309 riscv,isa = "rv64imafdc"; 1310 riscv,isa-base = "rv64i"; 1311 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1312 "zicntr", "zicsr", "zifencei", 1313 "zihpm"; 1314 reg = <42>; 1315 i-cache-block-size = <64>; 1316 i-cache-size = <65536>; 1317 i-cache-sets = <512>; 1318 d-cache-block-size = <64>; 1319 d-cache-size = <65536>; 1320 d-cache-sets = <512>; 1321 next-level-cache = <&l2_cache12>; 1322 mmu-type = "riscv,sv39"; 1323 1324 cpu42_intc: interrupt-controller { 1325 compatible = "riscv,cpu-intc"; 1326 interrupt-controller; 1327 #interrupt-cells = <1>; 1328 }; 1329 }; 1330 1331 cpu43: cpu@43 { 1332 compatible = "thead,c920", "riscv"; 1333 device_type = "cpu"; 1334 riscv,isa = "rv64imafdc"; 1335 riscv,isa-base = "rv64i"; 1336 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1337 "zicntr", "zicsr", "zifencei", 1338 "zihpm"; 1339 reg = <43>; 1340 i-cache-block-size = <64>; 1341 i-cache-size = <65536>; 1342 i-cache-sets = <512>; 1343 d-cache-block-size = <64>; 1344 d-cache-size = <65536>; 1345 d-cache-sets = <512>; 1346 next-level-cache = <&l2_cache12>; 1347 mmu-type = "riscv,sv39"; 1348 1349 cpu43_intc: interrupt-controller { 1350 compatible = "riscv,cpu-intc"; 1351 interrupt-controller; 1352 #interrupt-cells = <1>; 1353 }; 1354 }; 1355 1356 cpu44: cpu@44 { 1357 compatible = "thead,c920", "riscv"; 1358 device_type = "cpu"; 1359 riscv,isa = "rv64imafdc"; 1360 riscv,isa-base = "rv64i"; 1361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1362 "zicntr", "zicsr", "zifencei", 1363 "zihpm"; 1364 reg = <44>; 1365 i-cache-block-size = <64>; 1366 i-cache-size = <65536>; 1367 i-cache-sets = <512>; 1368 d-cache-block-size = <64>; 1369 d-cache-size = <65536>; 1370 d-cache-sets = <512>; 1371 next-level-cache = <&l2_cache13>; 1372 mmu-type = "riscv,sv39"; 1373 1374 cpu44_intc: interrupt-controller { 1375 compatible = "riscv,cpu-intc"; 1376 interrupt-controller; 1377 #interrupt-cells = <1>; 1378 }; 1379 }; 1380 1381 cpu45: cpu@45 { 1382 compatible = "thead,c920", "riscv"; 1383 device_type = "cpu"; 1384 riscv,isa = "rv64imafdc"; 1385 riscv,isa-base = "rv64i"; 1386 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1387 "zicntr", "zicsr", "zifencei", 1388 "zihpm"; 1389 reg = <45>; 1390 i-cache-block-size = <64>; 1391 i-cache-size = <65536>; 1392 i-cache-sets = <512>; 1393 d-cache-block-size = <64>; 1394 d-cache-size = <65536>; 1395 d-cache-sets = <512>; 1396 next-level-cache = <&l2_cache13>; 1397 mmu-type = "riscv,sv39"; 1398 1399 cpu45_intc: interrupt-controller { 1400 compatible = "riscv,cpu-intc"; 1401 interrupt-controller; 1402 #interrupt-cells = <1>; 1403 }; 1404 }; 1405 1406 cpu46: cpu@46 { 1407 compatible = "thead,c920", "riscv"; 1408 device_type = "cpu"; 1409 riscv,isa = "rv64imafdc"; 1410 riscv,isa-base = "rv64i"; 1411 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1412 "zicntr", "zicsr", "zifencei", 1413 "zihpm"; 1414 reg = <46>; 1415 i-cache-block-size = <64>; 1416 i-cache-size = <65536>; 1417 i-cache-sets = <512>; 1418 d-cache-block-size = <64>; 1419 d-cache-size = <65536>; 1420 d-cache-sets = <512>; 1421 next-level-cache = <&l2_cache13>; 1422 mmu-type = "riscv,sv39"; 1423 1424 cpu46_intc: interrupt-controller { 1425 compatible = "riscv,cpu-intc"; 1426 interrupt-controller; 1427 #interrupt-cells = <1>; 1428 }; 1429 }; 1430 1431 cpu47: cpu@47 { 1432 compatible = "thead,c920", "riscv"; 1433 device_type = "cpu"; 1434 riscv,isa = "rv64imafdc"; 1435 riscv,isa-base = "rv64i"; 1436 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1437 "zicntr", "zicsr", "zifencei", 1438 "zihpm"; 1439 reg = <47>; 1440 i-cache-block-size = <64>; 1441 i-cache-size = <65536>; 1442 i-cache-sets = <512>; 1443 d-cache-block-size = <64>; 1444 d-cache-size = <65536>; 1445 d-cache-sets = <512>; 1446 next-level-cache = <&l2_cache13>; 1447 mmu-type = "riscv,sv39"; 1448 1449 cpu47_intc: interrupt-controller { 1450 compatible = "riscv,cpu-intc"; 1451 interrupt-controller; 1452 #interrupt-cells = <1>; 1453 }; 1454 }; 1455 1456 cpu48: cpu@48 { 1457 compatible = "thead,c920", "riscv"; 1458 device_type = "cpu"; 1459 riscv,isa = "rv64imafdc"; 1460 riscv,isa-base = "rv64i"; 1461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1462 "zicntr", "zicsr", "zifencei", 1463 "zihpm"; 1464 reg = <48>; 1465 i-cache-block-size = <64>; 1466 i-cache-size = <65536>; 1467 i-cache-sets = <512>; 1468 d-cache-block-size = <64>; 1469 d-cache-size = <65536>; 1470 d-cache-sets = <512>; 1471 next-level-cache = <&l2_cache10>; 1472 mmu-type = "riscv,sv39"; 1473 1474 cpu48_intc: interrupt-controller { 1475 compatible = "riscv,cpu-intc"; 1476 interrupt-controller; 1477 #interrupt-cells = <1>; 1478 }; 1479 }; 1480 1481 cpu49: cpu@49 { 1482 compatible = "thead,c920", "riscv"; 1483 device_type = "cpu"; 1484 riscv,isa = "rv64imafdc"; 1485 riscv,isa-base = "rv64i"; 1486 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1487 "zicntr", "zicsr", "zifencei", 1488 "zihpm"; 1489 reg = <49>; 1490 i-cache-block-size = <64>; 1491 i-cache-size = <65536>; 1492 i-cache-sets = <512>; 1493 d-cache-block-size = <64>; 1494 d-cache-size = <65536>; 1495 d-cache-sets = <512>; 1496 next-level-cache = <&l2_cache10>; 1497 mmu-type = "riscv,sv39"; 1498 1499 cpu49_intc: interrupt-controller { 1500 compatible = "riscv,cpu-intc"; 1501 interrupt-controller; 1502 #interrupt-cells = <1>; 1503 }; 1504 }; 1505 1506 cpu50: cpu@50 { 1507 compatible = "thead,c920", "riscv"; 1508 device_type = "cpu"; 1509 riscv,isa = "rv64imafdc"; 1510 riscv,isa-base = "rv64i"; 1511 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1512 "zicntr", "zicsr", "zifencei", 1513 "zihpm"; 1514 reg = <50>; 1515 i-cache-block-size = <64>; 1516 i-cache-size = <65536>; 1517 i-cache-sets = <512>; 1518 d-cache-block-size = <64>; 1519 d-cache-size = <65536>; 1520 d-cache-sets = <512>; 1521 next-level-cache = <&l2_cache10>; 1522 mmu-type = "riscv,sv39"; 1523 1524 cpu50_intc: interrupt-controller { 1525 compatible = "riscv,cpu-intc"; 1526 interrupt-controller; 1527 #interrupt-cells = <1>; 1528 }; 1529 }; 1530 1531 cpu51: cpu@51 { 1532 compatible = "thead,c920", "riscv"; 1533 device_type = "cpu"; 1534 riscv,isa = "rv64imafdc"; 1535 riscv,isa-base = "rv64i"; 1536 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1537 "zicntr", "zicsr", "zifencei", 1538 "zihpm"; 1539 reg = <51>; 1540 i-cache-block-size = <64>; 1541 i-cache-size = <65536>; 1542 i-cache-sets = <512>; 1543 d-cache-block-size = <64>; 1544 d-cache-size = <65536>; 1545 d-cache-sets = <512>; 1546 next-level-cache = <&l2_cache10>; 1547 mmu-type = "riscv,sv39"; 1548 1549 cpu51_intc: interrupt-controller { 1550 compatible = "riscv,cpu-intc"; 1551 interrupt-controller; 1552 #interrupt-cells = <1>; 1553 }; 1554 }; 1555 1556 cpu52: cpu@52 { 1557 compatible = "thead,c920", "riscv"; 1558 device_type = "cpu"; 1559 riscv,isa = "rv64imafdc"; 1560 riscv,isa-base = "rv64i"; 1561 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1562 "zicntr", "zicsr", "zifencei", 1563 "zihpm"; 1564 reg = <52>; 1565 i-cache-block-size = <64>; 1566 i-cache-size = <65536>; 1567 i-cache-sets = <512>; 1568 d-cache-block-size = <64>; 1569 d-cache-size = <65536>; 1570 d-cache-sets = <512>; 1571 next-level-cache = <&l2_cache11>; 1572 mmu-type = "riscv,sv39"; 1573 1574 cpu52_intc: interrupt-controller { 1575 compatible = "riscv,cpu-intc"; 1576 interrupt-controller; 1577 #interrupt-cells = <1>; 1578 }; 1579 }; 1580 1581 cpu53: cpu@53 { 1582 compatible = "thead,c920", "riscv"; 1583 device_type = "cpu"; 1584 riscv,isa = "rv64imafdc"; 1585 riscv,isa-base = "rv64i"; 1586 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1587 "zicntr", "zicsr", "zifencei", 1588 "zihpm"; 1589 reg = <53>; 1590 i-cache-block-size = <64>; 1591 i-cache-size = <65536>; 1592 i-cache-sets = <512>; 1593 d-cache-block-size = <64>; 1594 d-cache-size = <65536>; 1595 d-cache-sets = <512>; 1596 next-level-cache = <&l2_cache11>; 1597 mmu-type = "riscv,sv39"; 1598 1599 cpu53_intc: interrupt-controller { 1600 compatible = "riscv,cpu-intc"; 1601 interrupt-controller; 1602 #interrupt-cells = <1>; 1603 }; 1604 }; 1605 1606 cpu54: cpu@54 { 1607 compatible = "thead,c920", "riscv"; 1608 device_type = "cpu"; 1609 riscv,isa = "rv64imafdc"; 1610 riscv,isa-base = "rv64i"; 1611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1612 "zicntr", "zicsr", "zifencei", 1613 "zihpm"; 1614 reg = <54>; 1615 i-cache-block-size = <64>; 1616 i-cache-size = <65536>; 1617 i-cache-sets = <512>; 1618 d-cache-block-size = <64>; 1619 d-cache-size = <65536>; 1620 d-cache-sets = <512>; 1621 next-level-cache = <&l2_cache11>; 1622 mmu-type = "riscv,sv39"; 1623 1624 cpu54_intc: interrupt-controller { 1625 compatible = "riscv,cpu-intc"; 1626 interrupt-controller; 1627 #interrupt-cells = <1>; 1628 }; 1629 }; 1630 1631 cpu55: cpu@55 { 1632 compatible = "thead,c920", "riscv"; 1633 device_type = "cpu"; 1634 riscv,isa = "rv64imafdc"; 1635 riscv,isa-base = "rv64i"; 1636 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1637 "zicntr", "zicsr", "zifencei", 1638 "zihpm"; 1639 reg = <55>; 1640 i-cache-block-size = <64>; 1641 i-cache-size = <65536>; 1642 i-cache-sets = <512>; 1643 d-cache-block-size = <64>; 1644 d-cache-size = <65536>; 1645 d-cache-sets = <512>; 1646 next-level-cache = <&l2_cache11>; 1647 mmu-type = "riscv,sv39"; 1648 1649 cpu55_intc: interrupt-controller { 1650 compatible = "riscv,cpu-intc"; 1651 interrupt-controller; 1652 #interrupt-cells = <1>; 1653 }; 1654 }; 1655 1656 cpu56: cpu@56 { 1657 compatible = "thead,c920", "riscv"; 1658 device_type = "cpu"; 1659 riscv,isa = "rv64imafdc"; 1660 riscv,isa-base = "rv64i"; 1661 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1662 "zicntr", "zicsr", "zifencei", 1663 "zihpm"; 1664 reg = <56>; 1665 i-cache-block-size = <64>; 1666 i-cache-size = <65536>; 1667 i-cache-sets = <512>; 1668 d-cache-block-size = <64>; 1669 d-cache-size = <65536>; 1670 d-cache-sets = <512>; 1671 next-level-cache = <&l2_cache14>; 1672 mmu-type = "riscv,sv39"; 1673 1674 cpu56_intc: interrupt-controller { 1675 compatible = "riscv,cpu-intc"; 1676 interrupt-controller; 1677 #interrupt-cells = <1>; 1678 }; 1679 }; 1680 1681 cpu57: cpu@57 { 1682 compatible = "thead,c920", "riscv"; 1683 device_type = "cpu"; 1684 riscv,isa = "rv64imafdc"; 1685 riscv,isa-base = "rv64i"; 1686 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1687 "zicntr", "zicsr", "zifencei", 1688 "zihpm"; 1689 reg = <57>; 1690 i-cache-block-size = <64>; 1691 i-cache-size = <65536>; 1692 i-cache-sets = <512>; 1693 d-cache-block-size = <64>; 1694 d-cache-size = <65536>; 1695 d-cache-sets = <512>; 1696 next-level-cache = <&l2_cache14>; 1697 mmu-type = "riscv,sv39"; 1698 1699 cpu57_intc: interrupt-controller { 1700 compatible = "riscv,cpu-intc"; 1701 interrupt-controller; 1702 #interrupt-cells = <1>; 1703 }; 1704 }; 1705 1706 cpu58: cpu@58 { 1707 compatible = "thead,c920", "riscv"; 1708 device_type = "cpu"; 1709 riscv,isa = "rv64imafdc"; 1710 riscv,isa-base = "rv64i"; 1711 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1712 "zicntr", "zicsr", "zifencei", 1713 "zihpm"; 1714 reg = <58>; 1715 i-cache-block-size = <64>; 1716 i-cache-size = <65536>; 1717 i-cache-sets = <512>; 1718 d-cache-block-size = <64>; 1719 d-cache-size = <65536>; 1720 d-cache-sets = <512>; 1721 next-level-cache = <&l2_cache14>; 1722 mmu-type = "riscv,sv39"; 1723 1724 cpu58_intc: interrupt-controller { 1725 compatible = "riscv,cpu-intc"; 1726 interrupt-controller; 1727 #interrupt-cells = <1>; 1728 }; 1729 }; 1730 1731 cpu59: cpu@59 { 1732 compatible = "thead,c920", "riscv"; 1733 device_type = "cpu"; 1734 riscv,isa = "rv64imafdc"; 1735 riscv,isa-base = "rv64i"; 1736 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1737 "zicntr", "zicsr", "zifencei", 1738 "zihpm"; 1739 reg = <59>; 1740 i-cache-block-size = <64>; 1741 i-cache-size = <65536>; 1742 i-cache-sets = <512>; 1743 d-cache-block-size = <64>; 1744 d-cache-size = <65536>; 1745 d-cache-sets = <512>; 1746 next-level-cache = <&l2_cache14>; 1747 mmu-type = "riscv,sv39"; 1748 1749 cpu59_intc: interrupt-controller { 1750 compatible = "riscv,cpu-intc"; 1751 interrupt-controller; 1752 #interrupt-cells = <1>; 1753 }; 1754 }; 1755 1756 cpu60: cpu@60 { 1757 compatible = "thead,c920", "riscv"; 1758 device_type = "cpu"; 1759 riscv,isa = "rv64imafdc"; 1760 riscv,isa-base = "rv64i"; 1761 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1762 "zicntr", "zicsr", "zifencei", 1763 "zihpm"; 1764 reg = <60>; 1765 i-cache-block-size = <64>; 1766 i-cache-size = <65536>; 1767 i-cache-sets = <512>; 1768 d-cache-block-size = <64>; 1769 d-cache-size = <65536>; 1770 d-cache-sets = <512>; 1771 next-level-cache = <&l2_cache15>; 1772 mmu-type = "riscv,sv39"; 1773 1774 cpu60_intc: interrupt-controller { 1775 compatible = "riscv,cpu-intc"; 1776 interrupt-controller; 1777 #interrupt-cells = <1>; 1778 }; 1779 }; 1780 1781 cpu61: cpu@61 { 1782 compatible = "thead,c920", "riscv"; 1783 device_type = "cpu"; 1784 riscv,isa = "rv64imafdc"; 1785 riscv,isa-base = "rv64i"; 1786 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1787 "zicntr", "zicsr", "zifencei", 1788 "zihpm"; 1789 reg = <61>; 1790 i-cache-block-size = <64>; 1791 i-cache-size = <65536>; 1792 i-cache-sets = <512>; 1793 d-cache-block-size = <64>; 1794 d-cache-size = <65536>; 1795 d-cache-sets = <512>; 1796 next-level-cache = <&l2_cache15>; 1797 mmu-type = "riscv,sv39"; 1798 1799 cpu61_intc: interrupt-controller { 1800 compatible = "riscv,cpu-intc"; 1801 interrupt-controller; 1802 #interrupt-cells = <1>; 1803 }; 1804 }; 1805 1806 cpu62: cpu@62 { 1807 compatible = "thead,c920", "riscv"; 1808 device_type = "cpu"; 1809 riscv,isa = "rv64imafdc"; 1810 riscv,isa-base = "rv64i"; 1811 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1812 "zicntr", "zicsr", "zifencei", 1813 "zihpm"; 1814 reg = <62>; 1815 i-cache-block-size = <64>; 1816 i-cache-size = <65536>; 1817 i-cache-sets = <512>; 1818 d-cache-block-size = <64>; 1819 d-cache-size = <65536>; 1820 d-cache-sets = <512>; 1821 next-level-cache = <&l2_cache15>; 1822 mmu-type = "riscv,sv39"; 1823 1824 cpu62_intc: interrupt-controller { 1825 compatible = "riscv,cpu-intc"; 1826 interrupt-controller; 1827 #interrupt-cells = <1>; 1828 }; 1829 }; 1830 1831 cpu63: cpu@63 { 1832 compatible = "thead,c920", "riscv"; 1833 device_type = "cpu"; 1834 riscv,isa = "rv64imafdc"; 1835 riscv,isa-base = "rv64i"; 1836 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1837 "zicntr", "zicsr", "zifencei", 1838 "zihpm"; 1839 reg = <63>; 1840 i-cache-block-size = <64>; 1841 i-cache-size = <65536>; 1842 i-cache-sets = <512>; 1843 d-cache-block-size = <64>; 1844 d-cache-size = <65536>; 1845 d-cache-sets = <512>; 1846 next-level-cache = <&l2_cache15>; 1847 mmu-type = "riscv,sv39"; 1848 1849 cpu63_intc: interrupt-controller { 1850 compatible = "riscv,cpu-intc"; 1851 interrupt-controller; 1852 #interrupt-cells = <1>; 1853 }; 1854 }; 1855 1856 l2_cache0: cache-controller-0 { 1857 compatible = "cache"; 1858 cache-block-size = <64>; 1859 cache-level = <2>; 1860 cache-size = <1048576>; 1861 cache-sets = <1024>; 1862 cache-unified; 1863 }; 1864 1865 l2_cache1: cache-controller-1 { 1866 compatible = "cache"; 1867 cache-block-size = <64>; 1868 cache-level = <2>; 1869 cache-size = <1048576>; 1870 cache-sets = <1024>; 1871 cache-unified; 1872 }; 1873 1874 l2_cache2: cache-controller-2 { 1875 compatible = "cache"; 1876 cache-block-size = <64>; 1877 cache-level = <2>; 1878 cache-size = <1048576>; 1879 cache-sets = <1024>; 1880 cache-unified; 1881 }; 1882 1883 l2_cache3: cache-controller-3 { 1884 compatible = "cache"; 1885 cache-block-size = <64>; 1886 cache-level = <2>; 1887 cache-size = <1048576>; 1888 cache-sets = <1024>; 1889 cache-unified; 1890 }; 1891 1892 l2_cache4: cache-controller-4 { 1893 compatible = "cache"; 1894 cache-block-size = <64>; 1895 cache-level = <2>; 1896 cache-size = <1048576>; 1897 cache-sets = <1024>; 1898 cache-unified; 1899 }; 1900 1901 l2_cache5: cache-controller-5 { 1902 compatible = "cache"; 1903 cache-block-size = <64>; 1904 cache-level = <2>; 1905 cache-size = <1048576>; 1906 cache-sets = <1024>; 1907 cache-unified; 1908 }; 1909 1910 l2_cache6: cache-controller-6 { 1911 compatible = "cache"; 1912 cache-block-size = <64>; 1913 cache-level = <2>; 1914 cache-size = <1048576>; 1915 cache-sets = <1024>; 1916 cache-unified; 1917 }; 1918 1919 l2_cache7: cache-controller-7 { 1920 compatible = "cache"; 1921 cache-block-size = <64>; 1922 cache-level = <2>; 1923 cache-size = <1048576>; 1924 cache-sets = <1024>; 1925 cache-unified; 1926 }; 1927 1928 l2_cache8: cache-controller-8 { 1929 compatible = "cache"; 1930 cache-block-size = <64>; 1931 cache-level = <2>; 1932 cache-size = <1048576>; 1933 cache-sets = <1024>; 1934 cache-unified; 1935 }; 1936 1937 l2_cache9: cache-controller-9 { 1938 compatible = "cache"; 1939 cache-block-size = <64>; 1940 cache-level = <2>; 1941 cache-size = <1048576>; 1942 cache-sets = <1024>; 1943 cache-unified; 1944 }; 1945 1946 l2_cache10: cache-controller-10 { 1947 compatible = "cache"; 1948 cache-block-size = <64>; 1949 cache-level = <2>; 1950 cache-size = <1048576>; 1951 cache-sets = <1024>; 1952 cache-unified; 1953 }; 1954 1955 l2_cache11: cache-controller-11 { 1956 compatible = "cache"; 1957 cache-block-size = <64>; 1958 cache-level = <2>; 1959 cache-size = <1048576>; 1960 cache-sets = <1024>; 1961 cache-unified; 1962 }; 1963 1964 l2_cache12: cache-controller-12 { 1965 compatible = "cache"; 1966 cache-block-size = <64>; 1967 cache-level = <2>; 1968 cache-size = <1048576>; 1969 cache-sets = <1024>; 1970 cache-unified; 1971 }; 1972 1973 l2_cache13: cache-controller-13 { 1974 compatible = "cache"; 1975 cache-block-size = <64>; 1976 cache-level = <2>; 1977 cache-size = <1048576>; 1978 cache-sets = <1024>; 1979 cache-unified; 1980 }; 1981 1982 l2_cache14: cache-controller-14 { 1983 compatible = "cache"; 1984 cache-block-size = <64>; 1985 cache-level = <2>; 1986 cache-size = <1048576>; 1987 cache-sets = <1024>; 1988 cache-unified; 1989 }; 1990 1991 l2_cache15: cache-controller-15 { 1992 compatible = "cache"; 1993 cache-block-size = <64>; 1994 cache-level = <2>; 1995 cache-size = <1048576>; 1996 cache-sets = <1024>; 1997 cache-unified; 1998 }; 1999 }; 2000}; 2001