1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 compatible = "sophgo,cv1800b"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 cpus: cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <25000000>; 17 18 cpu0: cpu@0 { 19 compatible = "thead,c906", "riscv"; 20 device_type = "cpu"; 21 reg = <0>; 22 d-cache-block-size = <64>; 23 d-cache-sets = <512>; 24 d-cache-size = <65536>; 25 i-cache-block-size = <64>; 26 i-cache-sets = <128>; 27 i-cache-size = <32768>; 28 mmu-type = "riscv,sv39"; 29 riscv,isa = "rv64imafdc"; 30 riscv,isa-base = "rv64i"; 31 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 32 "zifencei", "zihpm"; 33 34 cpu0_intc: interrupt-controller { 35 compatible = "riscv,cpu-intc"; 36 interrupt-controller; 37 #address-cells = <0>; 38 #interrupt-cells = <1>; 39 }; 40 }; 41 }; 42 43 osc: oscillator { 44 compatible = "fixed-clock"; 45 clock-output-names = "osc_25m"; 46 #clock-cells = <0>; 47 }; 48 49 soc { 50 compatible = "simple-bus"; 51 interrupt-parent = <&plic>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 dma-noncoherent; 55 ranges; 56 57 uart0: serial@4140000 { 58 compatible = "snps,dw-apb-uart"; 59 reg = <0x04140000 0x100>; 60 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 61 clocks = <&osc>; 62 reg-shift = <2>; 63 reg-io-width = <4>; 64 status = "disabled"; 65 }; 66 67 uart1: serial@4150000 { 68 compatible = "snps,dw-apb-uart"; 69 reg = <0x04150000 0x100>; 70 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&osc>; 72 reg-shift = <2>; 73 reg-io-width = <4>; 74 status = "disabled"; 75 }; 76 77 uart2: serial@4160000 { 78 compatible = "snps,dw-apb-uart"; 79 reg = <0x04160000 0x100>; 80 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&osc>; 82 reg-shift = <2>; 83 reg-io-width = <4>; 84 status = "disabled"; 85 }; 86 87 uart3: serial@4170000 { 88 compatible = "snps,dw-apb-uart"; 89 reg = <0x04170000 0x100>; 90 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&osc>; 92 reg-shift = <2>; 93 reg-io-width = <4>; 94 status = "disabled"; 95 }; 96 97 uart4: serial@41c0000 { 98 compatible = "snps,dw-apb-uart"; 99 reg = <0x041c0000 0x100>; 100 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&osc>; 102 reg-shift = <2>; 103 reg-io-width = <4>; 104 status = "disabled"; 105 }; 106 107 plic: interrupt-controller@70000000 { 108 compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; 109 reg = <0x70000000 0x4000000>; 110 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 111 interrupt-controller; 112 #address-cells = <0>; 113 #interrupt-cells = <2>; 114 riscv,ndev = <101>; 115 }; 116 117 clint: timer@74000000 { 118 compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; 119 reg = <0x74000000 0x10000>; 120 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; 121 }; 122 }; 123}; 124