1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 compatible = "sophgo,cv1800b"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 cpus: cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <25000000>; 17 18 cpu0: cpu@0 { 19 compatible = "thead,c906", "riscv"; 20 device_type = "cpu"; 21 reg = <0>; 22 d-cache-block-size = <64>; 23 d-cache-sets = <512>; 24 d-cache-size = <65536>; 25 i-cache-block-size = <64>; 26 i-cache-sets = <128>; 27 i-cache-size = <32768>; 28 mmu-type = "riscv,sv39"; 29 riscv,isa = "rv64imafdc"; 30 riscv,isa-base = "rv64i"; 31 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 32 "zifencei", "zihpm"; 33 34 cpu0_intc: interrupt-controller { 35 compatible = "riscv,cpu-intc"; 36 interrupt-controller; 37 #interrupt-cells = <1>; 38 }; 39 }; 40 }; 41 42 osc: oscillator { 43 compatible = "fixed-clock"; 44 clock-output-names = "osc_25m"; 45 #clock-cells = <0>; 46 }; 47 48 soc { 49 compatible = "simple-bus"; 50 interrupt-parent = <&plic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 dma-noncoherent; 54 ranges; 55 56 uart0: serial@4140000 { 57 compatible = "snps,dw-apb-uart"; 58 reg = <0x04140000 0x100>; 59 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 60 clocks = <&osc>; 61 reg-shift = <2>; 62 reg-io-width = <4>; 63 status = "disabled"; 64 }; 65 66 uart1: serial@4150000 { 67 compatible = "snps,dw-apb-uart"; 68 reg = <0x04150000 0x100>; 69 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 70 clocks = <&osc>; 71 reg-shift = <2>; 72 reg-io-width = <4>; 73 status = "disabled"; 74 }; 75 76 uart2: serial@4160000 { 77 compatible = "snps,dw-apb-uart"; 78 reg = <0x04160000 0x100>; 79 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 80 clocks = <&osc>; 81 reg-shift = <2>; 82 reg-io-width = <4>; 83 status = "disabled"; 84 }; 85 86 uart3: serial@4170000 { 87 compatible = "snps,dw-apb-uart"; 88 reg = <0x04170000 0x100>; 89 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&osc>; 91 reg-shift = <2>; 92 reg-io-width = <4>; 93 status = "disabled"; 94 }; 95 96 uart4: serial@41c0000 { 97 compatible = "snps,dw-apb-uart"; 98 reg = <0x041c0000 0x100>; 99 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&osc>; 101 reg-shift = <2>; 102 reg-io-width = <4>; 103 status = "disabled"; 104 }; 105 106 plic: interrupt-controller@70000000 { 107 compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; 108 reg = <0x70000000 0x4000000>; 109 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 110 interrupt-controller; 111 #address-cells = <0>; 112 #interrupt-cells = <2>; 113 riscv,ndev = <101>; 114 }; 115 116 clint: timer@74000000 { 117 compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; 118 reg = <0x74000000 0x10000>; 119 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; 120 }; 121 }; 122}; 123