xref: /linux/arch/riscv/boot/dts/microchip/mpfs.dtsi (revision 5027ec19f1049a07df5b0a37b1f462514cf2724b)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4/dts-v1/;
5#include "dt-bindings/clock/microchip,mpfs-clock.h"
6
7/ {
8	#address-cells = <2>;
9	#size-cells = <2>;
10	model = "Microchip PolarFire SoC";
11	compatible = "microchip,mpfs";
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			compatible = "sifive,e51", "sifive,rocket0", "riscv";
19			device_type = "cpu";
20			i-cache-block-size = <64>;
21			i-cache-sets = <128>;
22			i-cache-size = <16384>;
23			reg = <0>;
24			riscv,isa = "rv64imac";
25			riscv,isa-base = "rv64i";
26			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
27					       "zihpm";
28			clocks = <&clkcfg CLK_CPU>;
29			status = "disabled";
30
31			cpu0_intc: interrupt-controller {
32				#interrupt-cells = <1>;
33				compatible = "riscv,cpu-intc";
34				interrupt-controller;
35			};
36		};
37
38		cpu1: cpu@1 {
39			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
40			d-cache-block-size = <64>;
41			d-cache-sets = <64>;
42			d-cache-size = <32768>;
43			d-tlb-sets = <1>;
44			d-tlb-size = <32>;
45			device_type = "cpu";
46			i-cache-block-size = <64>;
47			i-cache-sets = <64>;
48			i-cache-size = <32768>;
49			i-tlb-sets = <1>;
50			i-tlb-size = <32>;
51			mmu-type = "riscv,sv39";
52			reg = <1>;
53			riscv,isa = "rv64imafdc";
54			riscv,isa-base = "rv64i";
55			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
56					       "zifencei", "zihpm";
57			clocks = <&clkcfg CLK_CPU>;
58			tlb-split;
59			next-level-cache = <&cctrllr>;
60			status = "okay";
61
62			cpu1_intc: interrupt-controller {
63				#interrupt-cells = <1>;
64				compatible = "riscv,cpu-intc";
65				interrupt-controller;
66			};
67		};
68
69		cpu2: cpu@2 {
70			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
71			d-cache-block-size = <64>;
72			d-cache-sets = <64>;
73			d-cache-size = <32768>;
74			d-tlb-sets = <1>;
75			d-tlb-size = <32>;
76			device_type = "cpu";
77			i-cache-block-size = <64>;
78			i-cache-sets = <64>;
79			i-cache-size = <32768>;
80			i-tlb-sets = <1>;
81			i-tlb-size = <32>;
82			mmu-type = "riscv,sv39";
83			reg = <2>;
84			riscv,isa = "rv64imafdc";
85			riscv,isa-base = "rv64i";
86			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
87					       "zifencei", "zihpm";
88			clocks = <&clkcfg CLK_CPU>;
89			tlb-split;
90			next-level-cache = <&cctrllr>;
91			status = "okay";
92
93			cpu2_intc: interrupt-controller {
94				#interrupt-cells = <1>;
95				compatible = "riscv,cpu-intc";
96				interrupt-controller;
97			};
98		};
99
100		cpu3: cpu@3 {
101			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
102			d-cache-block-size = <64>;
103			d-cache-sets = <64>;
104			d-cache-size = <32768>;
105			d-tlb-sets = <1>;
106			d-tlb-size = <32>;
107			device_type = "cpu";
108			i-cache-block-size = <64>;
109			i-cache-sets = <64>;
110			i-cache-size = <32768>;
111			i-tlb-sets = <1>;
112			i-tlb-size = <32>;
113			mmu-type = "riscv,sv39";
114			reg = <3>;
115			riscv,isa = "rv64imafdc";
116			riscv,isa-base = "rv64i";
117			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
118					       "zifencei", "zihpm";
119			clocks = <&clkcfg CLK_CPU>;
120			tlb-split;
121			next-level-cache = <&cctrllr>;
122			status = "okay";
123
124			cpu3_intc: interrupt-controller {
125				#interrupt-cells = <1>;
126				compatible = "riscv,cpu-intc";
127				interrupt-controller;
128			};
129		};
130
131		cpu4: cpu@4 {
132			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
133			d-cache-block-size = <64>;
134			d-cache-sets = <64>;
135			d-cache-size = <32768>;
136			d-tlb-sets = <1>;
137			d-tlb-size = <32>;
138			device_type = "cpu";
139			i-cache-block-size = <64>;
140			i-cache-sets = <64>;
141			i-cache-size = <32768>;
142			i-tlb-sets = <1>;
143			i-tlb-size = <32>;
144			mmu-type = "riscv,sv39";
145			reg = <4>;
146			riscv,isa = "rv64imafdc";
147			riscv,isa-base = "rv64i";
148			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
149					       "zifencei", "zihpm";
150			clocks = <&clkcfg CLK_CPU>;
151			tlb-split;
152			next-level-cache = <&cctrllr>;
153			status = "okay";
154			cpu4_intc: interrupt-controller {
155				#interrupt-cells = <1>;
156				compatible = "riscv,cpu-intc";
157				interrupt-controller;
158			};
159		};
160
161		cpu-map {
162			cluster0 {
163				core0 {
164					cpu = <&cpu0>;
165				};
166
167				core1 {
168					cpu = <&cpu1>;
169				};
170
171				core2 {
172					cpu = <&cpu2>;
173				};
174
175				core3 {
176					cpu = <&cpu3>;
177				};
178
179				core4 {
180					cpu = <&cpu4>;
181				};
182			};
183		};
184	};
185
186	refclk: mssrefclk {
187		compatible = "fixed-clock";
188		#clock-cells = <0>;
189	};
190
191	syscontroller: syscontroller {
192		compatible = "microchip,mpfs-sys-controller";
193		mboxes = <&mbox 0>;
194	};
195
196	soc {
197		#address-cells = <2>;
198		#size-cells = <2>;
199		compatible = "simple-bus";
200		ranges;
201
202		cctrllr: cache-controller@2010000 {
203			compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
204			reg = <0x0 0x2010000 0x0 0x1000>;
205			cache-block-size = <64>;
206			cache-level = <2>;
207			cache-sets = <1024>;
208			cache-size = <2097152>;
209			cache-unified;
210			interrupt-parent = <&plic>;
211			interrupts = <1>, <3>, <4>, <2>;
212		};
213
214		clint: clint@2000000 {
215			compatible = "sifive,fu540-c000-clint", "sifive,clint0";
216			reg = <0x0 0x2000000 0x0 0xC000>;
217			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
218					      <&cpu1_intc 3>, <&cpu1_intc 7>,
219					      <&cpu2_intc 3>, <&cpu2_intc 7>,
220					      <&cpu3_intc 3>, <&cpu3_intc 7>,
221					      <&cpu4_intc 3>, <&cpu4_intc 7>;
222		};
223
224		plic: interrupt-controller@c000000 {
225			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
226			reg = <0x0 0xc000000 0x0 0x4000000>;
227			#address-cells = <0>;
228			#interrupt-cells = <1>;
229			interrupt-controller;
230			interrupts-extended = <&cpu0_intc 11>,
231					      <&cpu1_intc 11>, <&cpu1_intc 9>,
232					      <&cpu2_intc 11>, <&cpu2_intc 9>,
233					      <&cpu3_intc 11>, <&cpu3_intc 9>,
234					      <&cpu4_intc 11>, <&cpu4_intc 9>;
235			riscv,ndev = <186>;
236		};
237
238		pdma: dma-controller@3000000 {
239			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
240			reg = <0x0 0x3000000 0x0 0x8000>;
241			interrupt-parent = <&plic>;
242			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
243			dma-channels = <4>;
244			#dma-cells = <1>;
245		};
246
247		clkcfg: clkcfg@20002000 {
248			compatible = "microchip,mpfs-clkcfg";
249			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
250			clocks = <&refclk>;
251			#clock-cells = <1>;
252			#reset-cells = <1>;
253		};
254
255		ccc_se: clock-controller@38010000 {
256			compatible = "microchip,mpfs-ccc";
257			reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
258			      <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
259			#clock-cells = <1>;
260			status = "disabled";
261		};
262
263		ccc_ne: clock-controller@38040000 {
264			compatible = "microchip,mpfs-ccc";
265			reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
266			      <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
267			#clock-cells = <1>;
268			status = "disabled";
269		};
270
271		ccc_nw: clock-controller@38100000 {
272			compatible = "microchip,mpfs-ccc";
273			reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
274			      <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
275			#clock-cells = <1>;
276			status = "disabled";
277		};
278
279		ccc_sw: clock-controller@38400000 {
280			compatible = "microchip,mpfs-ccc";
281			reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
282			      <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
283			#clock-cells = <1>;
284			status = "disabled";
285		};
286
287		mmuart0: serial@20000000 {
288			compatible = "ns16550a";
289			reg = <0x0 0x20000000 0x0 0x400>;
290			reg-io-width = <4>;
291			reg-shift = <2>;
292			interrupt-parent = <&plic>;
293			interrupts = <90>;
294			current-speed = <115200>;
295			clocks = <&clkcfg CLK_MMUART0>;
296			status = "disabled"; /* Reserved for the HSS */
297		};
298
299		mmuart1: serial@20100000 {
300			compatible = "ns16550a";
301			reg = <0x0 0x20100000 0x0 0x400>;
302			reg-io-width = <4>;
303			reg-shift = <2>;
304			interrupt-parent = <&plic>;
305			interrupts = <91>;
306			current-speed = <115200>;
307			clocks = <&clkcfg CLK_MMUART1>;
308			status = "disabled";
309		};
310
311		mmuart2: serial@20102000 {
312			compatible = "ns16550a";
313			reg = <0x0 0x20102000 0x0 0x400>;
314			reg-io-width = <4>;
315			reg-shift = <2>;
316			interrupt-parent = <&plic>;
317			interrupts = <92>;
318			current-speed = <115200>;
319			clocks = <&clkcfg CLK_MMUART2>;
320			status = "disabled";
321		};
322
323		mmuart3: serial@20104000 {
324			compatible = "ns16550a";
325			reg = <0x0 0x20104000 0x0 0x400>;
326			reg-io-width = <4>;
327			reg-shift = <2>;
328			interrupt-parent = <&plic>;
329			interrupts = <93>;
330			current-speed = <115200>;
331			clocks = <&clkcfg CLK_MMUART3>;
332			status = "disabled";
333		};
334
335		mmuart4: serial@20106000 {
336			compatible = "ns16550a";
337			reg = <0x0 0x20106000 0x0 0x400>;
338			reg-io-width = <4>;
339			reg-shift = <2>;
340			interrupt-parent = <&plic>;
341			interrupts = <94>;
342			clocks = <&clkcfg CLK_MMUART4>;
343			current-speed = <115200>;
344			status = "disabled";
345		};
346
347		/* Common node entry for emmc/sd */
348		mmc: mmc@20008000 {
349			compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
350			reg = <0x0 0x20008000 0x0 0x1000>;
351			interrupt-parent = <&plic>;
352			interrupts = <88>;
353			clocks = <&clkcfg CLK_MMC>;
354			max-frequency = <200000000>;
355			status = "disabled";
356		};
357
358		spi0: spi@20108000 {
359			compatible = "microchip,mpfs-spi";
360			#address-cells = <1>;
361			#size-cells = <0>;
362			reg = <0x0 0x20108000 0x0 0x1000>;
363			interrupt-parent = <&plic>;
364			interrupts = <54>;
365			clocks = <&clkcfg CLK_SPI0>;
366			status = "disabled";
367		};
368
369		spi1: spi@20109000 {
370			compatible = "microchip,mpfs-spi";
371			#address-cells = <1>;
372			#size-cells = <0>;
373			reg = <0x0 0x20109000 0x0 0x1000>;
374			interrupt-parent = <&plic>;
375			interrupts = <55>;
376			clocks = <&clkcfg CLK_SPI1>;
377			status = "disabled";
378		};
379
380		qspi: spi@21000000 {
381			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
382			#address-cells = <1>;
383			#size-cells = <0>;
384			reg = <0x0 0x21000000 0x0 0x1000>;
385			interrupt-parent = <&plic>;
386			interrupts = <85>;
387			clocks = <&clkcfg CLK_QSPI>;
388			status = "disabled";
389		};
390
391		i2c0: i2c@2010a000 {
392			compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
393			reg = <0x0 0x2010a000 0x0 0x1000>;
394			#address-cells = <1>;
395			#size-cells = <0>;
396			interrupt-parent = <&plic>;
397			interrupts = <58>;
398			clocks = <&clkcfg CLK_I2C0>;
399			clock-frequency = <100000>;
400			status = "disabled";
401		};
402
403		i2c1: i2c@2010b000 {
404			compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
405			reg = <0x0 0x2010b000 0x0 0x1000>;
406			#address-cells = <1>;
407			#size-cells = <0>;
408			interrupt-parent = <&plic>;
409			interrupts = <61>;
410			clocks = <&clkcfg CLK_I2C1>;
411			clock-frequency = <100000>;
412			status = "disabled";
413		};
414
415		can0: can@2010c000 {
416			compatible = "microchip,mpfs-can";
417			reg = <0x0 0x2010c000 0x0 0x1000>;
418			clocks = <&clkcfg CLK_CAN0>;
419			interrupt-parent = <&plic>;
420			interrupts = <56>;
421			status = "disabled";
422		};
423
424		can1: can@2010d000 {
425			compatible = "microchip,mpfs-can";
426			reg = <0x0 0x2010d000 0x0 0x1000>;
427			clocks = <&clkcfg CLK_CAN1>;
428			interrupt-parent = <&plic>;
429			interrupts = <57>;
430			status = "disabled";
431		};
432
433		mac0: ethernet@20110000 {
434			compatible = "microchip,mpfs-macb", "cdns,macb";
435			reg = <0x0 0x20110000 0x0 0x2000>;
436			#address-cells = <1>;
437			#size-cells = <0>;
438			interrupt-parent = <&plic>;
439			interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
440			local-mac-address = [00 00 00 00 00 00];
441			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
442			clock-names = "pclk", "hclk";
443			resets = <&clkcfg CLK_MAC0>;
444			status = "disabled";
445		};
446
447		mac1: ethernet@20112000 {
448			compatible = "microchip,mpfs-macb", "cdns,macb";
449			reg = <0x0 0x20112000 0x0 0x2000>;
450			#address-cells = <1>;
451			#size-cells = <0>;
452			interrupt-parent = <&plic>;
453			interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
454			local-mac-address = [00 00 00 00 00 00];
455			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
456			clock-names = "pclk", "hclk";
457			resets = <&clkcfg CLK_MAC1>;
458			status = "disabled";
459		};
460
461		gpio0: gpio@20120000 {
462			compatible = "microchip,mpfs-gpio";
463			reg = <0x0 0x20120000 0x0 0x1000>;
464			interrupt-parent = <&plic>;
465			interrupt-controller;
466			#interrupt-cells = <1>;
467			clocks = <&clkcfg CLK_GPIO0>;
468			gpio-controller;
469			#gpio-cells = <2>;
470			status = "disabled";
471		};
472
473		gpio1: gpio@20121000 {
474			compatible = "microchip,mpfs-gpio";
475			reg = <0x0 0x20121000 0x0 0x1000>;
476			interrupt-parent = <&plic>;
477			interrupt-controller;
478			#interrupt-cells = <1>;
479			clocks = <&clkcfg CLK_GPIO1>;
480			gpio-controller;
481			#gpio-cells = <2>;
482			status = "disabled";
483		};
484
485		gpio2: gpio@20122000 {
486			compatible = "microchip,mpfs-gpio";
487			reg = <0x0 0x20122000 0x0 0x1000>;
488			interrupt-parent = <&plic>;
489			interrupt-controller;
490			#interrupt-cells = <1>;
491			clocks = <&clkcfg CLK_GPIO2>;
492			gpio-controller;
493			#gpio-cells = <2>;
494			status = "disabled";
495		};
496
497		rtc: rtc@20124000 {
498			compatible = "microchip,mpfs-rtc";
499			reg = <0x0 0x20124000 0x0 0x1000>;
500			interrupt-parent = <&plic>;
501			interrupts = <80>, <81>;
502			clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
503			clock-names = "rtc", "rtcref";
504			status = "disabled";
505		};
506
507		usb: usb@20201000 {
508			compatible = "microchip,mpfs-musb";
509			reg = <0x0 0x20201000 0x0 0x1000>;
510			interrupt-parent = <&plic>;
511			interrupts = <86>, <87>;
512			clocks = <&clkcfg CLK_USB>;
513			interrupt-names = "dma","mc";
514			status = "disabled";
515		};
516
517		mbox: mailbox@37020000 {
518			compatible = "microchip,mpfs-mailbox";
519			reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
520			      <0x0 0x37020800 0x0 0x100>;
521			interrupt-parent = <&plic>;
522			interrupts = <96>;
523			#mbox-cells = <1>;
524			status = "disabled";
525		};
526	};
527};
528