xref: /linux/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2022 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-sev-kit-fabric.dtsi"
8
9/ {
10	#address-cells = <2>;
11	#size-cells = <2>;
12	model = "Microchip PolarFire-SoC SEV Kit";
13	compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
14
15	aliases {
16		ethernet0 = &mac1;
17		serial0 = &mmuart0;
18		serial1 = &mmuart1;
19		serial2 = &mmuart2;
20		serial3 = &mmuart3;
21		serial4 = &mmuart4;
22	};
23
24	chosen {
25		stdout-path = "serial1:115200n8";
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		fabricbuf0ddrc: buffer@80000000 {
34			compatible = "shared-dma-pool";
35			reg = <0x0 0x80000000 0x0 0x2000000>;
36		};
37
38		fabricbuf1ddrnc: buffer@c4000000 {
39			compatible = "shared-dma-pool";
40			reg = <0x0 0xc4000000 0x0 0x4000000>;
41		};
42
43		fabricbuf2ddrncwcb: buffer@d4000000 {
44			compatible = "shared-dma-pool";
45			reg = <0x0 0xd4000000 0x0 0x4000000>;
46		};
47	};
48
49	ddrc_cache: memory@1000000000 {
50		device_type = "memory";
51		reg = <0x10 0x0 0x0 0x76000000>;
52	};
53};
54
55&i2c0 {
56	status = "okay";
57};
58
59&irqmux {
60	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
61			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
62			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
63			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
64			<12 &plic 25>, <13 &plic 26>,
65
66			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
67			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
68			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
69			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
70			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
71			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
72			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
73			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
74
75			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
76			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
77			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
78			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
79			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
80			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
81			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
82			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
83			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
84			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
85			<94 &plic 53>, <95 &plic 53>;
86};
87
88&gpio2 {
89	status = "okay";
90};
91
92&mac0 {
93	status = "okay";
94	phy-mode = "sgmii";
95	phy-handle = <&phy0>;
96	phy1: ethernet-phy@9 {
97		reg = <9>;
98	};
99	phy0: ethernet-phy@8 {
100		reg = <8>;
101	};
102};
103
104&mac1 {
105	status = "okay";
106	phy-mode = "sgmii";
107	phy-handle = <&phy1>;
108};
109
110&mbox {
111	status = "okay";
112};
113
114&mmc {
115	status = "okay";
116	bus-width = <4>;
117	disable-wp;
118	cap-sd-highspeed;
119	cap-mmc-highspeed;
120	mmc-ddr-1_8v;
121	mmc-hs200-1_8v;
122	sd-uhs-sdr12;
123	sd-uhs-sdr25;
124	sd-uhs-sdr50;
125	sd-uhs-sdr104;
126};
127
128&mmuart1 {
129	status = "okay";
130};
131
132&mmuart2 {
133	status = "okay";
134};
135
136&mmuart3 {
137	status = "okay";
138};
139
140&mmuart4 {
141	status = "okay";
142};
143
144&refclk {
145	clock-frequency = <125000000>;
146};
147
148&rtc {
149	status = "okay";
150};
151
152&syscontroller {
153	status = "okay";
154};
155
156&usb {
157	status = "okay";
158	dr_mode = "otg";
159};
160