xref: /linux/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020-2022 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs.dtsi"
7#include "mpfs-polarberry-fabric.dtsi"
8
9/ {
10	model = "Sundance PolarBerry";
11	compatible = "sundance,polarberry", "microchip,mpfs";
12
13	aliases {
14		ethernet0 = &mac1;
15		serial0 = &mmuart0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	ddrc_cache_lo: memory@80000000 {
23		device_type = "memory";
24		reg = <0x0 0x80000000 0x0 0x2e000000>;
25	};
26
27	ddrc_cache_hi: memory@1000000000 {
28		device_type = "memory";
29		reg = <0x10 0x00000000 0x0 0xC0000000>;
30	};
31};
32
33&irqmux {
34	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
35			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
36			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
37			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
38			<12 &plic 25>, <13 &plic 26>,
39
40			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
41			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
42			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
43			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
44			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
45			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
46			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
47			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
48
49			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
50			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
51			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
52			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
53			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
54			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
55			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
56			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
57			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
58			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
59			<94 &plic 53>, <95 &plic 53>;
60};
61
62/*
63 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
64 * board.
65 */
66&mac0 {
67	phy-mode = "sgmii";
68	phy-handle = <&phy0>;
69	status = "disabled";
70};
71
72&mac1 {
73	phy-mode = "sgmii";
74	phy-handle = <&phy1>;
75	status = "okay";
76
77	phy1: ethernet-phy@5 {
78		reg = <5>;
79	};
80
81	phy0: ethernet-phy@4 {
82		reg = <4>;
83	};
84};
85
86&mbox {
87	status = "okay";
88};
89
90&mmc {
91	bus-width = <4>;
92	disable-wp;
93	cap-sd-highspeed;
94	cap-mmc-highspeed;
95	mmc-ddr-1_8v;
96	mmc-hs200-1_8v;
97	sd-uhs-sdr12;
98	sd-uhs-sdr25;
99	sd-uhs-sdr50;
100	sd-uhs-sdr104;
101	status = "okay";
102};
103
104&mmuart0 {
105	status = "okay";
106};
107
108&refclk {
109	clock-frequency = <125000000>;
110};
111
112&rtc {
113	status = "okay";
114};
115
116&syscontroller {
117	status = "okay";
118};
119