xref: /linux/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
5 * Rewritten to use includes:
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
7 */
8/dts-v1/;
9
10#include "mpfs.dtsi"
11#include "mpfs-m100pfs-fabric.dtsi"
12
13/* Clock frequency (in Hz) of the rtcclk */
14#define MTIMER_FREQ	1000000
15
16/ {
17	model = "Aries Embedded M100PFEVPS";
18	compatible = "aries,m100pfsevp", "microchip,mpfs";
19
20	aliases {
21		ethernet0 = &mac0;
22		ethernet1 = &mac1;
23		serial0 = &mmuart0;
24		serial1 = &mmuart1;
25		serial2 = &mmuart2;
26		serial3 = &mmuart3;
27		serial4 = &mmuart4;
28		gpio0 = &gpio0;
29		gpio1 = &gpio2;
30	};
31
32	chosen {
33		stdout-path = "serial1:115200n8";
34	};
35
36	cpus {
37		timebase-frequency = <MTIMER_FREQ>;
38	};
39
40	ddrc_cache_lo: memory@80000000 {
41		device_type = "memory";
42		reg = <0x0 0x80000000 0x0 0x40000000>;
43	};
44	ddrc_cache_hi: memory@1040000000 {
45		device_type = "memory";
46		reg = <0x10 0x40000000 0x0 0x40000000>;
47	};
48};
49
50&can0 {
51	status = "okay";
52};
53
54&i2c0 {
55	status = "okay";
56};
57
58&i2c1 {
59	status = "okay";
60};
61
62&gpio0 {
63	interrupts = <13>, <14>, <15>, <16>,
64		     <17>, <18>, <19>, <20>,
65		     <21>, <22>, <23>, <24>,
66		     <25>, <26>;
67	ngpios = <14>;
68	status = "okay";
69
70	pmic-irq-hog {
71		gpio-hog;
72		gpios = <13 0>;
73		input;
74	};
75
76	/* Set to low for eMMC, high for SD-card */
77	mmc-sel-hog {
78		gpio-hog;
79		gpios = <12 0>;
80		output-high;
81	};
82};
83
84&gpio2 {
85	interrupts = <13>, <14>, <15>, <16>,
86		     <17>, <18>, <19>, <20>,
87		     <21>, <22>, <23>, <24>,
88		     <25>, <26>, <27>, <28>,
89		     <29>, <30>, <31>, <32>,
90		     <33>, <34>, <35>, <36>,
91		     <37>, <38>, <39>, <40>,
92		     <41>, <42>, <43>, <44>;
93	status = "okay";
94};
95
96&mac0 {
97	status = "okay";
98	phy-mode = "gmii";
99	phy-handle = <&phy0>;
100	phy0: ethernet-phy@0 {
101		reg = <0>;
102	};
103};
104
105&mac1 {
106	status = "okay";
107	phy-mode = "gmii";
108	phy-handle = <&phy1>;
109	phy1: ethernet-phy@0 {
110		reg = <0>;
111	};
112};
113
114&mbox {
115	status = "okay";
116};
117
118&mmc {
119	max-frequency = <50000000>;
120	bus-width = <4>;
121	cap-mmc-highspeed;
122	cap-sd-highspeed;
123	no-1-8-v;
124	sd-uhs-sdr12;
125	sd-uhs-sdr25;
126	sd-uhs-sdr50;
127	sd-uhs-sdr104;
128	disable-wp;
129	status = "okay";
130};
131
132&mmuart1 {
133	status = "okay";
134};
135
136&mmuart2 {
137	status = "okay";
138};
139
140&mmuart3 {
141	status = "okay";
142};
143
144&mmuart4 {
145	status = "okay";
146};
147
148&pcie {
149	status = "okay";
150};
151
152&qspi {
153	status = "okay";
154};
155
156&refclk {
157	clock-frequency = <125000000>;
158};
159
160&rtc {
161	status = "okay";
162};
163
164&spi0 {
165	status = "okay";
166};
167
168&spi1 {
169	status = "okay";
170};
171
172&syscontroller {
173	status = "okay";
174};
175
176&usb {
177	status = "okay";
178	dr_mode = "host";
179};
180