1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "mpfs.dtsi" 7#include "mpfs-icicle-kit-fabric.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/leds/common.h> 10 11/ { 12 model = "Microchip PolarFire-SoC Icicle Kit"; 13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", 14 "microchip,mpfs"; 15 16 aliases { 17 ethernet0 = &mac1; 18 serial0 = &mmuart0; 19 serial1 = &mmuart1; 20 serial2 = &mmuart2; 21 serial3 = &mmuart3; 22 serial4 = &mmuart4; 23 }; 24 25 chosen { 26 stdout-path = "serial1:115200n8"; 27 }; 28 29 leds { 30 compatible = "gpio-leds"; 31 32 led-1 { 33 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 34 color = <LED_COLOR_ID_RED>; 35 label = "led1"; 36 }; 37 38 led-2 { 39 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 40 color = <LED_COLOR_ID_RED>; 41 label = "led2"; 42 }; 43 44 led-3 { 45 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; 46 color = <LED_COLOR_ID_AMBER>; 47 label = "led3"; 48 }; 49 50 led-4 { 51 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 52 color = <LED_COLOR_ID_AMBER>; 53 label = "led4"; 54 }; 55 }; 56 57 ddrc_cache_lo: memory@80000000 { 58 device_type = "memory"; 59 reg = <0x0 0x80000000 0x0 0x40000000>; 60 status = "okay"; 61 }; 62 63 ddrc_cache_hi: memory@1040000000 { 64 device_type = "memory"; 65 reg = <0x10 0x40000000 0x0 0x40000000>; 66 status = "okay"; 67 }; 68 69 reserved-memory { 70 #address-cells = <2>; 71 #size-cells = <2>; 72 ranges; 73 74 hss_payload: region@BFC00000 { 75 reg = <0x0 0xBFC00000 0x0 0x400000>; 76 no-map; 77 }; 78 }; 79}; 80 81&core_pwm0 { 82 status = "okay"; 83}; 84 85&gpio2 { 86 interrupts = <53>, <53>, <53>, <53>, 87 <53>, <53>, <53>, <53>, 88 <53>, <53>, <53>, <53>, 89 <53>, <53>, <53>, <53>, 90 <53>, <53>, <53>, <53>, 91 <53>, <53>, <53>, <53>, 92 <53>, <53>, <53>, <53>, 93 <53>, <53>, <53>, <53>; 94 status = "okay"; 95}; 96 97&i2c0 { 98 status = "okay"; 99}; 100 101&i2c1 { 102 status = "okay"; 103 104 power-monitor@10 { 105 compatible = "microchip,pac1934"; 106 reg = <0x10>; 107 108 #address-cells = <1>; 109 #size-cells = <0>; 110 111 channel@1 { 112 reg = <0x1>; 113 shunt-resistor-micro-ohms = <10000>; 114 label = "VDDREG"; 115 }; 116 117 channel@2 { 118 reg = <0x2>; 119 shunt-resistor-micro-ohms = <10000>; 120 label = "VDDA25"; 121 }; 122 123 channel@3 { 124 reg = <0x3>; 125 shunt-resistor-micro-ohms = <10000>; 126 label = "VDD25"; 127 }; 128 129 channel@4 { 130 reg = <0x4>; 131 shunt-resistor-micro-ohms = <10000>; 132 label = "VDDA_REG"; 133 }; 134 }; 135}; 136 137&i2c2 { 138 status = "okay"; 139}; 140 141&mac0 { 142 phy-mode = "sgmii"; 143 phy-handle = <&phy0>; 144 status = "okay"; 145}; 146 147&mac1 { 148 phy-mode = "sgmii"; 149 phy-handle = <&phy1>; 150 status = "okay"; 151 152 phy1: ethernet-phy@9 { 153 reg = <9>; 154 }; 155 156 phy0: ethernet-phy@8 { 157 reg = <8>; 158 }; 159}; 160 161&mbox { 162 status = "okay"; 163}; 164 165&mmc { 166 bus-width = <4>; 167 disable-wp; 168 cap-sd-highspeed; 169 cap-mmc-highspeed; 170 mmc-ddr-1_8v; 171 mmc-hs200-1_8v; 172 sd-uhs-sdr12; 173 sd-uhs-sdr25; 174 sd-uhs-sdr50; 175 sd-uhs-sdr104; 176 status = "okay"; 177}; 178 179&mmuart1 { 180 status = "okay"; 181}; 182 183&mmuart2 { 184 status = "okay"; 185}; 186 187&mmuart3 { 188 status = "okay"; 189}; 190 191&mmuart4 { 192 status = "okay"; 193}; 194 195&pcie { 196 status = "okay"; 197}; 198 199&qspi { 200 status = "okay"; 201}; 202 203&refclk { 204 clock-frequency = <125000000>; 205}; 206 207&refclk_ccc { 208 clock-frequency = <50000000>; 209}; 210 211&rtc { 212 status = "okay"; 213}; 214 215&spi0 { 216 status = "okay"; 217}; 218 219&spi1 { 220 status = "okay"; 221}; 222 223&syscontroller { 224 status = "okay"; 225}; 226 227&syscontroller_qspi { 228 /* 229 * The flash *is* there, but Icicle kits that have engineering sample 230 * silicon (write?) access to this flash to non-functional. The system 231 * controller itself can actually access it, but the MSS cannot write 232 * an image there. Instantiating a coreQSPI in the fabric & connecting 233 * it to the flash instead should work though. Pre-production or later 234 * silicon does not have this issue. 235 */ 236 status = "disabled"; 237 238 sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT 239 compatible = "jedec,spi-nor"; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 spi-max-frequency = <20000000>; 243 spi-rx-bus-width = <1>; 244 reg = <0>; 245 }; 246}; 247 248&usb { 249 status = "okay"; 250 dr_mode = "host"; 251}; 252