1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/ { 5 core_pwm0: pwm@40000000 { 6 compatible = "microchip,corepwm-rtl-v4"; 7 reg = <0x0 0x40000000 0x0 0xF0>; 8 microchip,sync-update-mask = /bits/ 32 <0>; 9 #pwm-cells = <3>; 10 clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; 11 status = "disabled"; 12 }; 13 14 i2c2: i2c@40000200 { 15 compatible = "microchip,corei2c-rtl-v7"; 16 reg = <0x0 0x40000200 0x0 0x100>; 17 #address-cells = <1>; 18 #size-cells = <0>; 19 clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; 20 interrupt-parent = <&plic>; 21 interrupts = <122>; 22 clock-frequency = <100000>; 23 status = "disabled"; 24 }; 25 26 ihc: mailbox { 27 compatible = "microchip,sbi-ipc"; 28 interrupt-parent = <&plic>; 29 interrupts = <180>, <179>, <178>, <177>; 30 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 31 #mbox-cells = <1>; 32 status = "disabled"; 33 }; 34 35 mailbox@50000000 { 36 compatible = "microchip,miv-ihc-rtl-v2"; 37 reg = <0x0 0x50000000 0x0 0x1c000>; 38 interrupt-parent = <&plic>; 39 interrupts = <180>, <179>, <178>, <177>; 40 interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; 41 #mbox-cells = <1>; 42 microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; 43 status = "disabled"; 44 }; 45 46 pcie: pcie@3000000000 { 47 compatible = "microchip,pcie-host-1.0"; 48 #address-cells = <0x3>; 49 #interrupt-cells = <0x1>; 50 #size-cells = <0x2>; 51 device_type = "pci"; 52 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, 53 <0x0 0x4300a000 0x0 0x2000>; 54 reg-names = "cfg", "bridge", "ctrl"; 55 bus-range = <0x0 0x7f>; 56 interrupt-parent = <&plic>; 57 interrupts = <119>; 58 interrupt-map = <0 0 0 1 &pcie_intc 0>, 59 <0 0 0 2 &pcie_intc 1>, 60 <0 0 0 3 &pcie_intc 2>, 61 <0 0 0 4 &pcie_intc 3>; 62 interrupt-map-mask = <0 0 0 7>; 63 clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; 64 clock-names = "fic1", "fic3"; 65 ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; 66 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; 67 msi-parent = <&pcie>; 68 msi-controller; 69 status = "disabled"; 70 pcie_intc: interrupt-controller { 71 #address-cells = <0>; 72 #interrupt-cells = <1>; 73 interrupt-controller; 74 }; 75 }; 76 77 refclk_ccc: clock-cccref { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 }; 81}; 82 83&ccc_nw { 84 clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, 85 <&refclk_ccc>, <&refclk_ccc>; 86 clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", 87 "dll0_ref", "dll1_ref"; 88 status = "okay"; 89}; 90